On 17-02-2025 22:56, Simona Vetter wrote:
On Mon, Feb 17, 2025 at 12:08:08PM +0200, Pekka Paalanen wrote:
Hi Arun,
this whole series seems to be missing all the UAPI docs for the DRM
ReST files, e.g. drm-kms.rst. The UAPI header doc comments are not a
replacement for them, I would assume both
On 17-02-2025 15:38, Pekka Paalanen wrote:
Hi Arun,
this whole series seems to be missing all the UAPI docs for the DRM
ReST files, e.g. drm-kms.rst. The UAPI header doc comments are not a
replacement for them, I would assume both are a requirement.
Without the ReST docs it is really difficult
== Series Details ==
Series: series starting with [1/2] drm/{i915,xe}: Move intel_pch under display
URL : https://patchwork.freedesktop.org/series/144988/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16147 -> Patchwork_144988v1
== Series Details ==
Series: series starting with [1/2] drm/{i915,xe}: Move intel_pch under display
URL : https://patchwork.freedesktop.org/series/144988/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: series starting with [1/2] drm/{i915,xe}: Move intel_pch under display
URL : https://patchwork.freedesktop.org/series/144988/
State : warning
== Summary ==
Error: dim checkpatch failed
0af56b324b0e drm/{i915,xe}: Move intel_pch under display
-:36: WARNING:FILE_PATH
Now that intel_pch lives under display, let's begin its
conversion towards struct intel_display.
Move the pch_type to inside intel_display and convert the
callers.
While doing it, sort intel_display_core.h include list
alphabetically.
Signed-off-by: Rodrigo Vivi
---
.../gpu/drm/i915/display/in
The only usage of the "PCH" infra is to detect which South Display
Engine we should be using. Move it under display so we can convert
all its callers towards intel_display struct later.
No functional or code change.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile
== Series Details ==
Series: drm/i915/dp: Fix 128b/132b modeset issues
URL : https://patchwork.freedesktop.org/series/144984/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16146 -> Patchwork_144984v1
Summary
---
**SU
== Series Details ==
Series: drm/i915/dp: Fix 128b/132b modeset issues
URL : https://patchwork.freedesktop.org/series/144984/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:
== Series Details ==
Series: drm/i915/dp: Fix 128b/132b modeset issues
URL : https://patchwork.freedesktop.org/series/144984/
State : warning
== Summary ==
Error: dim checkpatch failed
bbebbc2407b5 drm/i915/dp: Fix error handling during 128b/132b link training
-:55: WARNING:MISSING_FIXES_TAG:
During disabling the transcoder in DP 128b/132b mode (both in case of an
MST master transcoder and in case of SST) the transcoder function must
be first disabled without changing any other field in the register (in
particular leaving the DDI port and mode select fields unchanged) and
clearing the D
At the end of a 128b/132b link training sequence, the HW expects the
transcoder training pattern to be set to TPS2 and from that to normal
mode (disabling the training pattern). Transitioning from TPS1 directly
to normal mode leaves the transcoder in a stuck state, resulting in
page-flip timeouts l
This patchset fixes an issue during the error handling of a 128b/132b
mode link training failure and fixes the transcoder function disabling
sequence in 128b/132b SST mode.
Cc: Jani Nikula
Imre Deak (2):
drm/i915/dp: Fix error handling during 128b/132b link training
drm/i915/dp: Fix disablin
On Mon, Feb 17, 2025 at 06:26:17PM +0100, Simona Vetter wrote:
> On Mon, Feb 17, 2025 at 12:08:08PM +0200, Pekka Paalanen wrote:
> > Hi Arun,
> >
> > this whole series seems to be missing all the UAPI docs for the DRM
> > ReST files, e.g. drm-kms.rst. The UAPI header doc comments are not a
> > rep
== Series Details ==
Series: Improve type-safety on POWER_DOMAIN_*() macros (rev3)
URL : https://patchwork.freedesktop.org/series/144726/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16146 -> Patchwork_144726v3
Summary
---
== Series Details ==
Series: Improve type-safety on POWER_DOMAIN_*() macros (rev3)
URL : https://patchwork.freedesktop.org/series/144726/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Quoting Ville Syrjälä (2025-02-17 17:46:27-03:00)
>On Mon, Feb 17, 2025 at 05:34:28PM -0300, Gustavo Sousa wrote:
>> We already have other functions to get power domain for other things
>> (i.e. intel_display_power_*_domain()). Convert POWER_DOMAIN_*() macros
>> to the same standard.
>>
>> Cc: Vil
On Mon, Feb 17, 2025 at 05:34:27PM -0300, Gustavo Sousa wrote:
> In the hope of contributing to type safety in our code, let's ensure
> that the type returned by the POWER_DOMAIN_*() macros is always of type
> enum intel_display_power_domain.
>
> v2:
> - Remove accidental +1 in definition of POW
On Mon, Feb 17, 2025 at 05:34:26PM -0300, Gustavo Sousa wrote:
> Although we have comments in intel_display_limits.h saying that the
> code expects PIPE_A and TRANSCODER_A to be zero, it doesn't hurt to add
> them as explicit base values for calculating the power domain offset in
> POWER_DOMAIN_*()
On Mon, Feb 17, 2025 at 05:34:28PM -0300, Gustavo Sousa wrote:
> We already have other functions to get power domain for other things
> (i.e. intel_display_power_*_domain()). Convert POWER_DOMAIN_*() macros
> to the same standard.
>
> Cc: Ville Syrjälä
> Signed-off-by: Gustavo Sousa
> ---
>
> N
== Series Details ==
Series: drm/{i915, xe}/display: Move dsm registration under intel_driver
URL : https://patchwork.freedesktop.org/series/144975/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16146 -> Patchwork_144975v1
In the hope of contributing to type safety in our code, let's ensure
that the type returned by the POWER_DOMAIN_*() macros is always of type
enum intel_display_power_domain.
v2:
- Remove accidental +1 in definition of POWER_DOMAIN_PIPE(). (Jani)
Cc: Jani Nikula
Signed-off-by: Gustavo Sousa
--
We already have other functions to get power domain for other things
(i.e. intel_display_power_*_domain()). Convert POWER_DOMAIN_*() macros
to the same standard.
Cc: Ville Syrjälä
Signed-off-by: Gustavo Sousa
---
Note: Maybe this patch could be squashed with the previous one.
drivers/gpu/drm/
Fix one issue[1] reported by the kernel test robot and also take this
opportunity to improve POWER_DOMAIN_*() macros by making them explicitly
return the expected enum type with patch #2 and then turning them into function
with #3.
Patch #3 could be squashed into #2, but I'll defer that to reviewe
Although we have comments in intel_display_limits.h saying that the
code expects PIPE_A and TRANSCODER_A to be zero, it doesn't hurt to add
them as explicit base values for calculating the power domain offset in
POWER_DOMAIN_*() macros.
On the plus side, we have that this:
* Fixes a warning repo
On Mon, Feb 17, 2025 at 09:00:45AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Introduce i915_error_regs as the EIR/EMR counterpart
> to the IIR/IMR/IER i915_irq_regs, and update the irq
> reset/postingstall to utilize them accordingly.
>
> v2: Include xe compat versions
>
> Reviewed-
Quoting Ville Syrjälä (2025-02-17 14:44:39-03:00)
>On Mon, Feb 17, 2025 at 12:35:23PM -0300, Gustavo Sousa wrote:
>> Update intel_bw.c to use a "display" variable to refer to members of the
>> display struct. While this change does not move that file to completely
>> use struct intel_display as par
Move dsm register/unregister calls from the drivers to under
intel_display_driver register/unregister.
v2: Rebase only
Reviewed-by: Jonathan Cavitt
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_display_driver.c | 4
drivers/gpu/drm/i915/i915_driver.c
== Series Details ==
Series: series starting with [1/3] drm/xe/display: Move display runtime suspend
to a later point (rev2)
URL : https://patchwork.freedesktop.org/series/144901/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16146 -> Patchwork_144901v2
==
== Series Details ==
Series: series starting with [1/3] drm/xe/display: Move display runtime suspend
to a later point (rev2)
URL : https://patchwork.freedesktop.org/series/144901/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't b
On Mon, Feb 17, 2025 at 12:35:24PM -0300, Gustavo Sousa wrote:
> Add one step further into making intel_bw.c xe/i915 agnostic by using
> display-specific platform checks.
>
> v2:
> - Fix typo that resulted in converting IS_DG1(display) to
> display->platform.dg2.
>
> Signed-off-by: Gustavo
On Mon, Feb 17, 2025 at 08:34:39PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 14, 2025 at 05:41:26PM +0530, Ankit Nautiyal wrote:
> > During modeset enable sequence, program the fixed timings,
> > and turn on the VRR Timing Generator (VRR TG) for platforms
> > that always use VRR TG.
> >
> > Later
On Fri, Feb 14, 2025 at 05:41:23PM +0530, Ankit Nautiyal wrote:
> Do not program transcoder registers for VRR for the secondary pipe of
> the joiner. Remove check to skip VRR for joiner case.
Premature. We need to figure out how to correctly sequence
transcoder level stuff vs. pipe level stuff in
On Mon, Feb 17, 2025 at 07:49:08PM +0200, Ville Syrjälä wrote:
> On Mon, Feb 17, 2025 at 12:35:24PM -0300, Gustavo Sousa wrote:
> > Add one step further into making intel_bw.c xe/i915 agnostic by using
> > display-specific platform checks.
> >
> > v2:
> > - Fix typo that resulted in converting I
On Fri, Feb 14, 2025 at 05:41:15PM +0530, Ankit Nautiyal wrote:
> Since CMRR is now disabled, use the flag vrr.enable to tracks if vrr timing
> generator is used with variable timings.
>
> Avoid setting vrr.enable for CMRR and adjust readout to not set vrr.enable
> when vmax == vmin == flipline (f
Bandwidth parameters for Xe3_LPD have been updated with respect to
previous display releases. Encode them into xe3lpd_sa_info and use that
new struct.
Bspec: 68859
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_bw.c | 11 ++-
1 file changed, 10 insertions(+), 1 delet
On Fri, Feb 14, 2025 at 05:41:28PM +0530, Ankit Nautiyal wrote:
> Currently VRR timing generator is used only when VRR is enabled by
> userspace for sinks that support VRR. From MTL+ gradually move away from
> the older timing generator and use VRR timing generator for both variable
> and fixed tim
On Fri, Feb 14, 2025 at 05:41:26PM +0530, Ankit Nautiyal wrote:
> During modeset enable sequence, program the fixed timings,
> and turn on the VRR Timing Generator (VRR TG) for platforms
> that always use VRR TG.
>
> Later if vrr timings are required, vrr_enable() will switch
> to the real VRR tim
== Series Details ==
Series: drm/i915: Provide more information on display faults (rev3)
URL : https://patchwork.freedesktop.org/series/143627/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16146 -> Patchwork_143627v3
Summa
== Series Details ==
Series: drm/i915: Provide more information on display faults (rev3)
URL : https://patchwork.freedesktop.org/series/143627/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Fri, Feb 14, 2025 at 05:41:18PM +0530, Ankit Nautiyal wrote:
> Currently we do not support VRR with HDMI so skip vrr compute
> config step for DP with HDMI sink.
>
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 8 +++-
> 1 file changed, 7 insertions(+),
On Fri, Feb 14, 2025 at 05:41:17PM +0530, Ankit Nautiyal wrote:
> Currently we always compute the timings as if vrr is enabled.
> With this approach the state checker becomes complicated when we
> introduce fixed refresh rate mode with vrr timing generator.
>
> To avoid the complications, instead
== Series Details ==
Series: drm/i915: Provide more information on display faults (rev3)
URL : https://patchwork.freedesktop.org/series/143627/
State : warning
== Summary ==
Error: dim checkpatch failed
58ff02cb79db drm/i915: Add missing else to the if ladder in missing else
fb1760bf1c2f drm/i
On Fri, Feb 14, 2025 at 05:41:16PM +0530, Ankit Nautiyal wrote:
> To have fixed refresh rate with VRR timing generator the
> guardband/pipeline full can't be programmed on the fly. So we need to
> ensure that the values satisfy both the fixed and variable refresh
> rates.
>
> Since we compute thes
On Mon, Feb 17, 2025 at 12:35:23PM -0300, Gustavo Sousa wrote:
> Update intel_bw.c to use a "display" variable to refer to members of the
> display struct. While this change does not move that file to completely
> use struct intel_display as part of it's internal and public interface,
> this should
== Series Details ==
Series: drm/i915/xe3lpd: Update bandwidth parameters (rev2)
URL : https://patchwork.freedesktop.org/series/11/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16146 -> Patchwork_11v2
Summary
-
On Mon, Feb 17, 2025 at 12:08:08PM +0200, Pekka Paalanen wrote:
> Hi Arun,
>
> this whole series seems to be missing all the UAPI docs for the DRM
> ReST files, e.g. drm-kms.rst. The UAPI header doc comments are not a
> replacement for them, I would assume both are a requirement.
>
> Without the
Update intel_bw.c to use a "display" variable to refer to members of the
display struct. While this change does not move that file to completely
use struct intel_display as part of it's internal and public interface,
this should help with a future transition.
Signed-off-by: Gustavo Sousa
---
dri
Bandwidth parameters for Xe3_LPD have been updated with respect to
previous display releases. Encode them into xe3lpd_sa_info and use that
new struct.
Since we are touching intel_bw.c, also take the opportunity to make it
use display-specific platform checkers, which is what patches #1 and #2
are
Add one step further into making intel_bw.c xe/i915 agnostic by using
display-specific platform checks.
v2:
- Fix typo that resulted in converting IS_DG1(display) to
display->platform.dg2.
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_bw.c | 77 ++
On Mon, 17 Feb 2025 12:08:08 +0200
Pekka Paalanen wrote:
> Hi Arun,
>
> this whole series seems to be missing all the UAPI docs for the DRM
> ReST files, e.g. drm-kms.rst. The UAPI header doc comments are not a
> replacement for them, I would assume both are a requirement.
>
> Without the ReST
== Series Details ==
Series: drm/i915/display: Allow display PHYs to reset power state (rev4)
URL : https://patchwork.freedesktop.org/series/144102/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16143 -> Patchwork_144102v4
== Series Details ==
Series: drm/i915/display: Allow display PHYs to reset power state (rev4)
URL : https://patchwork.freedesktop.org/series/144102/
State : warning
== Summary ==
Error: dim checkpatch failed
39d8ced99928 drm/i915/display: Drop crtc_state from C10/C20 pll programming
-:290: CHE
The dedicated display PHYs reset to a power state that blocks S0ix,
increasing idle system power. After a system reset (cold boot,
S3/4/5, warm reset) if a dedicated PHY is not being brought up
shortly, use these steps to move the PHY to the lowest power state
to save power.
1. Follow the PLL Enab
For PLL programming for C10 and C20 we don't need to
carry crtc_state but instead use only necessary parts
of the crtc_state i.e. pll_state.
This change is needed to PTL wa 14023648281 where we would
need to otherwise pass an artificial crtc_state with majority
of the struct members initialized as
The dedicated display PHYs reset to a power state that blocks S0ix,
increasing idle system power. After a system reset (cold boot,
S3/4/5, warm reset) if a dedicated PHY is not being brought up
shortly, use these steps to move the PHY to the lowest power state
to save power.
1. Follow the PLL Enab
Hi Arun,
this whole series seems to be missing all the UAPI docs for the DRM
ReST files, e.g. drm-kms.rst. The UAPI header doc comments are not a
replacement for them, I would assume both are a requirement.
Without the ReST docs it is really difficult to see how this new UAPI
should be used.
On
> -Original Message-
> From: andriy.shevche...@linux.intel.com
>
> Sent: Monday, February 17, 2025 1:43 AM
> To: Borah, Chaitanya Kumar
> Cc: linux-ser...@vger.kernel.org; intel-gfx@lists.freedesktop.org; intel-
> x...@lists.freedesktop.org; Kurmi, Suresh Kumar
> ; Saarinen, Jani
> Su
== Series Details ==
Series: drm/i915: Provide more information on display faults (rev2)
URL : https://patchwork.freedesktop.org/series/143627/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16142 -> Patchwork_143627v2
Summa
59 matches
Mail list logo
