On Mon, Feb 17, 2025 at 07:49:08PM +0200, Ville Syrjälä wrote:
> On Mon, Feb 17, 2025 at 12:35:24PM -0300, Gustavo Sousa wrote:
> > Add one step further into making intel_bw.c xe/i915 agnostic by using
> > display-specific platform checks.
> >
> > v2:
> > - Fix typo that resulted in converting IS_DG1(display) to
> > display->platform.dg2.
> >
> > Signed-off-by: Gustavo Sousa <gustavo.so...@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_bw.c | 77 ++++++++++++++-----------
> > 1 file changed, 43 insertions(+), 34 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 0fb41e6cd8ae..51b82979a8e4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -78,6 +78,7 @@ static int icl_pcode_read_qgv_point_info(struct
> > drm_i915_private *dev_priv,
> > struct intel_qgv_point *sp,
> > int point)
> > {
> > + struct intel_display *display = &dev_priv->display;
> > u32 val = 0, val2 = 0;
> > u16 dclk;
> > int ret;
> > @@ -89,7 +90,7 @@ static int icl_pcode_read_qgv_point_info(struct
> > drm_i915_private *dev_priv,
> > return ret;
> >
> > dclk = val & 0xffff;
> > - sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) >= 12 ?
> > 500 : 0),
> > + sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(display) >= 12 ?
> > 500 : 0),
>
> Side note: could you (or someone) fix up this botched rounding stuff?
Hmm. Could probably take the same approach that we use for
the PSF stuff and and just do something like:
int dclk_freq_mhz(int ratio)
{
/* multiples of 16.666 MHz (100/6) */
return DIV_ROUND_CLOSEST(ratio * 100, 6);
}
--
Ville Syrjälä
Intel
