> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Tuesday, 26 November 2024 12.12
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Vivi, Rodrigo
>
> Subject: [PATCH 2/2] drm/i915/dislay: convert i9xx_display_sr.[ch] to struct
> intel_display
>
> Going f
== Series Details ==
Series: Refactor VRR for different VRR timing generator
URL : https://patchwork.freedesktop.org/series/141820/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15750 -> Patchwork_141820v1
Summary
---
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Tuesday, 26 November 2024 12.12
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Vivi, Rodrigo
>
> Subject: [PATCH 1/2] drm/i915/display: prefer DISPLAY_VER over GRAPHICS_VER
> in display s/r
>
> Use dis
There is a HW issue that arises when there are race conditions
between TCSS entering/exiting TC7 or TC10 states while the
driver is asserting/deasserting TCSS power request. As a
workaround, Display driver will implement a mailbox sequence
to ensure that the TCSS is in TC0 when TCSS power request i
Let's start using struct intel_display instead of struct drm_i915_private
when introducing new code. No functional changes.
v2: Drop tc_to_intel_display() helper funtion (Jani)
Signed-off-by: Mika Kahola
Reviewed-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_tc.c | 9 ---
There is a HW issue that arises when there are race conditions
between TCSS entering/exiting TC7 or TC10 states while the
driver is asserting/deasserting TCSS power request. As a
workaround, Display driver will implement a mailbox sequence
to ensure that the TCSS is in TC0 when TCSS power request i
== Series Details ==
Series: Refactor VRR for different VRR timing generator
URL : https://patchwork.freedesktop.org/series/141820/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bit
Print Vrr mode along with other vrr members in crtc_state dump.
Signed-off-by: Ankit Nautiyal
---
.../drm/i915/display/intel_crtc_state_dump.c| 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
b/drivers/
The VRR timing generator can be used in multiple modes of operation:
dynamic refresh rate (VRR), content-matched refresh rate (CMRR), and
fixed refresh rate (Fixed_RR).
Currently, VRR and CMRR modes are supported, with Fixed_RR mode
forthcoming.
To track the different operational modes of the VRR
Fill vrr.mode during compute_config and update intel_vrr_get_config() to
read vrr.mode based on CMRR and VRR enable conditions.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 5 +
2 files changed, 6 inserti
Since cmrr is now one of the mode of operation of VRR timing generator,
move its elements in the vrr struct.
Replace cmrr.enable with vrr.mode INTEL_VRRTG_MODE_CMRR and move cmrr_m
and cmrr_n in vrr struct.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 19 +++
Since we now have vrr.mode to track the mode in which the VRR timing
generator is running, we no longer need member vrr.enable.
Replace the check for vrr.enable and use a helper to check
vrr.mode != NONE.
Signed-off-by: Ankit Nautiyal
---
.../drm/i915/display/intel_crtc_state_dump.c | 2 +-
d
Combine the CMRR capability and enable check into a single condition.
Set crtc_state->cmrr.enable directly within the combined condition.
This will make way to absorb cmrr members in vrr struct.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 5 ++---
1 file changed,
Introduce helper functions to compute timings for different mode of
operation of VRR timing generator.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 115 +++
1 file changed, 75 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/di
The VRR timing generator supports multiple modes:
dynamic refresh rate (VRR), content-matched refresh rate (CMRR), and
fixed refresh rate (Fixed_RR).
To better track the different operational modes of the VRR timing generator
refactor the existing vrr members and functions.
This will also help to
== Series Details ==
Series: drm/i915/dpt: Try to make DPT shrinkable again
URL : https://patchwork.freedesktop.org/series/141815/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15750 -> Patchwork_141815v1
Summary
---
== Series Details ==
Series: drm/i915/dpt: Try to make DPT shrinkable again
URL : https://patchwork.freedesktop.org/series/141815/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
From: Ville Syrjälä
Try to make DPT objects shrinakble once again. To overcome
the earlier suspend/resume issues we'll just make sure all
DPT VMAs are evicted during suspend, and thus resume won't
care whether the DPT objects got kicked out or not.
The proper solution would perhaps be to do the
From: Ville Syrjälä
This reverts commit 51064d471c53dcc8eddd2333c3f1c1d9131ba36c.
Now that we forcefully evict all DPT VMAs during suspend
there should be no problem allowing the shrinker to eat
the DPT objects.
Cc: Brian Geffon
Cc: Vidya Srinivas
Closes: https://gitlab.freedesktop.org/drm/i9
From: Ville Syrjälä
Currently intel_dpt_resume() tries to blindly rewrite all the
PTEs for currently bound DPT VMAs. That is problematic because
the CPU mapping for the DPT is only really guaranteed to exist
while the DPT object has been pinned. In the past we worked
around this issue by making D
From: Ville Syrjälä
Currently we reuse the commit_work for a later cleanup step.
Let's not do that so that atomic ioctl handler won't accidentally
wait for the cleanup work when it really wants to just wait on the
commit_tail() part. We'll just add another work struct for the
cleanup.
Cc: Brian
From: Ville Syrjälä
Introduce a dedicated workqueue for the commit cleanup work.
In the future we'll need this to guarantee all the cleanup
works have finished at a specific point during suspend.
Cc: Brian Geffon
Cc: Vidya Srinivas
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/displa
On Mon, Nov 25, 2024 at 02:55:34PM +0800, Xi Ruoyao wrote:
> On Tue, 2024-10-08 at 12:01 +0300, Juha-Pekka Heikkila wrote:
> > On 4.10.2024 21.03, Ville Syrjälä wrote:
> > > On Fri, Oct 04, 2024 at 04:35:17PM +0300, Juha-Pekka Heikkila wrote:
> > > > On 18.9.2024 17.44, Ville Syrjala wrote:
> > > >
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Wednesday, November 20, 2024 4:08 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org; Kandpal, Suraj ;
> jani.nik...@linux.intel.com; Deak, Imre
> Subject: [PATCH 11/12] drm/i915/dp: Make dsc helpers acce
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Wednesday, November 20, 2024 4:08 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org; Kandpal, Suraj ;
> jani.nik...@linux.intel.com; Deak, Imre
> Subject: [PATCH 09/12] drm/i915/dp_mst: Refactor pipe_bpp
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Wednesday, November 20, 2024 4:08 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org; Kandpal, Suraj ;
> jani.nik...@linux.intel.com; Deak, Imre
> Subject: [PATCH 04/12] drm/i915/dp: Remove HAS_DSC macro
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Wednesday, November 20, 2024 4:08 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org; Kandpal, Suraj ;
> jani.nik...@linux.intel.com; Deak, Imre
> Subject: [PATCH 02/12] drm/i915/dp: Return early if DSC n
== Series Details ==
Series: drm/dp: Expose only a properly inited connector
URL : https://patchwork.freedesktop.org/series/141797/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15749 -> Patchwork_141797v1
Summary
---
== Series Details ==
Series: drm/dp: Expose only a properly inited connector
URL : https://patchwork.freedesktop.org/series/141797/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
After a connector is added to the drm_mode_config::connector_list, it's
visible to any in-kernel users looking up connectors via the above list.
Make sure that the connector is properly initialized before such
look-ups.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915
After an error during adding an MST connector the MST port and the
intel_connector object could be leaked, fix this up.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
dif
Follow the canonical way in intel_dp_mst.c, referencing a connector only
via a struct intel_connector pointer and naming this pointer 'connector'
instead of 'intel_connector', the only exception being the casting of
a drm_connector function parameter pointer to intel_connector, calling
the drm_conn
Atm when the connector is added to the drm_mode_config::connector_list,
the connector may not be fully initialized yet. This is not a problem
for user space, which will see the connector only after it's registered
later, it could be a problem for in-kernel users looking up connectors
via the above
This patchset is v2 of [1], without the first patch which is already
merged, adding Rodrigo's R-bs and addressing Jani's review comments in
patch 1 of this patchset and the newly added patch 4.
Cc: Rodrigo Vivi
Cc: Jani Nikula
[1] https://lore.kernel.org/all/20241115164159.1081675-1-imre.d...@i
== Series Details ==
Series: Plane Color Pipeline support for Intel platforms (rev2)
URL : https://patchwork.freedesktop.org/series/129811/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15749 -> Patchwork_129811v2
Summary
-
== Series Details ==
Series: Plane Color Pipeline support for Intel platforms (rev2)
URL : https://patchwork.freedesktop.org/series/129811/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Plane Color Pipeline support for Intel platforms (rev2)
URL : https://patchwork.freedesktop.org/series/129811/
State : warning
== Summary ==
Error: dim checkpatch failed
0aab9cd08484 drm: color pipeline base work
-:46: WARNING:FILE_PATH_CHANGES: added, moved or del
From: Chaitanya Kumar Borah
Add helper to initialize 1D segmented LUT
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_colorop.c | 27 ++-
include/drm/drm_colorop.h | 4
2 files changed, 30 insertions(+), 1 deletion(-)
On Tue, 26 Nov 2024, "Kahola, Mika" wrote:
>> -Original Message-
>> From: Jani Nikula
>> Sent: Tuesday, 26 November 2024 11.30
>> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org
>> Cc: Sousa, Gustavo ; Jadav, Raag
>> ; Kahola, Mika
>> Subject: Re: [PATCH v5 1/2] drm/i915/xe3lpd: Power
Extract the LUT and program plane post csc registers.
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_color.c | 109 +
1 file changed, 109 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers
Add documentation to explain properties of the exposed hardware
1D LUT blocks, its identification and computation of the LUT samples
based on the number of samples, their distribution and precison.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
Documentation/gpu/rfc/color_p
From: Chaitanya Kumar Borah
Expose color pipeline and add ability to program it.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_uni
Add callback for programming Pre-CSC LUT for TGL and beyond
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 88 ++
1 file changed, 88 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/dr
Add macros to define Plane Post CSC registers
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
.../i915/display/skl_universal_plane_regs.h | 73 +++
1 file changed, 73 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
b/dri
From: Chaitanya Kumar Borah
Add framework that will help in loading LUT to Pre/Post CSC color
blocks.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 27 ++
drivers/gpu/drm/i915/display/intel_color.h | 2 ++
Add macros to define Plane Degamma registers
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
.../i915/display/skl_universal_plane_regs.h | 53 +++
1 file changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
b/driv
Add callback for setting CTM block in platforms D13 and beyond
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 79 ++
1 file changed, 79 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b
From: Chaitanya Kumar Borah
Since we intend to add plane color callbacks from Xelpd(D13 and beyond),
create a different structure for it.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 15 ++-
1 file changed, 14 ins
From: Chaitanya Kumar Borah
Add callback to intel color functions for setting plane CTM.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 23 ++
drivers/gpu/drm/i915/display/intel_color.h | 2 ++
2 files chan
From: Chaitanya Kumar Borah
Add infrastructure to set colorop. We iterate through all the color ops
in a selected COLOR PIPELINE and set them one by one.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 31 ++
From: Chaitanya Kumar Borah
Add supported color pipelines and attach it to plane.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 42 ++
drivers/gpu/drm/i915/display/intel_color.h | 3 ++
2 files changed, 45
From: Chaitanya Kumar Borah
Add a color pipeline with three colorops in the sequence
1D LUT MULTSEG - CTM - 1D LUT MULTSEG
This pipeline can be used to do any color space conversion or HDR
tone mapping
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/d
From: Chaitanya Kumar Borah
Add support for color ops that can be programmed
by 1 dimensional multi segmented Look Up Tables.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic.c | 4
drivers/gpu/drm/drm_atomic_uapi.c | 3 +++
include/uapi
From: Chaitanya Kumar Borah
Add intel colorop create helper
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 39 ++
drivers/gpu/drm/i915/display/intel_color.h | 3 ++
2 files changed, 42 insertions(+)
diff -
From: Chaitanya Kumar Borah
Add support for 3x3 Color Transformation Matrices in Color Pipeline.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic.c | 3 +++
drivers/gpu/drm/drm_atomic_uapi.c | 3 +++
drivers/gpu/drm/drm_colorop.c | 29 +
From: Chaitanya Kumar Borah
Add data structure to store intel specific details of colorop
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
.../drm/i915/display/intel_display_types.h| 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/
> -Original Message-
> From: Jani Nikula
> Sent: Tuesday, 26 November 2024 11.30
> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org
> Cc: Sousa, Gustavo ; Jadav, Raag
> ; Kahola, Mika
> Subject: Re: [PATCH v5 1/2] drm/i915/xe3lpd: Power request
> asserting/deasserting
>
> On Tue, 05 No
From: Chaitanya Kumar Borah
Add macros to identify intel color blocks. It will help
in mapping drm_color_ops to intel color HW blocks
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_display_limits.h | 13 +
1 file changed, 13
This adds helper functions to create 1D multi-segmented Lut color block
capabilities. It exposes the hardware block as segments
which are converted to blob and passed in the property.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_colorop.c | 24
Existing LUT precision structure is having only 16 bit
precision. This is not enough for upcoming enhanced hardwares
and advance usecases like HDR processing. Hence added a new
structure with 32 bit precision values.
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gp
Add capability property which a colorop can expose it's
hardware's abilities. It's a blob property that can be
filled with respective data structures depending on the
colorop. The user space is expected to read this property
and program the colorop accordingly.
Signed-off-by: Uma Shankar
Signed-o
Add a helper to create capability property for a colorop
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/drm_colorop.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/drm_colorop.c b/drivers/gpu/drm/drm_colorop.c
ind
This defines a new structure to define color lut ranges,
along with related macro definitions and enums. This will help
describe segmented lut ranges/PWL LUTs in the hardware.
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
include/uapi/drm/drm_mode.h | 64 ++
This series intends to add support for Plane Color Management for
Intel platforms. This is based on the design which has been agreed
upon by the community. Series implementing the design for generic
DRM core has been sent out by Harry Wentland and is under review
below:
https://patchwork.freedeskto
On Mon, Nov 25, 2024 at 10:04:46PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/dp_mst: Fix MST sideband message body length check
> URL : https://patchwork.freedesktop.org/series/141772/
> State : failure
Thanks for the review, patch is pushed to drm-misc-fixes.
The failure
== Series Details ==
Series: series starting with [1/2] drm/i915/display: prefer DISPLAY_VER over
GRAPHICS_VER in display s/r
URL : https://patchwork.freedesktop.org/series/141783/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15747 -> Patchwork_141783v1
=
== Series Details ==
Series: series starting with [1/2] drm/i915/display: prefer DISPLAY_VER over
GRAPHICS_VER in display s/r
URL : https://patchwork.freedesktop.org/series/141783/
State : warning
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/141783/revisions/1/
> -Original Message-
> From: Borah, Chaitanya Kumar
> Sent: Tuesday, 26 November 2024 11.04
> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org
> Cc: jani.nik...@linux.intel.com; Sousa, Gustavo ;
> Jadav, Raag ; Kahola, Mika
> Subject: RE: [PATCH v5 2/2] drm/i915/display: Use struct inte
> -Original Message-
> From: Srinivas, Vidya
> Sent: 25 November 2024 17:01
> To: Brian Geffon
> Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville ;
> ville.syrj...@linux.intel.com; Lee, Shawn C
> Subject: RE: [PATCH 2/2] [RFC] drm/i915: Unbind the vma in suspend if it was
> bound
>
Going forward, struct intel_display is the main device data structure
for display. Switch to it.
Cc: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/i9xx_display_sr.c| 76 +--
.../gpu/drm/i915/display/i9xx_display_sr.h| 6 +-
drivers/gpu/drm/i915/i9
Use display version checks for display scratch registers, not graphics
version. And for the older platforms it's the same thing anyway.
Cc: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_display_sr.c | 16
1 file changed, 8 insertions(+), 8 deleti
On Tue, 05 Nov 2024, Mika Kahola wrote:
> There is a HW issue that arises when there are race conditions
> between TCSS entering/exiting TC7 or TC10 states while the
> driver is asserting/deasserting TCSS power request. As a
> workaround, Display driver will implement a mailbox sequence
> to ensur
On Mon, 25 Nov 2024, Imre Deak wrote:
> On Mon, Nov 25, 2024 at 02:09:59PM +0200, Jani Nikula wrote:
>> encoder->get_hw_state() returns false for DP MST, and currently always
>> interprets 128b/132b as MST. Therefore the DDI MST mode checks in
>> intel_ddi_connector_get_hw_state() are redundant.
>
> -Original Message-
> From: Intel-gfx On Behalf Of Mika
> Kahola
> Sent: Tuesday, November 5, 2024 6:48 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: jani.nik...@linux.intel.com; Sousa, Gustavo ;
> Jadav, Raag ; Kahola, Mika
> Subject: [PATCH v5 2/2] drm/i915/display: Use struct inte
Am 26.11.24 um 07:38 schrieb Raag Jadav:
On Mon, Nov 25, 2024 at 10:32:42AM +0100, Christian König wrote:
Am 22.11.24 um 17:02 schrieb Raag Jadav:
On Fri, Nov 22, 2024 at 11:09:32AM +0100, Christian König wrote:
Am 22.11.24 um 08:07 schrieb Raag Jadav:
On Mon, Nov 18, 2024 at 08:26:37PM +0530
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