> Subject: [PATCH dii-client 2/2] drm/i915/gt: Apply workaround 22016122933
> correctly
Remove dii-client from the subject.
Otherwise LGTM.
Acked-by: Fei Yang
> WA_22016122933 was recently applied to all MeteorLake engines,
> which is simultaneously too broad (should only apply to Media
> engi
> Refactor i915_coherent_map_type to be GT-centric rather than
> device-centric. Each GT may require different coherency handling
> due to hardware workarounds.
>
> Since the function now takes a GT instead of the i915, the function
> is renamed and moved to the gt folder.
Remove dii-client in th
== Series Details ==
Series: MTL Degamma implementation (rev3)
URL : https://patchwork.freedesktop.org/series/119844/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13419_full -> Patchwork_119844v3_full
Summary
---
**
> -Original Message-
> From: Intel-gfx On Behalf Of
> Shankar,
> Uma
> Sent: Thursday, July 20, 2023 3:41 PM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/hotplug: Reduce SHPD_FILTER to 250us
>
>
>
> > -Original Message-
>
== Series Details ==
Series: MTL Degamma implementation (rev3)
URL : https://patchwork.freedesktop.org/series/119844/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13419_full -> Patchwork_119844v3_full
Summary
---
**
Any comments?
Thanks and Regards,
Arun R Murthy
> -Original Message-
> From: Murthy, Arun R
> Sent: Friday, July 14, 2023 11:08 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: [PATCH] drm/i915/dp: Fix LT debug print in SDP CRC enable
>
> Th
On Wed, Jul 26, 2023 at 09:21:50AM +0800, Su Hui wrote:
> On 2023/7/25 13:51, Dan Carpenter wrote:
> > The reason why the first five attempts had bugs is because we are
> > trying to write it in the most complicated way possible, shifting by
> > logical not what?
> Wonderful! Should I add your name
== Series Details ==
Series: Fix C10/C20 implementation w.r.t. owned PHY lanes
URL : https://patchwork.freedesktop.org/series/121334/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13422_full -> Patchwork_121334v1_full
Summa
Hello Tvrtko,
Your analysis is correct. Alistair has sent a new patch set with a fix.
Thank you.
Regards
Chaitanya
> -Original Message-
> From: Tvrtko Ursulin
> Sent: Tuesday, July 25, 2023 4:24 PM
> To: Borah, Chaitanya Kumar ;
> apop...@nvidia.com
> Cc: Nikula, Jani ; intel-gfx@list
Hello Alistair,
Thank you for the quick fix.
Regards
Chaitanya
> -Original Message-
> From: Alistair Popple
> Sent: Tuesday, July 25, 2023 6:45 PM
> To: Borah, Chaitanya Kumar
> Cc: Yedireswarapu, SaiX Nandan ;
> Saarinen, Jani ; Kurmi, Suresh Kumar
> ; Nikula, Jani ; intel-
> g...@li
== Series Details ==
Series: drm/i915/guc/slpc: Restore efficient freq earlier (rev2)
URL : https://patchwork.freedesktop.org/series/121150/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13422 -> Patchwork_121150v2
Summary
This should be done before the soft min/max frequencies are restored.
When we disable the "Ignore efficient frequency" flag, GuC does not
actually bring the requested freq down to RPn.
Specifically, this scenario-
- ignore efficient freq set to true
- reduce min to RPn (from efficient)
- suspend
== Series Details ==
Series: Update AUX invalidation sequence (rev12)
URL : https://patchwork.freedesktop.org/series/119798/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13422 -> Patchwork_119798v12
Summary
---
**FA
== Series Details ==
Series: Update AUX invalidation sequence (rev12)
URL : https://patchwork.freedesktop.org/series/119798/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:1
== Series Details ==
Series: Update AUX invalidation sequence (rev12)
URL : https://patchwork.freedesktop.org/series/119798/
State : warning
== Summary ==
Error: dim checkpatch failed
94aa9fabe7a4 drm/i915/gt: Cleanup aux invalidation registers
ff01e99c38e6 drm/i915: Add the gen12_needs_ccs_au
== Series Details ==
Series: Fix C10/C20 implementation w.r.t. owned PHY lanes
URL : https://patchwork.freedesktop.org/series/121334/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13422 -> Patchwork_121334v1
Summary
---
== Series Details ==
Series: drm/i915: Avoid GGTT flushing on non-GGTT paths of i915_vma_pin_iomap
(rev3)
URL : https://patchwork.freedesktop.org/series/121236/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13420_full -> Patchwork_121236v3_full
===
Hello,
On Tue, Jul 25, 2023 at 03:08:40PM +0100, Tvrtko Ursulin wrote:
> > Also, shouldn't this be keyed by the drm device?
>
> It could have that too, or it could come later. Fun with GPUs that it not
> only could be keyed by the device, but also by the type of the GPU engine.
> (Which are a) ven
On Mon, Jul 24, 2023 at 08:47:48PM +0800, suijingfeng wrote:
> On 2023/7/20 03:32, Bjorn Helgaas wrote:
> > "drm/loongson: Add an implement for ..." also solves a problem, but it
> > lacks a commit log, so I don't know what the problem is.
>
> I have already telling you one yeas ago.
The patch it
On Mon, Jul 24, 2023 at 08:16:18PM +0800, suijingfeng wrote:
> On 2023/7/20 03:32, Bjorn Helgaas wrote:
> > > 2) It does not take the PCI Bar may get relocated into consideration.
> > > 3) It is not effective for the PCI device without a dedicated VRAM Bar.
> > > 4) It is device-agnostic, thus it h
It is possible to generalize the "disable" value for the transmitters to
be a bit mask based on the port width and the port reversal boolean,
with a small exception for DP-alt mode with "x1" port width.
Simplify the code by using such a mask and a for-loop instead of using
switch-case statements.
According to the BSpec, voltage swing programming should be done for
owned PHY lanes. Do not program a not-owned PHY lane.
BSpec: 74103, 74104
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 25 +++-
1 file changed, 14 insertions(+), 11 deletions(-
There are more parts of C10/C20 programming that need to take owned
lanes into account. Define the function intel_cx0_get_owned_lane_mask()
and use it. There will be new users of that function in upcoming
changes.
BSpec: 64539
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_c
Display must not enable or disable transmitters for not-owned PHY lanes.
BSpec: 64539
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers
While 619a06dba6fa ("drm/i915/mtl: Reset only one lane in case of MFD")
fixes the problem for lane reset logic, there are also more parts of the
implementation that need to take owned PHY lanes into consideration.
This series provides fixes for such places. The changes to the logic
have been teste
On Tue, Jul 25, 2023 at 01:08:11AM -0400, Gupta, Anshuman wrote:
>
>
> > -Original Message-
> > From: Vivi, Rodrigo
> > Sent: Saturday, July 22, 2023 12:30 AM
> > To: Gupta, Anshuman
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [PATCH 1/4] drm/xe: Only set PCI d3cold_allowed
== Series Details ==
Series: Update AUX invalidation sequence (rev11)
URL : https://patchwork.freedesktop.org/series/119798/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13420_full -> Patchwork_119798v11_full
Summary
-
> -Original Message-
> From: Intel-gfx On Behalf Of Maarten
> Lankhorst
> Sent: Thursday, June 29, 2023 9:05 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Swap ggtt_vma during legacy cursor
> update
>
> Xe is lacking the ability to re-use the ggt
== Series Details ==
Series: series starting with [dii-client,1/2] drm/i915: Make
i915_coherent_map_type GT-centric
URL : https://patchwork.freedesktop.org/series/121324/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13421 -> Patchwork_121324v1
===
== Series Details ==
Series: series starting with [dii-client,1/2] drm/i915: Make
i915_coherent_map_type GT-centric
URL : https://patchwork.freedesktop.org/series/121324/
State : warning
== Summary ==
Error: dim checkpatch failed
04b9b8deb0b7 drm/i915: Make i915_coherent_map_type GT-centric
-
== Series Details ==
Series: series starting with [dii-client,1/2] drm/i915: Make
i915_coherent_map_type GT-centric
URL : https://patchwork.freedesktop.org/series/121324/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
On Mon, 24 Jul 2023 13:09:22 -0600
Alex Williamson wrote:
> On Tue, 18 Jul 2023 13:57:46 -0300
> Jason Gunthorpe wrote:
>
> > On Tue, Jul 18, 2023 at 06:55:25AM -0700, Yi Liu wrote:
> > > Existing VFIO provides group-centric user APIs for userspace. Userspace
> > > opens the /dev/vfio/$group_
== Series Details ==
Series: drm/i915: Use the i915_vma_flush_writes helper (rev3)
URL : https://patchwork.freedesktop.org/series/121122/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13419_full -> Patchwork_121122v3_full
S
-Original Message-
From: Tvrtko Ursulin
Sent: Tuesday, July 25, 2023 9:23 AM
To: Cavitt, Jonathan ;
intel-gfx@lists.freedesktop.org
Cc: Shyti, Andi ; Roper, Matthew D
; chris.p.wil...@linux.intel.com; Das, Nirmoy
Subject: Re: [Intel-gfx] [PATCH dii-client 1/2] drm/i915: Make
i915_coh
On Mon, Jul 24, 2023 at 11:25:11AM +0300, Andy Shevchenko wrote:
> abs_diff() belongs to math.h. Move it there.
> This will allow others to use it.
>
> Signed-off-by: Andy Shevchenko
> Reviewed-by: Jiri Slaby # tty/serial
Acked-by: Greg Kroah-Hartman
Hi,
On Tue, Jul 25, 2023 at 03:41:31PM +0200, Andrzej Hajda wrote:
> On 25.07.2023 12:33, Andi Shyti wrote:
> > Quite surprised to see that around i915 there are still i915->gt0
> > references. Replace them with the to_gt() helper.
> >
> > Signed-off-by: Andi Shyti
> > ---
> > drivers/gpu/drm/
On 25/07/2023 17:01, Jonathan Cavitt wrote:
Refactor i915_coherent_map_type to be GT-centric rather than
device-centric. Each GT may require different coherency
handling due to hardware workarounds.
Since the function now takes a GT instead of the i915, the function is
renamed and moved to th
On Tue, Jul 25, 2023 at 12:10:18PM +0200, Andi Shyti wrote:
> Hi Matt,
>
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> > @@ -470,9 +470,13 @@ enum i915_map_type i915_coherent_map_type(struct
> > drm_i915_private *i915,
> >
== Series Details ==
Series: drm/i915: Avoid GGTT flushing on non-GGTT paths of i915_vma_pin_iomap
(rev3)
URL : https://patchwork.freedesktop.org/series/121236/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13420 -> Patchwork_121236v3
=
Refactor i915_coherent_map_type to be GT-centric rather than
device-centric. Each GT may require different coherency
handling due to hardware workarounds.
Since the function now takes a GT instead of the i915, the function is
renamed and moved to the gt folder.
Suggested-by: Matt Roper
Signed-o
WA_22016122933 was recently applied to all MeteorLake engines, which is
simultaneously too broad (should only apply to Media engines) and too
specific (should apply to all platforms that use the same media engine
as MeteorLake). Correct this in cases where coherency settings are
modified.
There w
== Series Details ==
Series: drm/i915: Replace i915->gt0 with to_gt(i915)
URL : https://patchwork.freedesktop.org/series/121302/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13419_full -> Patchwork_121302v1_full
Summary
--
On Tue, Jul 25, 2023 at 04:52:07PM +0100, Tvrtko Ursulin wrote:
>
> On 25/07/2023 16:35, Matt Roper wrote:
> > On Tue, Jul 25, 2023 at 01:02:54PM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 25/07/2023 01:13, Matt Roper wrote:
> > > > Although some of our Xe_LPG workarounds were already being appl
== Series Details ==
Series: drm/i915: Avoid GGTT flushing on non-GGTT paths of i915_vma_pin_iomap
(rev3)
URL : https://patchwork.freedesktop.org/series/121236/
State : warning
== Summary ==
Error: dim checkpatch failed
aaa6028351e5 drm/i915: Avoid GGTT flushing on non-GGTT paths of
i915_vma
On Tue, Jul 25, 2023 at 01:10:24PM +0100, Tvrtko Ursulin wrote:
>
> On 25/07/2023 01:13, Matt Roper wrote:
> > Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
> > of these workarounds are actually tied to MTL as a platform; they only
> > relate to the Xe_LPG graphics IP, reg
On 25/07/2023 16:35, Matt Roper wrote:
On Tue, Jul 25, 2023 at 01:02:54PM +0100, Tvrtko Ursulin wrote:
On 25/07/2023 01:13, Matt Roper wrote:
Although some of our Xe_LPG workarounds were already being applied based
on IP version correctly, others were matching on MTL as a base platform,
whic
On Tue, Jul 25, 2023 at 12:04:43PM +0200, Andi Shyti wrote:
> Hi Matt,
>
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -436,6 +436,9 @@ static inline struct intel_gt *to_gt(struct
> > drm_i915_private *i915)
> > #define __GT_VER_FULL(gt) (__IS_MEDIA_G
== Series Details ==
Series: Update AUX invalidation sequence (rev11)
URL : https://patchwork.freedesktop.org/series/119798/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13420 -> Patchwork_119798v11
Summary
---
**SU
On Tue, Jul 25, 2023 at 01:02:54PM +0100, Tvrtko Ursulin wrote:
>
> On 25/07/2023 01:13, Matt Roper wrote:
> > Although some of our Xe_LPG workarounds were already being applied based
> > on IP version correctly, others were matching on MTL as a base platform,
> > which is incorrect. Although MTL
== Series Details ==
Series: Update AUX invalidation sequence (rev11)
URL : https://patchwork.freedesktop.org/series/119798/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:1
== Series Details ==
Series: Update AUX invalidation sequence (rev11)
URL : https://patchwork.freedesktop.org/series/119798/
State : warning
== Summary ==
Error: dim checkpatch failed
ffd7dd1ce4c9 drm/i915/gt: Cleanup aux invalidation registers
bc25ba7824ec drm/i915: Add the gen12_needs_ccs_au
On Tue, Jul 25, 2023 at 11:21:34AM +0200, Andi Shyti wrote:
> Hi Matt,
>
> > +/*
> > + * Wa_22011802037 requires that we (or the GuC) ensure that no command
> > + * streamers are executing MI_FORCE_WAKE while an engine reset is
> > initiated.
> > + */
> > +bool intel_engine_reset_needs_wa_2201180
== Series Details ==
Series: MTL Degamma implementation (rev3)
URL : https://patchwork.freedesktop.org/series/119844/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13419_full -> Patchwork_119844v3_full
Summary
---
**
On 21/07/2023 23:20, Tejun Heo wrote:
On Fri, Jul 21, 2023 at 12:19:32PM -1000, Tejun Heo wrote:
On Wed, Jul 12, 2023 at 12:46:03PM +0100, Tvrtko Ursulin wrote:
+ drm.active_us
+ GPU time used by the group recursively including all child groups.
Maybe instead add drm.stat and have "u
== Series Details ==
Series: drm/i915: Avoid GGTT flushing on non-GGTT paths of i915_vma_pin_iomap
(rev2)
URL : https://patchwork.freedesktop.org/series/121236/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13419 -> Patchwork_121236v2
=
Hi Daniele,
On Thu, Jul 20, 2023 at 04:05:05PM -0700, Daniele Ceraolo Spurio wrote:
> If we can't load the HuC due to an injected failure, we don't want
> to throw and error and trip CI. Using the gt_probe_error macro for
> logging ensure that the error is only printed if it wasn't explicitly
> in
Hi Uwe,
On Fri, Jul 21, 2023 at 11:21:33PM +0200, Uwe Kleine-König wrote:
> to_i915 is defined as
>
> container_of(dev, struct drm_i915_private, drm);
>
> So for a struct drm_device *dev, to_i915(dev)->drm is just dev. Simplify
> accordingly.
>
> Signed-off-by: Uwe Kleine-König
pushed t
== Series Details ==
Series: drm/i915: Avoid GGTT flushing on non-GGTT paths of i915_vma_pin_iomap
(rev2)
URL : https://patchwork.freedesktop.org/series/121236/
State : warning
== Summary ==
Error: dim checkpatch failed
7f0658687535 drm/i915: Avoid GGTT flushing on non-GGTT paths of
i915_vma
On 21/07/2023 23:17, Tejun Heo wrote:
On Wed, Jul 12, 2023 at 12:46:00PM +0100, Tvrtko Ursulin wrote:
+DRM scheduling soft limits
+~~
Please don't say soft limits for this. It means something different for
memcg, so it gets really confusing. Call it "weight based CPU
On 25.07.2023 12:33, Andi Shyti wrote:
Quite surprised to see that around i915 there are still i915->gt0
references. Replace them with the to_gt() helper.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c |
From: Tvrtko Ursulin
Commit 4bc91dbde0da ("drm/i915/lmem: Bypass aperture when lmem is available")
added a code path which does not map via GGTT, but was still setting the
ggtt write bit, and so triggering the GGTT flushing.
Fix it by not setting that bit unless the GGTT mapping path was used, a
Hi Tvrtko,
> --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> @@ -68,10 +68,8 @@ flush_write_domain(struct drm_i915_gem_object *obj,
> unsigned int flush_domains)
> switch (obj->write_domain) {
> case I915_GEM_DOMAIN_GTT:
>
Hi Jonathan,
On Fri, Jul 21, 2023 at 07:05:58AM -0700, Jonathan Cavitt wrote:
> Refactor i915_coherent_map_type to be GT-centric rather than
> device-centric. Each GT may require different coherency
> handling due to hardware workarounds.
[...]
> -enum i915_map_type i915_coherent_map_type(struc
Hi Uwe,
On Fri, Jul 21, 2023 at 11:21:33PM +0200, Uwe Kleine-König wrote:
> to_i915 is defined as
>
> container_of(dev, struct drm_i915_private, drm);
>
> So for a struct drm_device *dev, to_i915(dev)->drm is just dev. Simplify
> accordingly.
>
> Signed-off-by: Uwe Kleine-König
that's c
Hi Uwe,
> > If you think the reported changes have nothing to do with the changes
> > introduced in Patchwork_121164v1_full, please notify your bug team to
> > allow them
> > to document this new failure mode, which will reduce false positives in
> > CI.
>
> I don't think my patch results
Hi Andy,
On Mon, Jul 24, 2023 at 11:25:11AM +0300, Andy Shevchenko wrote:
> abs_diff() belongs to math.h. Move it there.
> This will allow others to use it.
>
> Signed-off-by: Andy Shevchenko
> Reviewed-by: Jiri Slaby # tty/serial
Reviewed-by: Andi Shyti
Thanks,
Andi
== Series Details ==
Series: drm/i915: Use the i915_vma_flush_writes helper (rev3)
URL : https://patchwork.freedesktop.org/series/121122/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13419 -> Patchwork_121122v3
Summary
---
Hi Tvrtko,
> > > Commit 4bc91dbde0da ("drm/i915/lmem: Bypass aperture when lmem is
> > > available")
> > > added a code path which does not map via GGTT, but was still setting the
> > > ggtt write bit, and so triggering the GGTT flushing.
> > >
> > > Fix it by not setting that bit unless the GGT
== Series Details ==
Series: drm/i915/tv: avoid possible division by zero (rev3)
URL : https://patchwork.freedesktop.org/series/120851/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13418_full -> Patchwork_120851v3_full
Sum
On 25/07/2023 01:13, Matt Roper wrote:
Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
of these workarounds are actually tied to MTL as a platform; they only
relate to the Xe_LPG graphics IP, regardless of what platform it appears
in. At the moment MTL is the only platfo
On 25/07/2023 01:13, Matt Roper wrote:
Although some of our Xe_LPG workarounds were already being applied based
on IP version correctly, others were matching on MTL as a base platform,
which is incorrect. Although MTL is the only platform right now that
uses Xe_LPG IP, this may not always be t
On 24/07/2023 21:16, Andi Shyti wrote:
Hi Tvrtko,
On Mon, Jul 24, 2023 at 01:56:33PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Commit 4bc91dbde0da ("drm/i915/lmem: Bypass aperture when lmem is available")
added a code path which does not map via GGTT, but was still setting the
ggtt
== Series Details ==
Series: drm/i915: Replace i915->gt0 with to_gt(i915)
URL : https://patchwork.freedesktop.org/series/121302/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13419 -> Patchwork_121302v1
Summary
---
*
On 7/25/2023 3:40 PM, Lisovskiy, Stanislav wrote:
On Tue, Jul 25, 2023 at 11:22:52AM +0530, Nautiyal, Ankit K wrote:
On 7/20/2023 2:46 PM, Lisovskiy, Stanislav wrote:
On Thu, Jul 13, 2023 at 04:03:33PM +0530, Ankit Nautiyal wrote:
Currently we assume 2 Pixels Per Clock (PPC) while computing
On 7/25/2023 3:43 PM, Lisovskiy, Stanislav wrote:
On Mon, Jul 24, 2023 at 05:49:11PM +0530, Nautiyal, Ankit K wrote:
Hi Stan,
Thanks for the reviews ans suggestions. Please my response inline:
On 7/20/2023 2:59 PM, Lisovskiy, Stanislav wrote:
On Thu, Jul 13, 2023 at 04:03:32PM +0530, Ankit
On 25/07/2023 00:38, Sripada, Radhakrishna wrote:
Hi Tvrtko,
The changes makes sense and based on the description looks good.
I am bit skeptical about the exec buffer failure reported by ci hence,
withholding the r-b for now. If you believe the CI failure is unrelated
please feel free to add m
On 25/07/2023 07:42, Borah, Chaitanya Kumar wrote:
Hello Alistair,
Hope you are doing well. I am Chaitanya from the linux graphics team in Intel.
This mail is regarding a regression we are seeing in our CI runs[1] on linux-next
repository.
On next-20230720 [2], we are seeing the followi
== Series Details ==
Series: Update AUX invalidation sequence (rev10)
URL : https://patchwork.freedesktop.org/series/119798/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13418_full -> Patchwork_119798v10_full
Summary
-
Quite surprised to see that around i915 there are still i915->gt0
references. Replace them with the to_gt() helper.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_region
On Mon, Jul 24, 2023 at 05:49:11PM +0530, Nautiyal, Ankit K wrote:
> Hi Stan,
>
> Thanks for the reviews ans suggestions. Please my response inline:
>
>
> On 7/20/2023 2:59 PM, Lisovskiy, Stanislav wrote:
> > On Thu, Jul 13, 2023 at 04:03:32PM +0530, Ankit Nautiyal wrote:
> > > In Bigjoiner chec
On Tue, Jul 25, 2023 at 11:22:52AM +0530, Nautiyal, Ankit K wrote:
>
> On 7/20/2023 2:46 PM, Lisovskiy, Stanislav wrote:
> > On Thu, Jul 13, 2023 at 04:03:33PM +0530, Ankit Nautiyal wrote:
> > > Currently we assume 2 Pixels Per Clock (PPC) while computing
> > > plane cdclk and min_cdlck. In cases
Hi Matt,
> --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> @@ -470,9 +470,13 @@ enum i915_map_type i915_coherent_map_type(struct
> drm_i915_private *i915,
> bool always_coherent)
> {
> /*
> - *
Hi Matt,
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -436,6 +436,9 @@ static inline struct intel_gt *to_gt(struct
> drm_i915_private *i915)
> #define __GT_VER_FULL(gt) (__IS_MEDIA_GT(gt) ? \
> MEDIA_VER_FULL((gt)->i915) : \
>
== Series Details ==
Series: MTL Degamma implementation (rev3)
URL : https://patchwork.freedesktop.org/series/119844/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13419 -> Patchwork_119844v3
Summary
---
**WARNING**
Hi Matt,
[...]
all good
[...]
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
Is this the right place to define this? Maybe in
i915/gt/intel_gt.h?
> @@ -431,6 +431,29 @@ static inline struct intel_gt *to_gt(struct
> drm_i915_private *i915)
> #define IS_GRAPHI
== Series Details ==
Series: Reduce MTL-specific platform checks (rev2)
URL : https://patchwork.freedesktop.org/series/120943/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13418_full -> Patchwork_120943v2_full
Summary
Hi Matt,
On Mon, Jul 24, 2023 at 05:13:15PM -0700, Matt Roper wrote:
> The currently implemented Xe_LPM+ workarounds are specific to media
> version 13.00. When new IP versions show up in the future, they'll need
> their own workaround lists.
Makes sense...
Reviewed-by: Andi Shyti
Andi
> Si
Hi Matt,
> +/*
> + * Wa_22011802037 requires that we (or the GuC) ensure that no command
> + * streamers are executing MI_FORCE_WAKE while an engine reset is initiated.
> + */
> +bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
I've seen this format in a recent Jonathan's patch a
For MTL and beyond, convert back the 24 bit lut values
read from HW to 16 bit values to maintain parity with
userspace values. This way we avoid pipe config mismatch
for pre-csc lut values.
v2: Add helper function to downscale values (Jani)
Signed-off-by: Chaitanya Kumar Borah
Reviewed-by: Uma S
MTL onwards Degamma LUT/PRE-CSC LUT precision has been increased from
16 bits to 24 bits. Currently, drm framework only supports LUTs up to 16
bit precision. Until a new uapi comes along to support higher bitdepth,
upscale the values sent from userland to 24 bit before writing into the
HW to contin
MTL onwards Degamma LUT/PRE-CSC LUT precision has been increased from
16 bits to 24 bits. Currently, drm framework only supports LUTs up to 16
bit precision. Until a new uapi comes along to support higher bitdepth,
upscale the values sent from userland to 24 bit before writing into the
HW to contin
== Series Details ==
Series: drm/i915/tv: avoid possible division by zero (rev3)
URL : https://patchwork.freedesktop.org/series/120851/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13418 -> Patchwork_120851v3
Summary
-
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