== Series Details ==
Series: Fix Guc-Err-Capture sizing warning
URL : https://patchwork.freedesktop.org/series/109439/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12221 -> Patchwork_109439v1
Summary
---
**SUCCESS**
From: Matthew Brost
Add a delay, configurable via debugfs (default 34ms), to disable
scheduling of a context after the pin count goes to zero. Disable
scheduling is a costly operation as it requires synchronizing with
the GuC. So the idea is that a delay allows the user to resubmit
something befo
This series adds a delay before disabling scheduling of the guc-context
when a context has become idle to avoid costly re-registration that may
occur immediately after. The 2nd patch should explain it quite well.
The origin of this series was posted by Matthew Brost back in Oct 2021
(https://patch
On Wed, 2022-10-05 at 17:25 -0700, Harrison, John C wrote:
> On 9/21/2022 10:32, Alan Previn wrote:
> > @@ -208,6 +210,11 @@ struct intel_context {
> > * each priority bucket
> > */
> > u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
> > + /**
> > +
== Series Details ==
Series: drm/i915/pxp: Prepare intel_pxp entry points for MTL (rev2)
URL : https://patchwork.freedesktop.org/series/109429/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12221 -> Patchwork_109429v2
Summa
GuC Error capture initialization calculates an estimation
buffer size for worst case scenario of all engines getting
reset. Fix the calculation change from drm_warn to drm_dbg
since its a corner case
Changes from prior revs:
v2: - Reduce the guc-log-buffer error-capture-region allocation
During GuC error capture initialization, we estimate the amount of size
we need for the error-capture-region of the shared GuC-log-buffer.
This calculation was incorrect so fix that. With the fixed calculation
we can reduce the allocation of error-capture region from 4MB to 1MB
(see note2 below for
== Series Details ==
Series: drm/i915/pxp: Prepare intel_pxp entry points for MTL (rev2)
URL : https://patchwork.freedesktop.org/series/109429/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/pxp: Prepare intel_pxp entry points for MTL (rev2)
URL : https://patchwork.freedesktop.org/series/109429/
State : warning
== Summary ==
Error: dim checkpatch failed
e2bceb18904d drm/i915/pxp: Make gt and pxp init/fini aware of PXP-owning-GT
-:79: CHECK:MAC
In preparation for future MTL-PXP feature support, PXP control
context should only valid on the correct gt tile. Depending on the
device-info this mat not necessarily be the root GT tile and
depends on which tile owns the VEBOX and KCR.
PXP is still a global feature (despite the control-context be
Make intel_pxp_key_check implicitly find the PXP-owning-GT.
Callers of this function shall now pass in i915 since PXP
is a global GPU feature. Make intel_pxp_key_check implicitly
find the right gt to verify pxp session key establishment count
so it's transparent to the callers.
Signed-off-by: Alan
MTL has two tiles that is represented by the intel_gt structure in the i915
code. The PXP feature has a control-structure that contains the PXP context
and this hangs of the intel_gt structure. In MTL, the standalone media tile
(i.e. not the root tile) contains the VDBOX and KCR engine which is wha
Ensure i915_pxp_tee_component_bind / unbind implicitly sorts out
getting the correct PXP control-context from the PXP-owning-GT
when establishing or ending connection.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 17 +++--
1 file changed, 15 insertions(+)
Make PXP suspend/ resume functions implicitly verify if the caller
is the PXP-owning-GT. PXP control structure still hangs off the intel_gt
structure that manages has gt-level power management events. Thus change
the input param to intel_gt structure and let PXP implicitly take the
expected action
Make intel_pxp_is_start implicitly find the PXP-owning-GT.
Callers of this function shall now pass in i915 since PXP
is a global GPU feature. Make intel_pxp_start implicitly
find the right gt to start PXP arb session so
it's transparent to the callers.
Signed-off-by: Alan Previn
---
drivers/gpu/
Make intel_pxp_is_active implicitly find the PXP-owning-GT.
As per prior two patches, callers of this function shall now
pass in i915 since PXP is a global GPU feature. Make
intel_pxp_is_active implicitly find the right gt to check if
PXP is active so it's transparent to the callers.
Signed-off-by
Make intel_pxp_is_enabled implicitly find the PXP-owning-GT.
PXP feature support is a device-config flag. In preparation for MTL
PXP control-context shall reside on of the two GT's.
That said, update intel_pxp_is_enabled to take in i915 as its input
and internally find the right gt to check if PXP
== Series Details ==
Series: drm/i915: Fix display problems after resume (rev2)
URL : https://patchwork.freedesktop.org/series/108432/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12217_full -> Patchwork_108432v2_full
Summ
On 9/21/2022 10:32, Alan Previn wrote:
From: Matthew Brost
Add a delay, configurable via debugfs (default 34ms), to disable
scheduling of a context after the pin count goes to zero. Disable
scheduling is a costly operation as it requires synchronizing with
the GuC. So the idea is that a delay a
== Series Details ==
Series: drm/i915: Ensure dbuf state is defined
URL : https://patchwork.freedesktop.org/series/109414/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12217_full -> Patchwork_109414v1_full
Summary
---
Hi John, tested on real PVC and the estimated min size needed was ~115K. Even
without modelling, we can safely say that
an imaginary device with a tile that is 4x bigger would still be half than 1
MB. That said I shall proceed with a re-rev
that shall include dropping the size of guc-log-error-ca
On Wed, 5 Oct 2022 14:17:17 -0600
Alex Williamson wrote:
> On Thu, 29 Sep 2022 14:48:35 -0300
> Jason Gunthorpe wrote:
>
> > When converting to directly create the vfio_device the mdev driver has to
> > put a vfio_register_emulated_iommu_dev() in the probe() and a pairing
> > vfio_unregister_gr
== Series Details ==
Series: drm/connector: connector iterator with filtering
URL : https://patchwork.freedesktop.org/series/109411/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12217_full -> Patchwork_109411v1_full
Summar
I just realize i missed a patch (similar refactoring for pxp-suspend/resume
when caller is external).
Will post a rev2 with that missing bit. Review can continue on rev1 though
(rev2 will be an additional
patch following the same design proposal).
...alan
On Wed, 2022-10-05 at 12:18 -0700, Alan
== Series Details ==
Series: drm/i915/gvt: Add missing vfio_unregister_group_dev() call (rev2)
URL : https://patchwork.freedesktop.org/series/109264/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12219 -> Patchwork_109264v2
== Series Details ==
Series: drm/i915/gvt: Add missing vfio_unregister_group_dev() call (rev2)
URL : https://patchwork.freedesktop.org/series/109264/
State : warning
== Summary ==
Error: dim checkpatch failed
d1cb20a63051 drm/i915/gvt: Add missing vfio_unregister_group_dev() call
-:16: WARNING
On Wed, Oct 05, 2022 at 10:14:43PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 05, 2022 at 08:52:51PM +0300, Imre Deak wrote:
> > The GPU reset involves a display suspend/resume sequence, but this is
> > done without suspending/resuming the encoders.
>
> The display reset path is there for the old p
== Series Details ==
Series: series starting with [1/3] drm/i915: Extract intel_mmio_bar() (rev2)
URL : https://patchwork.freedesktop.org/series/109421/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12219 -> Patchwork_109421v2
==
On Thu, 29 Sep 2022 14:48:35 -0300
Jason Gunthorpe wrote:
> When converting to directly create the vfio_device the mdev driver has to
> put a vfio_register_emulated_iommu_dev() in the probe() and a pairing
> vfio_unregister_group_dev() in the remove.
>
> This was missed for gvt, add it.
>
> Cc:
== Series Details ==
Series: series starting with [1/3] drm/i915: Extract intel_mmio_bar() (rev2)
URL : https://patchwork.freedesktop.org/series/109421/
State : warning
== Summary ==
Error: dim checkpatch failed
bc524155b7f3 drm/i915: Extract intel_mmio_bar()
7d5f2af2878a drm/i915: Name our BA
== Series Details ==
Series: drm/i915/pxp: Prepare intel_pxp entry points for MTL
URL : https://patchwork.freedesktop.org/series/109429/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12219 -> Patchwork_109429v1
Summary
From: Ville Syrjälä
We use all kinds of weird names for our base address registers.
Take the names from the spec and stick to them to avoid confusing
everyone.
The only exceptions are IOBAR and LMEMBAR since naming them
IOBAR_BAR and LMEMBAR_BAR looks too funny, and yet I think
that adding the _
== Series Details ==
Series: drm/i915/pxp: Prepare intel_pxp entry points for MTL
URL : https://patchwork.freedesktop.org/series/109429/
State : warning
== Summary ==
Error: dim checkpatch failed
982be24e039b drm/i915/pxp: Make gt and pxp init/fini aware of PXP-owning-GT
-:79: CHECK:MACRO_ARG_
Ensure i915_pxp_tee_component_bind / unbind implicitly sorts out
getting the correct PXP control-context from the PXP-owning-GT
when establishing or ending connection.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 17 +++--
1 file changed, 15 insertions(+)
Make intel_pxp_key_check implicitly find the PXP-owning-GT.
Callers of this function shall now pass in i915 since PXP
is a global GPU feature. Make intel_pxp_key_check implicitly
find the right gt to verify pxp session key establishment count
so it's transparent to the callers.
Signed-off-by: Alan
Make intel_pxp_is_start implicitly find the PXP-owning-GT.
Callers of this function shall now pass in i915 since PXP
is a global GPU feature. Make intel_pxp_start implicitly
find the right gt to start PXP arb session so
it's transparent to the callers.
Signed-off-by: Alan Previn
---
drivers/gpu/
Make intel_pxp_is_active implicitly find the PXP-owning-GT.
As per prior two patches, callers of this function shall now
pass in i915 since PXP is a global GPU feature. Make
intel_pxp_is_active implicitly find the right gt to check if
PXP is active so it's transparent to the callers.
Signed-off-by
MTL has two tiles that is represented by the intel_gt structure in the i915
code. The PXP feature has a control-structure that contains the PXP context
and this hangs of the intel_gt structure. In MTL, the standalone media tile
(i.e. not the root tile) contains the VDBOX and KCR engine which is wha
In preparation for future MTL-PXP feature support, PXP control
context should only valid on the correct gt tile. Depending on the
device-info this mat not necessarily be the root GT tile and
depends on which tile owns the VEBOX and KCR.
PXP is still a global feature (despite the control-context be
Make intel_pxp_is_enabled implicitly find the PXP-owning-GT.
PXP feature support is a device-config flag. In preparation for MTL
PXP control-context shall reside on of the two GT's.
That said, update intel_pxp_is_enabled to take in i915 as its input
and internally find the right gt to check if PXP
On Wed, Oct 05, 2022 at 08:52:51PM +0300, Imre Deak wrote:
> The GPU reset involves a display suspend/resume sequence, but this is
> done without suspending/resuming the encoders.
The display reset path is there for the old platforms which
can't reset the gt stuff separately from the display engin
== Series Details ==
Series: series starting with [1/2] drm/i915: Take display INIT power for GPU
reset/restore
URL : https://patchwork.freedesktop.org/series/109426/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12219 -> Patchwork_109426v1
===
On 10/3/2022 05:00, Tvrtko Ursulin wrote:
On 03/10/2022 08:53, Tvrtko Ursulin wrote:
On 30/09/2022 18:44, John Harrison wrote:
On 9/30/2022 02:22, Tvrtko Ursulin wrote:
On 29/09/2022 17:21, John Harrison wrote:
On 9/29/2022 00:42, Tvrtko Ursulin wrote:
On 29/09/2022 03:18, john.c.harri...@in
== Series Details ==
Series: series starting with [1/2] drm/i915: Take display INIT power for GPU
reset/restore
URL : https://patchwork.freedesktop.org/series/109426/
State : warning
== Summary ==
Error: dim checkpatch failed
b0acff1ebe11 drm/i915: Take display INIT power for GPU reset/restor
== Series Details ==
Series: drm/i915/slpc: Update frequency debugfs for SLPC (rev4)
URL : https://patchwork.freedesktop.org/series/109328/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12219 -> Patchwork_109328v4
Summary
-
== Series Details ==
Series: drm/i915/slpc: Update frequency debugfs for SLPC (rev4)
URL : https://patchwork.freedesktop.org/series/109328/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include
The GPU reset involves a display suspend/resume sequence, but this is
done without suspending/resuming the encoders. The encoder HW readout
code during resume however assumes that the encoders were
suspended/resumed, at least on TypeC platforms where the TC PHYs must be
left in a disconnected state
Restoring the display during a GPU reset is in practice a display
(system) resume sequence, so take the required INIT power for this. So
far this didn't cause a problem as old platforms (where the reset
clobbers display) have only an always-on power well and for new
platforms __intel_display_resume
== Series Details ==
Series: series starting with [1/2] drm/i915: add back GEN12_BDSM_MASK
URL : https://patchwork.freedesktop.org/series/109420/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12219 -> Patchwork_109420v1
Sum
== Series Details ==
Series: series starting with [1/3] drm/i915: Extract intel_mmio_bar()
URL : https://patchwork.freedesktop.org/series/109421/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CH
On Wed, 05 Oct 2022, Jani Nikula wrote:
> On Wed, 05 Oct 2022, Vinay Belgaumkar wrote:
>> Move it to the RPS source file.
>>
>> v2: Separate out code movement and functional changes (Jani)
>>
>> Signed-off-by: Vinay Belgaumkar
>
> Reviewed-by: Jani Nikula
PS. Sorry, I'll leave patch 2 for some
On Wed, 05 Oct 2022, Vinay Belgaumkar wrote:
> Move it to the RPS source file.
>
> v2: Separate out code movement and functional changes (Jani)
>
> Signed-off-by: Vinay Belgaumkar
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 157 +
> drivers
On Wed, Oct 05, 2022 at 05:15:49PM +0100, Robin Murphy wrote:
> On 2022-10-05 16:25, Guenter Roeck wrote:
> > On Wed, Oct 05, 2022 at 04:26:28PM +0200, Thorsten Leemhuis wrote:
> > > [adding the coretemp maintainer (Fenghua Yu) and the appropriate mailing
> > > list to the list of recipients, as th
On Wed, Oct 05, 2022 at 05:02:58PM +0100, Matthew Auld wrote:
> On Wed, 5 Oct 2022 at 16:42, Ville Syrjala
> wrote:
> >
> > From: Ville Syrjälä
> >
> > We use all kinds of weird names for our base address registers.
> > Take the names from the spec and stick to them to avoid confusing
> > everyon
On Wed, Oct 05, 2022 at 04:31:48PM +0100, Matthew Auld wrote:
Restore the previous behaviour here where we compare the
pci_resource_len() with the actual lmem_size, and not the dsm size,
since dsm here is just some subset snipped off the end of the lmem.
Otherwise we will incorrectly report an io
On Wed, Oct 05, 2022 at 04:31:47PM +0100, Matthew Auld wrote:
The mask was added in commit e5f415bfc5c2 ("drm/i915: Add missing mask
when reading GEN12_DSMBASE"), but then looks to be dropped in some
unrelated code movement in commit dbb2ffbfd708 ("drm/i915/mtl: enable
local stolen memory") witho
On 2022-10-05 16:25, Guenter Roeck wrote:
On Wed, Oct 05, 2022 at 04:26:28PM +0200, Thorsten Leemhuis wrote:
[adding the coretemp maintainer (Fenghua Yu) and the appropriate mailing
list to the list of recipients, as there apparently is a coretemp bug
that results in a iommu change causing a reg
On Wed, 5 Oct 2022 at 16:42, Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> The fact that LMEMBAR is BAR2 should be of no real interest
> to anyone. So use the name of the BAR rather than its index.
>
> Signed-off-by: Ville Syrjälä
Acked-by: Matthew Auld
On Wed, 5 Oct 2022 at 16:42, Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> We use all kinds of weird names for our base address registers.
> Take the names from the spec and stick to them to avoid confusing
> everyone.
>
> The only exceptions are IOBAR and LMEMBAR since naming them
> IOBAR_BAR
Read the values stored in the SLPC structures. Remove the
fields that are no longer valid (like RPS interrupts) as
well.
v2: Move all functionality changes to this patch (Jani)
v3: Fix compile warning and if condition (Jani)
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/intel_rps.
Move it to the RPS source file.
v2: Separate out code movement and functional changes (Jani)
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 157 +
drivers/gpu/drm/i915/gt/intel_rps.c | 163 ++
drivers/gpu/drm/i915/gt
Remove the RPS related information that is not valid when
SLPC is enabled.
v2: Add version numbers and address other comments (Jani)
v3: Fix compile warning
Signed-off-by: Vinay Belgaumkar
Vinay Belgaumkar (2):
drm/i915: Add a wrapper for frequency debugfs
drm/i915/slpc: Update the frequenc
On Wed, 5 Oct 2022 at 16:42, Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> We have the same code to determine the MMIO BAR in
> two places. Collect it to a single place.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Matthew Auld
From: Ville Syrjälä
The fact that LMEMBAR is BAR2 should be of no real interest
to anyone. So use the name of the BAR rather than its index.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
driver
From: Ville Syrjälä
We use all kinds of weird names for our base address registers.
Take the names from the spec and stick to them to avoid confusing
everyone.
The only exceptions are IOBAR and LMEMBAR since naming them
IOBAR_BAR and LMEMBAR_BAR looks too funny, and yet I think
that adding the _
From: Ville Syrjälä
We have the same code to determine the MMIO BAR in
two places. Collect it to a single place.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 4 +---
drivers/gpu/drm/i915/intel_pci_config.h | 8 ++
Restore the previous behaviour here where we compare the
pci_resource_len() with the actual lmem_size, and not the dsm size,
since dsm here is just some subset snipped off the end of the lmem.
Otherwise we will incorrectly report an io_size > 0 on small-bar
systems.
It doesn't looks like MTL is ex
The mask was added in commit e5f415bfc5c2 ("drm/i915: Add missing mask
when reading GEN12_DSMBASE"), but then looks to be dropped in some
unrelated code movement in commit dbb2ffbfd708 ("drm/i915/mtl: enable
local stolen memory") without explanation. Add it back.
Fixes: dbb2ffbfd708 ("drm/i915/mtl
On Wed, Oct 05, 2022 at 04:26:28PM +0200, Thorsten Leemhuis wrote:
> [adding the coretemp maintainer (Fenghua Yu) and the appropriate mailing
> list to the list of recipients, as there apparently is a coretemp bug
> that results in a iommu change causing a regression]
>
> On 30.09.22 18:57, Janusz
On 10/5/22 15:32, Matthew Auld wrote:
Hi Thomas,
Thanks for reviewing, Matt.
/Thomas
On 05/10/2022 13:11, Thomas Hellström wrote:
Commit 39a2bd34c933 ("drm/i915: Use the vma resource as argument for gtt
binding / unbinding") introduced a regression that due to the vma
resource
trackin
== Series Details ==
Series: drm/i915/mtl: Add MTP ddc pin configuration
URL : https://patchwork.freedesktop.org/series/109406/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12216_full -> Patchwork_109406v1_full
Summary
---
Hi Thomas,
On 05/10/2022 13:11, Thomas Hellström wrote:
Commit 39a2bd34c933 ("drm/i915: Use the vma resource as argument for gtt
binding / unbinding") introduced a regression that due to the vma resource
tracking of the binding state, dpt ptes were not correctly repopulated.
Fix this by clearing
On Wed, Oct 05, 2022 at 12:25:26PM +, Kahola, Mika wrote:
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: Wednesday, October 5, 2022 2:29 PM
> > To: Kahola, Mika
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Ensure dbuf state is define
== Series Details ==
Series: drm/i915: Fix display problems after resume (rev2)
URL : https://patchwork.freedesktop.org/series/108432/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12217 -> Patchwork_108432v2
Summary
--
== Series Details ==
Series: drm/i915: Ensure dbuf state is defined
URL : https://patchwork.freedesktop.org/series/109414/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12217 -> Patchwork_109414v1
Summary
---
**SUCCE
> -Original Message-
> From: Ville Syrjälä
> Sent: Wednesday, October 5, 2022 2:29 PM
> To: Kahola, Mika
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Ensure dbuf state is defined
>
> On Wed, Oct 05, 2022 at 02:11:58PM +0300, Mika Kahola wrote:
> > En
Commit 39a2bd34c933 ("drm/i915: Use the vma resource as argument for gtt
binding / unbinding") introduced a regression that due to the vma resource
tracking of the binding state, dpt ptes were not correctly repopulated.
Fix this by clearing the vma resource state before repopulating.
The state will
== Series Details ==
Series: drm/connector: connector iterator with filtering
URL : https://patchwork.freedesktop.org/series/109411/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12217 -> Patchwork_109411v1
Summary
---
== Series Details ==
Series: drm/connector: connector iterator with filtering
URL : https://patchwork.freedesktop.org/series/109411/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Wed, Oct 05, 2022 at 02:11:58PM +0300, Mika Kahola wrote:
> Ensure that the new dbuf state is not null. If so, throw
> an error, discontinue to allocate ddb and return.
>
> Signed-off-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 3 +++
> 1 file changed, 3 insertions(
On Wed, 05 Oct 2022, Jiri Slaby wrote:
> On 04. 10. 22, 12:52, Jani Nikula wrote:
>> On Tue, 04 Oct 2022, "Jiri Slaby (SUSE)" wrote:
>>> When DRM_I915=y and BACKLIGHT_CLASS_DEVICE=m, the build fails:
>>> ld: drivers/gpu/drm/i915/display/intel_backlight.o: in function
>>> `intel_backlight_device_
Ensure that the new dbuf state is not null. If so, throw
an error, discontinue to allocate ddb and return.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/skl_watermark.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gp
The drm_connectors that are embedded in writeback connectors won't be
embedded in intel_connectors, so we can't assume being able to convert a
drm_connector to intel_connector when iterating all the connectors we
have. Use the drm connector list filtering to skip writeback connectors.
Note: We cou
Add new function drm_connector_list_iter_filter_begin() to initialize
connector list iterator with a filter function. Subsequent iteration on
the list will only return connectors on which the filter function
returns true.
Cc: Arun R Murthy
Cc: Suraj Kandpal
Cc: Ville Syrjälä
Signed-off-by: Jani
Currently i915 assumes all drm_connectors it encounters are embedded in
intel_connectors that i915 allocated. The drm_writeback_connector forces
a design where this is not the case; we can't provide our own connector,
and writeback embeds the drm_connector it initializes itself.
To use drm writeba
On Mon, 19 Sep 2022, "Kandpal, Suraj" wrote:
> From: Suraj Kandpal
>
> Changing intel_connector iterators as with writeback introduction
> not all drm_connector will be embedded within intel_connector.
>
> Signed-off-by: Suraj Kandpal
> Reviewed-by: Arun R Murthy
> ---
> drivers/gpu/drm/i915/d
== Series Details ==
Series: drm/i915: Enable SDP split for DP2.0
URL : https://patchwork.freedesktop.org/series/109395/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12215_full -> Patchwork_109395v1_full
Summary
---
On Mon, 19 Sep 2022, "Kandpal, Suraj" wrote:
> From: Suraj Kandpal
>
> Adding WD Types, WD transcoder to enum list and WD Transcoder offsets.
> Adding i915 register definitions related to WD transcoder
>
> Signed-off-by: Suraj Kandpal
> Reviewed-by: Arun R Murthy
> ---
> drivers/gpu/drm/i915/d
On Tue, 04 Oct 2022, Vinay Belgaumkar wrote:
> Read the values stored in the SLPC structures. Remove the
> fields that are no longer valid (like RPS interrupts) as
> well.
>
> v2: Move all functionality changes to this patch (Jani)
>
> Signed-off-by: Vinay Belgaumkar
> ---
> drivers/gpu/drm/i915
On 04/10/2022 16:13, Ceraolo Spurio, Daniele wrote:
On 10/4/2022 4:14 AM, Tvrtko Ursulin wrote:
On 03/10/2022 13:16, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Patch which added graceful exit for non-persistent contexts missed the
fact it is not enough to set the exiting flag on a context
On Tue, 04 Oct 2022 06:00:22 -0700, Tvrtko Ursulin wrote:
>
Hi Tvrtko,
>
> On 04/10/2022 10:29, Tvrtko Ursulin wrote:
> >
> > On 03/10/2022 20:24, Ashutosh Dixit wrote:
> >> PMU and sysfs use different wakeref's to "interpret" zero freq. Sysfs
> >> uses
> >> runtime PM wakeref (see intel_rps_read
On Tue, Oct 04, 2022 at 05:25:34PM -0700, Radhakrishna Sripada wrote:
Meteorlake PCH reuses Alderlake ddc pin mapping. Extend
ADL-P pin mapping for Meteorlake.
Cc: Lucas De Marchi
Signed-off-by: Radhakrishna Sripada
This is actually the vbt -> display engine mapping.
Bspec 20124 - worth not
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