[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference

== Series Details == Series: series starting with [1/2] drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference URL : https://patchwork.freedesktop.org/series/99301/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22093_full ==

[Intel-gfx] ✗ Fi.CI.BAT: failure for Fix up request cancel (rev3)

== Series Details == Series: Fix up request cancel (rev3) URL : https://patchwork.freedesktop.org/series/99173/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11130 -> Patchwork_22095 Summary --- **FAILURE** Seriou

Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: Move dsc/joiner enable into hsw_crtc_enable()

On Tue, Jan 25, 2022 at 08:50:47AM +0200, Jani Nikula wrote: > On Tue, 25 Jan 2022, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Lift the dsc/joiner enable up from the wonky places where it > > currently sits (ddi .pre_enable() or icl_ddi_bigjoiner_pre_enable()) > > into hsw_crtc_enable()

Re: [Intel-gfx] [PATCH v2] drm/edid: Support type 7 timings

On Sun, 23 Jan 2022, Yaroslav Bolyukin wrote: > Per VESA DisplayID Standard v2.0: Type VII Timing – Detailed Timing Data > > Definitions were already provided as type I, but not used > > Signed-off-by: Yaroslav Bolyukin Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/drm_edid.c | 12

Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: Move dsc/joiner enable into hsw_crtc_enable()

On Tue, 25 Jan 2022, Ville Syrjala wrote: > From: Ville Syrjälä > > Lift the dsc/joiner enable up from the wonky places where it > currently sits (ddi .pre_enable() or icl_ddi_bigjoiner_pre_enable()) > into hsw_crtc_enable() where we write the other per-pipe stuff > as well. Makes the transcoder

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Fix up request cancel (rev3)

== Series Details == Series: Fix up request cancel (rev3) URL : https://patchwork.freedesktop.org/series/99173/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix up request cancel (rev3)

== Series Details == Series: Fix up request cancel (rev3) URL : https://patchwork.freedesktop.org/series/99173/ State : warning == Summary == $ dim checkpatch origin/drm-tip b01d46d0bed9 drm/i915: Add request cancel low level trace point bf264f6cff19 drm/i915/guc: Cancel requests immediately 0

[Intel-gfx] [PATCH v2 5/5] drm/i915: Move dsc/joiner enable into hsw_crtc_enable()

From: Ville Syrjälä Lift the dsc/joiner enable up from the wonky places where it currently sits (ddi .pre_enable() or icl_ddi_bigjoiner_pre_enable()) into hsw_crtc_enable() where we write the other per-pipe stuff as well. Makes the transcoder vs. pipe split less confusing. For DSI this results i

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate

== Series Details == Series: series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate URL : https://patchwork.freedesktop.org/series/99278/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22089_full =

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Move dsc/joiner enable into hsw_crtc_enable()

On Tue, Jan 25, 2022 at 07:40:04AM +0200, Jani Nikula wrote: > On Mon, 24 Jan 2022, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Lift the dsc/joiner enable up from the wonky places where it > > currently sits (ddi .pre_enable() or icl_ddi_bigjoiner_pre_enable()) > > into hsw_crtc_enable()

Re: [Intel-gfx] [PATCH 1/2] drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference

On Mon, 24 Jan 2022, Umesh Nerlige Ramappa wrote: > All timestamps returned by GuC for GuC PMU busyness are captured from > GUC PM TIMESTAMP. Since this timestamp does not tick when GuC goes idle, > kmd uses RING_TIMESTAMP to measure busyness of an engine with an active > context. In further stre

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Move dsc/joiner enable into hsw_crtc_enable()

On Mon, 24 Jan 2022, Ville Syrjala wrote: > From: Ville Syrjälä > > Lift the dsc/joiner enable up from the wonky places where it > currently sits (ddi .pre_enable() or icl_ddi_bigjoiner_pre_enable()) > into hsw_crtc_enable() where we write the other per-pipe stuff > as well. Makes the transcoder

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] drm/i915: Skip dsc readout if the transcoder is disabled

== Series Details == Series: series starting with [1/5] drm/i915: Skip dsc readout if the transcoder is disabled URL : https://patchwork.freedesktop.org/series/99276/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22088_full

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Extract hsw_configure_cpu_transcoder()

On Mon, 24 Jan 2022, Ville Syrjala wrote: > From: Ville Syrjälä > > Pull the transcoder specific modeset steps into a single place. > With bigoiner we need to keep in mind wheher we're dealing with > the transcoder or the pipe, and a slightly higher level split makes > that easier. > > Signed-off

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Skip dsc readout if the transcoder is disabled

On Mon, 24 Jan 2022, Ville Syrjala wrote: > From: Ville Syrjälä > > Tryingf to do readout when we don't even have a cpu transcoder > is not a great idea. Don't do it. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_display.c | 6 +++--- >

Re: [Intel-gfx] [PATCH 1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate

On Mon, 24 Jan 2022, Ville Syrjala wrote: > From: Ville Syrjälä > > Use DISPLAY_VER rather than GRAPHICS_VER to determine > availability of display hardware features. > > Signed-off-by: Ville Syrjälä On both patches, Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_drv.h | 18

Re: [Intel-gfx] [PATCH] drm/i915/overlay: Prevent divide by zero bugs in scaling

On Mon, Jan 24, 2022 at 03:24:09PM +0300, Dan Carpenter wrote: > Smatch detected a divide by zero bug in check_overlay_scaling(). > > drivers/gpu/drm/i915/display/intel_overlay.c:976 check_overlay_scaling() > error: potential divide by zero bug '/ rec->dst_height'. > drivers/gpu/drm/i9

[Intel-gfx] ✗ Fi.CI.IGT: failure for Fix up request cancel (rev2)

== Series Details == Series: Fix up request cancel (rev2) URL : https://patchwork.freedesktop.org/series/99173/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22087_full Summary --- **FAILURE**

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: make static read-only array page_count const

== Series Details == Series: drm/i915/selftests: make static read-only array page_count const URL : https://patchwork.freedesktop.org/series/99252/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22085_full

[Intel-gfx] ✓ Fi.CI.BAT: success for Second round of i915_reg.h splitting (rev2)

== Series Details == Series: Second round of i915_reg.h splitting (rev2) URL : https://patchwork.freedesktop.org/series/99079/ State : success == Summary == CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22094 Summary --- **SUCC

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/edid: Support type 7 timings

== Series Details == Series: drm/edid: Support type 7 timings URL : https://patchwork.freedesktop.org/series/99250/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22082_full Summary --- **FAILU

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Second round of i915_reg.h splitting (rev2)

== Series Details == Series: Second round of i915_reg.h splitting (rev2) URL : https://patchwork.freedesktop.org/series/99079/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Second round of i915_reg.h splitting (rev2)

== Series Details == Series: Second round of i915_reg.h splitting (rev2) URL : https://patchwork.freedesktop.org/series/99079/ State : warning == Summary == $ dim checkpatch origin/drm-tip 48db4167e8d0 drm/i915/perf: Move OA regs to their own header -:39: WARNING:FILE_PATH_CHANGES: added, move

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference

== Series Details == Series: series starting with [1/2] drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference URL : https://patchwork.freedesktop.org/series/99301/ State : success == Summary == CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22093

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference

== Series Details == Series: series starting with [1/2] drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference URL : https://patchwork.freedesktop.org/series/99301/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each com

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Fix NULL vs IS_ERR checking for kernel_context (rev2)

== Series Details == Series: drm/i915/selftests: Fix NULL vs IS_ERR checking for kernel_context (rev2) URL : https://patchwork.freedesktop.org/series/98685/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22081_full ==

[Intel-gfx] [PATCH v2 2/6] drm/i915/perf: Express OA register ranges with i915_range

Let's use 'struct i915_range' to express sets of b-counter and mux registers in the perf code. This makes the code more similar to how we handle things like multicast register ranges, forcewake tables, shadow tables, etc. and also lets us avoid needing symbolic register name definitions for the va

[Intel-gfx] [PATCH v2 1/6] drm/i915/perf: Move OA regs to their own header

The OA unit registers are only used by the perf code; move them to their own header file. Cc: Jani Nikula Cc: Umesh Nerlige Ramappa Cc: Lionel Landwerlin Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gvt/scheduler.c | 1 + drivers/gpu/drm/i915/i915_perf.c | 1 + drivers/g

[Intel-gfx] [PATCH v2 4/6] drm/i915: Parameterize MI_PREDICATE registers

The various MI_PREDICATE registers have per-engine instances. Today we only utilize the RCS0 instance of each, but that will likely change in the future; switch to parameterized register definitions to make these easier to work with going forward. Of special note is MI_PREDICATE_RESULT_2; we only

[Intel-gfx] [PATCH v2 3/6] drm/i915: Parameterize R_PWR_CLK_STATE register definition

At the moment we only use R_PWR_CLK_STATE in the context of the RCS engine, but upcoming support for compute engines will start using instances relative to the CCS engine base offsets. Let's parameterize the register and move it to the engine reg header. Cc: Jani Nikula Signed-off-by: Matt Roper

[Intel-gfx] [PATCH v2 6/6] drm/i915: Only include i915_reg.h from .c files

Several of our i915 header files, have been including i915_reg.h. This means that any change to i915_reg.h will trigger a full rebuild of pretty much every file of the driver, even those that don't have any kind of register access. Let's delete the i915_reg.h include from all headers and include

[Intel-gfx] [PATCH v2 0/6] Second round of i915_reg.h splitting

Let's continue to split our giant i915_reg.h file into more logical domain-specific headers. In addition to a bunch of register definition segregation, the final patch of this series ensures that i915_reg.h is only #include'd from .c files that truly need its definitions (and removes all of the pl

[Intel-gfx] [PATCH 1/2] drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference

All timestamps returned by GuC for GuC PMU busyness are captured from GUC PM TIMESTAMP. Since this timestamp does not tick when GuC goes idle, kmd uses RING_TIMESTAMP to measure busyness of an engine with an active context. In further stress testing, the MMIO read of the RING_TIMESTAMP is seen to c

[Intel-gfx] [PATCH 2/2] drm/i915/pmu: Fix KMD and GuC race on accessing busyness

GuC updates shared memory and KMD reads it. Since this is not synchronized, we run into a race where the value read is inconsistent. Sometimes the inconsistency is in reading the upper MSB bytes of the last_switch_in value. 2 types of cases are seen - upper 8 bits are zero and upper 24 bits are zer

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/rpl-s: Add stepping info (rev3)

== Series Details == Series: drm/i915/rpl-s: Add stepping info (rev3) URL : https://patchwork.freedesktop.org/series/99162/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22092 Summary --- **FAILURE

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/rpl-s: Add stepping info (rev2)

== Series Details == Series: drm/i915/rpl-s: Add stepping info (rev2) URL : https://patchwork.freedesktop.org/series/99162/ State : success == Summary == CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22091 Summary --- **SUCCESS

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/rpl-s: Add stepping info (rev3)

== Series Details == Series: drm/i915/rpl-s: Add stepping info (rev3) URL : https://patchwork.freedesktop.org/series/99162/ State : warning == Summary == $ dim checkpatch origin/drm-tip adb56d9bb11b drm/i915/rpl-s: Add stepping info -:38: CHECK:LINE_SPACING: Please don't use multiple blank lin

Re: [Intel-gfx] [v2] drm/i915/rpl-s: Add stepping info

> -Original Message- > From: Roper, Matthew D > Sent: Monday, January 24, 2022 5:06 PM > To: Srivatsa, Anusha > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [v2] drm/i915/rpl-s: Add stepping info > > On Mon, Jan 24, 2022 at 04:16:35PM -0800, Anusha Srivatsa wrote: > > Add steppi

Re: [Intel-gfx] [v2] drm/i915/rpl-s: Add stepping info

On Mon, Jan 24, 2022 at 04:16:35PM -0800, Anusha Srivatsa wrote: > Add stepping-substepping info in > accordance to BSpec changes. > Though it looks weird, the revision ID > for the newer stepping is indeed backwards > and is in accordance to the spec. > > v2: Rearrange the platforms in logical or

[Intel-gfx] [RESEND] drm/i915/rpl-s: Add stepping info

Add stepping-substepping info in accordance to BSpec changes. Though it looks weird, the revision ID for the newer stepping is indeed backwards and is in accordance to the spec. v2: Rearrange the platforms in logical order (Matt) Bspec: 53655 Cc: Roper, Matthew D Signed-off-by: Anusha Srivatsa

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/rpl-s: Add stepping info (rev2)

== Series Details == Series: drm/i915/rpl-s: Add stepping info (rev2) URL : https://patchwork.freedesktop.org/series/99162/ State : warning == Summary == $ dim checkpatch origin/drm-tip ae8b0b24992a drm/i915/rpl-s: Add stepping info -:38: CHECK:LINE_SPACING: Please don't use multiple blank lin

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate

== Series Details == Series: series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate URL : https://patchwork.freedesktop.org/series/99278/ State : success == Summary == CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22089 ===

[Intel-gfx] ✗ Fi.CI.BUILD: failure for linux-next: manual merge of the drm-intel-gt tree with the drm-intel tree

== Series Details == Series: linux-next: manual merge of the drm-intel-gt tree with the drm-intel tree URL : https://patchwork.freedesktop.org/series/99294/ State : failure == Summary == Applying: linux-next: manual merge of the drm-intel-gt tree with the drm-intel tree error: sha1 informati

[Intel-gfx] [v2] drm/i915/rpl-s: Add stepping info

Add stepping-substepping info in accordance to BSpec changes. Though it looks weird, the revision ID for the newer stepping is indeed backwards and is in accordance to the spec. v2: Rearrange the platforms in logical order (Matt) Bspec: 53655 Cc: Roper, Matthew D Signed-off-by: Anusha Srivatsa

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate

== Series Details == Series: series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate URL : https://patchwork.freedesktop.org/series/99278/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be ch

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate

== Series Details == Series: series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate URL : https://patchwork.freedesktop.org/series/99278/ State : warning == Summary == $ dim checkpatch origin/drm-tip cf24e52f7816 drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropri

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Skip dsc readout if the transcoder is disabled

== Series Details == Series: series starting with [1/5] drm/i915: Skip dsc readout if the transcoder is disabled URL : https://patchwork.freedesktop.org/series/99276/ State : success == Summary == CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22088 ==

[Intel-gfx] ✓ Fi.CI.BAT: success for Fix up request cancel (rev2)

== Series Details == Series: Fix up request cancel (rev2) URL : https://patchwork.freedesktop.org/series/99173/ State : success == Summary == CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22087 Summary --- **SUCCESS** No reg

[Intel-gfx] linux-next: manual merge of the drm-intel-gt tree with the drm-intel tree

Hi all, Today's linux-next merge of the drm-intel-gt tree got a conflict in: drivers/gpu/drm/i915/i915_drv.h between commit: 2ef97818d3aa ("drm/i915: split out i915_gem_evict.h from i915_drv.h") from the drm-intel tree and commit: 7e00897be8bf ("drm/i915: Add object locking to i915_gem_

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Fix up request cancel (rev2)

== Series Details == Series: Fix up request cancel (rev2) URL : https://patchwork.freedesktop.org/series/99173/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix up request cancel (rev2)

== Series Details == Series: Fix up request cancel (rev2) URL : https://patchwork.freedesktop.org/series/99173/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9d38a07fb177 drm/i915: Add request cancel low level trace point f478dcc4fbab drm/i915/guc: Cancel requests immediately b

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: make static read-only array page_count const

== Series Details == Series: drm/i915/selftests: make static read-only array page_count const URL : https://patchwork.freedesktop.org/series/99252/ State : success == Summary == CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22085 Summ

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/overlay: Prevent divide by zero bugs in scaling

== Series Details == Series: drm/i915/overlay: Prevent divide by zero bugs in scaling URL : https://patchwork.freedesktop.org/series/99242/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11128_full -> Patchwork_22079_full Su

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Async flip optimization for DG2 (rev8)

== Series Details == Series: Async flip optimization for DG2 (rev8) URL : https://patchwork.freedesktop.org/series/98981/ State : failure == Summary == Applying: drm/i915: Pass plane to watermark calculation functions Applying: drm/i915: Introduce do_async_flip flag to intel_plane_state Applyi

[Intel-gfx] linux-next: manual merge of the drm-intel tree with Linus' tree

Hi all, Today's linux-next merge of the drm-intel tree got a conflict in: drivers/gpu/drm/i915/intel_pm.c between commit: cca084692394 ("drm/i915: Use per device iommu check") from Linus' tree and commit: 8172375ea95a ("drm/i915: Remove zombie async flip vt-d w/a") from the drm-intel t

[Intel-gfx] linux-next: manual merge of the drm-intel tree with Linus' tree

Hi all, Today's linux-next merge of the drm-intel tree got a conflict in: drivers/gpu/drm/i915/i915_reg.h between commit: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to pmu") from Linus' tree and commit: 202b1f4c1234 ("drm/i915/gt: Move engine registers to their

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: make static read-only array page_count const

== Series Details == Series: drm/i915/selftests: make static read-only array page_count const URL : https://patchwork.freedesktop.org/series/99252/ State : warning == Summary == $ dim checkpatch origin/drm-tip fb32ff7638fd drm/i915/selftests: make static read-only array page_count const -:24:

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/11] drm/radeon: use ttm_resource_manager_debug

== Series Details == Series: series starting with [01/11] drm/radeon: use ttm_resource_manager_debug URL : https://patchwork.freedesktop.org/series/99249/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22083 ===

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Add basic support for flat-CCS bo evictions

== Series Details == Series: Add basic support for flat-CCS bo evictions URL : https://patchwork.freedesktop.org/series/99248/ State : failure == Summary == Applying: drm/i915/flat-CCS: Add GEM bo structure fields for flat-CCS Applying: drm/i915/flat-CCS: Add flat CCS plane capabilities and mo

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/11] drm/radeon: use ttm_resource_manager_debug

== Series Details == Series: series starting with [01/11] drm/radeon: use ttm_resource_manager_debug URL : https://patchwork.freedesktop.org/series/99249/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separa

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/11] drm/radeon: use ttm_resource_manager_debug

== Series Details == Series: series starting with [01/11] drm/radeon: use ttm_resource_manager_debug URL : https://patchwork.freedesktop.org/series/99249/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5647bdbd9dd6 dma-buf: consolidate dma_fence subclass checking -:117: WARNING:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: Support type 7 timings

== Series Details == Series: drm/edid: Support type 7 timings URL : https://patchwork.freedesktop.org/series/99250/ State : success == Summary == CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22082 Summary --- **SUCCESS** No

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/edid: Support type 7 timings

== Series Details == Series: drm/edid: Support type 7 timings URL : https://patchwork.freedesktop.org/series/99250/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9735d3ddba6d drm/edid: Support type 7 timings -:24: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #24: F

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Fix NULL vs IS_ERR checking for kernel_context (rev2)

== Series Details == Series: drm/i915/selftests: Fix NULL vs IS_ERR checking for kernel_context (rev2) URL : https://patchwork.freedesktop.org/series/98685/ State : success == Summary == CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22081

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Lock dpt_obj around set_cache_level.

== Series Details == Series: drm/i915: Lock dpt_obj around set_cache_level. URL : https://patchwork.freedesktop.org/series/99245/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22080 Summary --- **F

Re: [Intel-gfx] [PATCH 01/11] drm/radeon: use ttm_resource_manager_debug

Am 24.01.22 um 17:33 schrieb Thomas Hellström: On Mon, 2022-01-24 at 14:03 +0100, Christian König wrote: Instead of calling the debug operation directly. Signed-off-by: Christian König Reviewed-by: Huang Rui The first two patches seem unrelated to the series. No idea what happened here, th

Re: [Intel-gfx] [PATCH 06/11] dma-buf: warn about containers in dma_resv object

Am 24.01.22 um 17:36 schrieb Thomas Hellström (Intel): On 1/24/22 14:03, Christian König wrote: Drivers should not add containers as shared fences to the dma_resv object, instead each fence should be added individually. Signed-off-by: Christian König Reviewed-by: Daniel Vetter Reviewed-by:

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Lock dpt_obj around set_cache_level.

== Series Details == Series: drm/i915: Lock dpt_obj around set_cache_level. URL : https://patchwork.freedesktop.org/series/99245/ State : warning == Summary == $ dim checkpatch origin/drm-tip f8d0f6b03553 drm/i915: Lock dpt_obj around set_cache_level. -:8: WARNING:COMMIT_LOG_LONG_LINE: Possibl

Re: [Intel-gfx] [PATCH 2/7] drm/i915/guc: Add XE_LP registers for GuC error state capture.

Internal feedback is to exactly match the register dumps output as it did in execlist, however it seems that the register dump function in execlist targetting the GT subsystem also includes non-GT registers like display-related ones that GuC doesn't manage. So for that, I will have to break up the

[Intel-gfx] [PATCH 2/2] drm/i915: Introduce ilk_pch_pre_enable()

From: Ville Syrjälä Complete the ilk pch modeset abstraction by adding ilk_pch_pre_enable(). I did the disable vs. post_disable split already for the disable sequence, but the enable sequence was still left with the naked ilk_fdi_pll_enable() call for some reason. Signed-off-by: Ville Syrjälä -

[Intel-gfx] [PATCH 1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate

From: Ville Syrjälä Use DISPLAY_VER rather than GRAPHICS_VER to determine availability of display hardware features. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.h | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915

[Intel-gfx] [PATCH 4/5] drm/i915: Extract hsw_configure_cpu_transcoder()

From: Ville Syrjälä Pull the transcoder specific modeset steps into a single place. With bigoiner we need to keep in mind wheher we're dealing with the transcoder or the pipe, and a slightly higher level split makes that easier. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/int

[Intel-gfx] [PATCH 5/5] drm/i915: Move dsc/joiner enable into hsw_crtc_enable()

From: Ville Syrjälä Lift the dsc/joiner enable up from the wonky places where it currently sits (ddi .pre_enable() or icl_ddi_bigjoiner_pre_enable()) into hsw_crtc_enable() where we write the other per-pipe stuff as well. Makes the transcoder vs. pipe split less confusing. Signed-off-by: Ville S

[Intel-gfx] [PATCH 3/5] drm/i915: Use per-device debugs for bigjoiner stuff

From: Ville Syrjälä Specify which device we're talking about when spewing bigjoiner debugs. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 22 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/

[Intel-gfx] [PATCH 2/5] drm/i915: Simplify intel_dsc_source_support()

From: Ville Syrjälä We can simplify the icl check in intel_dsc_source_support() by noting that the only case when DSC is not supported is when using transcoder A. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vdsc.c | 7 +-- 1 file changed, 1

[Intel-gfx] [PATCH 1/5] drm/i915: Skip dsc readout if the transcoder is disabled

From: Ville Syrjälä Tryingf to do readout when we don't even have a cpu transcoder is not a great idea. Don't do it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/disp

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2

On Mon, Jan 24, 2022 at 03:52:34PM +0200, Stanislav Lisovskiy wrote: > In terms of async flip optimization we don't to allocate > extra ddb space, so lets skip it. > > v2: - Extracted min ddb async flip check to separate function > (Ville Syrjälä) > - Used this function to prevent false

Re: [Intel-gfx] [PATCH V2 0/7] DRM kmap() fixes and kmap_local_page() conversions

On Mon, Jan 24, 2022 at 01:08:26PM +0100, Christian König wrote: > Am 24.01.22 um 02:54 schrieb ira.we...@intel.com: > > From: Ira Weiny > > > > Changes from V1: > > Use memcpy_to_page() where appropriate > > Rebased to latest > > > > The kmap() call may cause issues with work being done

Re: [Intel-gfx] [RFC PATCH 5/5] drm/i915/flat-CCS: handle creation and destruction of flat CCS bo's

On Mon, 2022-01-24 at 17:24 +0100, Thomas Hellström wrote: > Hi, Adrian > > On 1/21/22 23:22, Adrian Larumbe wrote: > > When a flat-CCS lmem-bound BO is evicted onto smem for the first > > time, a > > separate swap gem object is created to hold the contents of the CCS > > block. > > It is assumed

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/overlay: Prevent divide by zero bugs in scaling

== Series Details == Series: drm/i915/overlay: Prevent divide by zero bugs in scaling URL : https://patchwork.freedesktop.org/series/99242/ State : success == Summary == CI Bug Log - changes from CI_DRM_11128 -> Patchwork_22079 Summary

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg2: Add Wa_18018781329 (rev7)

On Sun, Jan 23, 2022 at 11:33:55PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/dg2: Add Wa_18018781329 (rev7) > URL : https://patchwork.freedesktop.org/series/99128/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_11120_full -> Patchwork_22072_f

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: fix header file inclusion for might_alloc() (rev4)

== Series Details == Series: drm/i915: fix header file inclusion for might_alloc() (rev4) URL : https://patchwork.freedesktop.org/series/99215/ State : failure == Summary == Applying: drm/i915: fix header file inclusion for might_alloc() Using index info to reconstruct a base tree... M d

Re: [Intel-gfx] [PATCH 2/3] drm/arm/komeda : change driver to use drm_writeback_connector.base pointer

This makes sense given the other patches in your series, but it seems as yet no one has anything to say about this. I don't have anything specific to comment on other than it seems to make the correct changes to komeda given the rest. Reviewed-by: Carsten Haitzler On 1/11/22 10:18, Kandpal,

Re: [Intel-gfx] [PATCH 08/11] dma-buf: add dma_fence_chain_contained helper

On 1/24/22 14:03, Christian König wrote: It's a reoccurring pattern that we need to extract the fence from a dma_fence_chain object. Add a helper for this. Signed-off-by: Christian König Reviewed-by: Thomas Hellström --- drivers/dma-buf/dma-fence-chain.c | 6 ++ include/linux/dm

Re: [Intel-gfx] [PATCH 06/11] dma-buf: warn about containers in dma_resv object

On 1/24/22 14:03, Christian König wrote: Drivers should not add containers as shared fences to the dma_resv object, instead each fence should be added individually. Signed-off-by: Christian König Reviewed-by: Daniel Vetter Reviewed-by: Thomas Hellström Is there any indication that this t

Re: [Intel-gfx] [PATCH 01/11] drm/radeon: use ttm_resource_manager_debug

On Mon, 2022-01-24 at 14:03 +0100, Christian König wrote: > Instead of calling the debug operation directly. > > Signed-off-by: Christian König > Reviewed-by: Huang Rui The first two patches seem unrelated to the series. Also is there a chance of a series cover-letter? Thanks, Thomas > ---

Re: [Intel-gfx] [PATCH 04/11] dma-buf: warn about dma_fence_array container rules v2

On Mon, 2022-01-24 at 14:03 +0100, Christian König wrote: > It's not allowed to nest another dma_fence container into a > dma_fence_array > or otherwise we can run into recursion. > > Warn about that when we create a dma_fence_array. > > v2: fix comment style and typo in the warning pointed out b

Re: [Intel-gfx] [RFC PATCH 5/5] drm/i915/flat-CCS: handle creation and destruction of flat CCS bo's

Hi, Adrian On 1/21/22 23:22, Adrian Larumbe wrote: When a flat-CCS lmem-bound BO is evicted onto smem for the first time, a separate swap gem object is created to hold the contents of the CCS block. It is assumed that, for a flat-CCS bo to be migrated back onto lmem, it should've begun its life

Re: [Intel-gfx] [PATCH V2 3/7] drm/gma: Remove calls to kmap()

On Sun, Jan 23, 2022 at 05:54:05PM -0800, ira.we...@intel.com wrote: > From: Ira Weiny > > kmap() is being deprecated and these instances are easy to convert to > kmap_local_page(). > > Furthermore, in gma_crtc_cursor_set() use the memcpy_from_page() helper > instead of an open coded use of kmap

Re: [Intel-gfx] [RFC PATCH 4/5] drm/i915/flat-CCS: handle CCS block blit for bo migrations

On Fri, 21 Jan 2022, Adrian Larumbe wrote: > Because the smem-evicted bo that holds the CCS block has to be blitted > separately from the original compressed bo, two sets of PTEs have to > be emitted for every bo copy. > > This commit is partially based off another commit from Ramalingam C > , cur

Re: [Intel-gfx] [RFC PATCH 3/5] drm/i915/flat-CCS: move GET_CCS_SIZE macro into driver-wide header

On Fri, 21 Jan 2022, Adrian Larumbe wrote: > It has to be used by other files other than low-level migration code. Maybe, but i915_drv.h is not the dumping ground for this stuff. Especially you shouldn't add anything in i915_drv.h that requires you to pull in other headers. The goal is to go in t

Re: [Intel-gfx] [PATCH] drm/i915: Lock dpt_obj around set_cache_level.

On 1/24/22 14:02, Maarten Lankhorst wrote: set_cache_level may unbind the object, which will result in the below lockdep splat: <6> [184.578145] [IGT] kms_addfb_basic: starting subtest addfb25-framebuffer-vs-set-tiling <4> [184.578220] [ cut here ] <4> [184.578221] WARN

Re: [Intel-gfx] [PATCH 11/11] drm/vmwgfx: remove vmw_wait_dma_fence

On Mon, 2022-01-24 at 14:03 +0100, Christian König wrote: > Decomposing fence containers don't seem to make any sense here. > > So just remove the function entirely and call dma_fence_wait() > directly. > > Signed-off-by: Christian König > Cc: VMware Graphics > Cc: Zack Rusin Looks good. That

[Intel-gfx] [PATCH 3/4] drm/i915/execlists: Fix execlists request cancellation corner case

More than 1 request can be submitted to a single ELSP at a time if multiple requests are ready run to on the same context. When a request is canceled it is marked bad, an idle pulse is triggered to the engine (high priority kernel request), the execlists scheduler sees that running request is bad a

[Intel-gfx] [PATCH 2/4] drm/i915/guc: Cancel requests immediately

Change the preemption timeout to the smallest possible value (1 us) when disabling scheduling to cancel a request and restore it after cancellation. This not only cancels the request as fast as possible, it fixes a bug where the preemption timeout is 0 which results in the schedule disable hanging

[Intel-gfx] [PATCH 1/4] drm/i915: Add request cancel low level trace point

Add request cancel trace point guarded by CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINT. Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/intel_context.h | 1 + drivers/gpu/drm/i915/i915_trace.h | 10 ++ 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_

[Intel-gfx] [PATCH 0/4] Fix up request cancel

Fix request cancellation + add request cancel low level trace point. v2: - Update cancel reset selftest preemption timeout value to zero - Fix bug in execlists cancel code Signed-off-by: Matthew Brost Matthew Brost (4): drm/i915: Add request cancel low level trace point drm/i915/guc: Ca

[Intel-gfx] [PATCH 4/4] drm/i915/selftests: Set preemption timeout to zero in cancel reset test

Set the preemption timeout to zero to prove that request cancellation with preemption disabled works. Also this seals a race between a possible preemption and request cancellation. Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/selftests/i915_request.c | 7 --- 1 file changed, 4 inser

Re: [Intel-gfx] [PATCH 0/9] drm/i915/display: drm device based logging conversions

On Fri, 21 Jan 2022, Ville Syrjälä wrote: > On Fri, Jan 21, 2022 at 03:00:29PM +0200, Jani Nikula wrote: >> Purge some accumulated drm device based logging changes from my local >> branches. >> >> Jani Nikula (9): >> drm/i915/snps: convert to drm device based logging >> drm/i915/pps: convert

[Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2

In terms of async flip optimization we don't to allocate extra ddb space, so lets skip it. v2: - Extracted min ddb async flip check to separate function (Ville Syrjälä) - Used this function to prevent false positive WARN to be triggered(Ville Syrjälä) v3: - Renamed dg2_need_min_dd

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