== Series Details ==
Series: drm/i915/debugfs: xelpd lpsp capability
URL : https://patchwork.freedesktop.org/series/92364/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10324_full -> Patchwork_20563_full
Summary
---
Hi Vinay,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next drm/drm-next v5.13 next-20210709]
[If your patch is applied to the wrong git tree
On Thu, Jul 08, 2021 at 02:18:27PM -0700, José Roberto de Souza wrote:
> This workaround is also applicable to xelpd display so extending it.
>
> Cc: Gwan-gyeong Mun
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 4
On Thu, Jul 08, 2021 at 02:18:26PM -0700, José Roberto de Souza wrote:
> Alderlake-P have different values for MBUS DBOX A credits depending
> if MBUS join is enabled or not.
>
> BSpec: 50343
> BSpec: 54369
> Cc: Matt Atwood
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/di
== Series Details ==
Series: drm/i915: Add TTM offset argument to mmap. (rev2)
URL : https://patchwork.freedesktop.org/series/92103/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10324_full -> Patchwork_20562_full
Summary
-
On Thu, Jul 08, 2021 at 02:18:25PM -0700, José Roberto de Souza wrote:
> This workaround is not needed for platforms with display 13.
>
> Cc: Gwan-gyeong Mun
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 9 +---
Hi Vinay,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next drm/drm-next v5.13 next-20210709]
[If your patch is applied to the wrong git tree
On Thu, Jul 08, 2021 at 02:18:23PM -0700, José Roberto de Souza wrote:
> BSpec: 54370
> Cc: Gwan-gyeong Mun
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff
On Thu, Jul 08, 2021 at 02:18:22PM -0700, José Roberto de Souza wrote:
> Same bit was required for Wa_14012131227 in DG1 now it is also
This is a DG1-specific number; the general lineage number given here and
in the comment should be 22011054531 (and this lineage number does apply
to TGL, RKL, ADL
On Thu, Jul 08, 2021 at 02:18:21PM -0700, José Roberto de Souza wrote:
> From: Lucas De Marchi
>
> Most of the places are using this format so lets consolidate it.
>
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915
== Series Details ==
Series: Minor revid/stepping and workaround cleanup (rev2)
URL : https://patchwork.freedesktop.org/series/92299/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10329 -> Patchwork_20568
Summary
---
== Series Details ==
Series: Minor revid/stepping and workaround cleanup (rev2)
URL : https://patchwork.freedesktop.org/series/92299/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
602f2fe49dc0 drm/i915/step: s/_revid_tbl/_revids
023cab2a2100 drm/i915: Make pre-production detect
On Fri, Jul 09, 2021 at 05:16:34PM -0700, John Harrison wrote:
> On 6/24/2021 00:04, Matthew Brost wrote:
> > When running the GuC the GPU can't be considered idle if the GuC still
> > has contexts pinned. As such, a call has been added in
> > intel_gt_wait_for_idle to idle the UC and in turn the G
On Thu, Jul 08, 2021 at 11:08:46AM -0700, Srivatsa, Anusha wrote:
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of
> > Matt Roper
> > Sent: Wednesday, July 7, 2021 10:38 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH 1/7] drm/i915: Make pre-producti
Switch RKL to use a revid->stepping table as we're trying to do on all
platforms going forward.
Bspec: 44501
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 8 ++--
drivers/gpu/drm/i915/intel_step.c| 9 ++
Switch JSL/EHL to use a revid->stepping table as we're trying to do on
all platforms going forward.
Bspec: 29153
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h
Switch SKL to use a revid->stepping table as we're trying to do on all
platforms going forward. Also drop the preproduction revisions and add
the newer steppings we hadn't already handled.
Note that SKL has a case where a newer revision ID corresponds to an
older GT/disp stepping (0x9 -> STEP_J0,
Switch BXT to use a revid->stepping table as we're trying to do on all
platforms going forward. Note that the REVID macros we had before
weren't being used anywhere in the code and weren't even correct; the
table values come from the bspec (and omits all the placeholder and
preproduction revisions
From: Anusha Srivatsa
Simplify the stepping info array name.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_step.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel
Switch GLK to use a revid->stepping table as we're trying to do on all
platforms going forward. Pre-production and placeholder revisions are
omitted.
Although nothing in the code is using the data from this table at the
moment, we expect some upcoming DMC patches to start utilizing it.
Bspec: 19
All of the Cannon Lake hardware that came out had graphics fused off,
and our userspace drivers have already dropped their support for the
platform; CNL-specific code in i915 that isn't inherited by subsequent
platforms is effectively dead code. Let's remove all of the
CNL-specific workarounds as
Switch ICL to use a revid->stepping table as we're trying to do on all
platforms going forward. While we're at it, let's include some
additional steppings that have popped up, even if we don't yet have any
workarounds tied to those steppings (we probably need to audit our
workaround list soon to s
Although we're converting our workarounds to use a revid->stepping
lookup table, the function that detects pre-production hardware should
continue to compare against PCI revision ID values directly. These are
listed in the bspec as integers, so it's easier to confirm their
correctness if we just u
We're past the point at which we usually drop workarounds that were
never needed on production hardware. The driver will already print an
error and apply taint if loaded on pre-production hardware.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 39 --
Switch DG1 to use a revid->stepping table as we're trying to do on all
platforms going forward.
This removes the last use of IS_REVID() and REVID_FOREVER, so remove
those now-unused macros as well to prevent their accidental use on
future platforms.
Bspec: 44463
Signed-off-by: Matt Roper
---
..
PCI revision IDs don't always map to GT and display IP steppings in an
intuitive/sensible way. On many of our recent platforms we've switched
to using revid->stepping lookup tables with the infrastructure in
intel_step.c to handle stepping lookups and comparisons. This series
converts several of
We're long past the point where we need to care about pre-production
hardware, and we already warn the user and taint the kernel if we detect
the driver is being loaded on pre-production hardware.
Bspec: 18329
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_step.c | 1 -
1 file changed,
On Fri, Jul 09, 2021 at 03:59:11PM -0700, John Harrison wrote:
> On 6/24/2021 00:04, Matthew Brost wrote:
> > Extend the deregistration context fence to fence whne a GuC context has
> > scheduling disable pending.
> >
> > Cc: John Harrison
> > Signed-off-by: Matthew Brost
> > ---
> > .../gpu/d
== Series Details ==
Series: drm/i915: Add missing docbook chapters for i915 uapi.
URL : https://patchwork.freedesktop.org/series/92359/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10324_full -> Patchwork_20561_full
Summa
Hi Vinay,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next drm/drm-next v5.13 next-20210709]
[If your patch is applied to the wrong git tree
On Fri, Jul 09, 2021 at 03:53:29PM -0700, John Harrison wrote:
> On 6/24/2021 00:04, Matthew Brost wrote:
> > Disable engine barriers for unpinning with GuC. This feature isn't
> > needed with the GuC as it disables context scheduling before unpinning
> > which guarantees the HW will not reference
== Series Details ==
Series: Enable GuC based power management features
URL : https://patchwork.freedesktop.org/series/92391/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10329 -> Patchwork_20567
Summary
---
**FAILU
== Series Details ==
Series: Enable GuC based power management features
URL : https://patchwork.freedesktop.org/series/92391/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/g
== Series Details ==
Series: Enable GuC based power management features
URL : https://patchwork.freedesktop.org/series/92391/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d9063ce26607 drm/i915/guc: Squashed patch - DO NOT REVIEW
-:21: WARNING:BAD_SIGN_OFF: Duplicate signature
This feature hands over the control of HW RC6 to the GUC.
GUC decides when to put HW into RC6 based on it's internal
busyness algorithms.
GUCRC needs GUC submission to be enabled, and only
supported on Gen12+ for now.
When GUCRC is enabled, do not set HW RC6. Use a H2G message
to tell guc to enab
Tests that exercise the slpc get/set frequency interfaces.
Clamp_max will set max frequency to multiple levels and check
that slpc requests frequency lower than or equal to it.
Clamp_min will set min frequency to different levels and check
if slpc requests are higher or equal to those levels.
Si
Update the get/set min/max freq hooks to work for
slpc case as well. Consolidate helpers for requested/min/max
frequency get/set to intel_rps where the proper action can
be taken depending on whether slpc is enabled.
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Su
SLPC requests efficient frequency by default instead of min.
It provides a flag to turn this off. Set that flag to maintain
original semantics so that tests do not fail. SLPC can also
request frequency that is much higher than the platform max,
update that as well for the same reason.
Signed-off-b
Cache rp0, rp1 and rpn platform limits into slpc structure
for range checking while setting min/max frequencies.
Also add "soft" limits which keep track of frequency changes
made from userland. These are initially set to platform min
and max.
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/
This interrupt is enabled during RPS initialization, and
now needs to be done by slpc code. It allows ARAT timer
expiry interrupts to get forwarded to GuC.
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 16
drivers/gpu/drm/i915/gt/uc/intel_guc_
This prints out relevant SLPC info from the SLPC shared structure.
We will send a h2g message which forces SLPC to update the
shared data structure with latest information before reading it.
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
.../gpu/drm/i915/gt/uc/intel_gu
Add helpers to read the min/max frequency being used
by SLPC. This is done by send a h2g command which forces
SLPC to update the shared data struct which can then be
read.
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 58 ++
Add param set h2g helpers to set the min and max frequencies
for use by SLPC.
Signed-off-by: Sundaresan Sujaritha
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 94 +
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 +
2 files changed, 96 i
Add methods for interacting with guc for enabling SLPC. Enable
SLPC after guc submission has been established. GuC load will
fail if SLPC cannot be successfully initialized. Add various
helper methods to set/unset the parameters for SLPC. They can
be set using h2g calls or directly setting bits in
Allocate data structures for SLPC and functions for
initializing on host side.
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 11 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 36 -
drivers/gpu/dr
Replicate the SLPC header file in GuC for the most part. There are
some SLPC mode based parameters which haven't been included since
we are not using them.
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 4 +
drivers/gpu/
Declare header and source files for SLPC, along with init and
enable/disable function templates.
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 ++
drivers/gpu/drm/i915/
Disable RPS when slpc is enabled. Also ensure uc_init is called
before we initialize RPS so that we can check for slpc support.
We do not need to enable up/down interrupts when slpc is enabled.
However, we still need the ARAT interrupt, which will be enabled
separately.
Signed-off-by: Vinay Belgau
Add macros to check for slpc support. This feature is currently supported
for gen12+ and enabled whenever guc submission is enabled/selected.
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c
This series enables Single Loop Power Control (SLPC) feature in GuC.
GuC implements various power management algorithms as part of it's
operation. These need to be specifically enabled by KMD. They replace
the legacy host based management of these features.
With this series, we will enable two PM
On 6/24/2021 00:04, Matthew Brost wrote:
When running the GuC the GPU can't be considered idle if the GuC still
has contexts pinned. As such, a call has been added in
intel_gt_wait_for_idle to idle the UC and in turn the GuC by waiting for
the number of unpinned contexts to go to zero.
v2: rtime
On 6/24/2021 00:04, Matthew Brost wrote:
Semaphores are an optimization and not required for basic GuC submission
to work properly. Disable until we have time to do the implementation to
enable semaphores and tune them for performance. Also long direction is
just to delete semaphores from the i91
On 6/24/2021 00:04, Matthew Brost wrote:
Disable preempt busywait when using GuC scheduling. This isn't need as
needed
the GuC control preemption when scheduling.
controls
With the above fixed:
Reviewed-by: John Harrison
Cc: John Harrison
Signed-off-by: Matthew Brost
---
drivers/gpu
On 6/24/2021 00:04, Matthew Brost wrote:
Extend the deregistration context fence to fence whne a GuC context has
scheduling disable pending.
Cc: John Harrison
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++
1 file changed, 30 insertio
On 6/24/2021 00:04, Matthew Brost wrote:
Disable engine barriers for unpinning with GuC. This feature isn't
needed with the GuC as it disables context scheduling before unpinning
which guarantees the HW will not reference the context. Hence it is
not necessary to defer unpinning until a kernel co
On 6/24/2021 00:04, Matthew Brost wrote:
With GuC scheduling, it isn't safe to unpin a context while scheduling
is enabled for that context as the GuC may touch some of the pinned
state (e.g. LRC). To ensure scheduling isn't enabled when an unpin is
done, a call back is added to intel_context_unp
On 6/24/2021 00:04, Matthew Brost wrote:
Sometime during context pinning a context with the same guc_id is
Sometime*s*
registered with the GuC. In this a case deregister must be before before
before before -> done before
the context can be registered. A fence is inserted on all requests whi
On Fri, Jul 09, 2021 at 11:36:09AM -0700, Anusha Srivatsa wrote:
-Original Message-
From: De Marchi, Lucas
Sent: Friday, July 9, 2021 10:53 AM
To: Roper, Matthew D
Cc: Srivatsa, Anusha ; intel-
g...@lists.freedesktop.org; Jani Nikula
Subject: Re: [Intel-gfx] [PATCH 09/10] drm/i915/s
== Series Details ==
Series: iommu/vt-d: Disable igfx iommu superpage on bxt/skl/glk
URL : https://patchwork.freedesktop.org/series/92374/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10326 -> Patchwork_20566
Summary
-
> -Original Message-
> From: De Marchi, Lucas
> Sent: Friday, July 9, 2021 10:53 AM
> To: Roper, Matthew D
> Cc: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org; Jani Nikula
> Subject: Re: [Intel-gfx] [PATCH 09/10] drm/i915/step: Add intel_step_name()
> helper
>
> On Thu, Jul
On Wed, Jul 07, 2021 at 03:22:07PM -0700, Matt Roper wrote:
DG2 has some changes to the expected modesetting sequences when compared
to gen12. Adjust our driver logic accordingly. Although the DP
sequence is pretty similar to TGL's, there are some steps that change,
so let's split the handling
== Series Details ==
Series: iommu/vt-d: Disable igfx iommu superpage on bxt/skl/glk
URL : https://patchwork.freedesktop.org/series/92374/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7da685194fc4 iommu/vt-d: Disable superpage for Geminilake igfx
-:18: WARNING:COMMIT_LOG_LONG_
== Series Details ==
Series: drm/vgem: Restore mmap functionality
URL : https://patchwork.freedesktop.org/series/92373/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10326 -> Patchwork_20565
Summary
---
**FAILURE**
On Thu, Jul 08, 2021 at 09:16:16PM -0700, Matt Roper wrote:
On Thu, Jul 08, 2021 at 04:18:20PM -0700, Anusha Srivatsa wrote:
Add a helper to convert the step info to string.
This is specifically useful when we want to load a specific
firmware for a given stepping/substepping combination.
What
== Series Details ==
Series: drm/i915/ehl: unconditionally flush the pages on acquire (rev2)
URL : https://patchwork.freedesktop.org/series/92367/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10326 -> Patchwork_20564
Summa
On Wed, Jul 07, 2021 at 04:59:21PM -0700, Lucas De Marchi wrote:
> Besides the arch version returned by GRAPHICS_VER(), new platforms
> contain a "release id" to make clear the difference from one platform to
> another.
>
> The release id number is not formally defined by hardware until future
> p
On Wed, Jul 07, 2021 at 04:59:20PM -0700, Lucas De Marchi wrote:
> Brevity is not needed here, so just spell out "* version" in the string.
>
> Suggested-by: Chris Wilson
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 6 +++---
> 1
== Series Details ==
Series: drm/i915/ehl: unconditionally flush the pages on acquire (rev2)
URL : https://patchwork.freedesktop.org/series/92367/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
898f9d8b7d24 drm/i915/ehl: unconditionally flush the pages on acquire
-:20: WARNING:C
On Fri, Jul 9, 2021 at 6:35 PM Matthew Auld
wrote:
>
> On Fri, 9 Jul 2021 at 17:13, Daniel Vetter wrote:
> >
> > On Fri, Jul 9, 2021 at 5:19 PM Matthew Auld wrote:
> > >
> > > EHL and JSL add the 'Bypass LLC' MOCS entry, which should make it
> > > possible for userspace to bypass the GTT caching
From: Ville Syrjälä
With the iommu driver disabling VT-d superpage it should be
safe to use FBC on SKL/BXT with VT-d otherwise enabled.
Cc: David Woodhouse
Cc: Lu Baolu
Cc: io...@lists.linux-foundation.org
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 16 ---
From: Ville Syrjälä
Broxton has known issues with VT-d superpage. Namely frame buffer
compression (FBC) can't be safely used when superpage is enabled.
Currently we're disabling FBC entirely when VT-d is active, but
I think just disabling superpage would be better since FBC can
save some power.
From: Ville Syrjälä
Skylake has known issues with VT-d superpage. Namely frame buffer
compression (FBC) can't be safely used when superpage is enabled.
Currently we're disabling FBC entirely when VT-d is active, but
I think just disabling superpage would be better since FBC can
save some power.
From: Ville Syrjälä
While running "gem_exec_big --r single" from igt-gpu-tools on
Geminilake as soon as a 2M mapping is made I tend to get a DMAR
write fault. Strangely the faulting address is always a 4K page
and usually very far away from the 2M page that got mapped.
But if no 2M mappings get u
From: Ville Syrjälä
I ran into some kind of fail with VT-d superpage on Geminlake igfx,
so without any better ideas let's just disable it.
Additionally Skylake/Broxton igfx have known issues with VT-d
superpage as well, so let's disable it there as well. This should
let us re-enable frame buffer
On Fri, 9 Jul 2021 at 17:13, Daniel Vetter wrote:
>
> On Fri, Jul 9, 2021 at 5:19 PM Matthew Auld wrote:
> >
> > EHL and JSL add the 'Bypass LLC' MOCS entry, which should make it
> > possible for userspace to bypass the GTT caching bits set by the kernel,
> > as per the given object cache_level.
On Fri, Jul 9, 2021 at 5:19 PM Matthew Auld wrote:
>
> EHL and JSL add the 'Bypass LLC' MOCS entry, which should make it
> possible for userspace to bypass the GTT caching bits set by the kernel,
> as per the given object cache_level. This is troublesome since the heavy
> flush we apply when first
Commit 375cca1cfeb5 ("drm/vgem: Implement mmap as GEM object function")
accidentally removed the actual mmap functionality from vgem. Restore
the original implementation and VMA flags.
Fixes access to unmapped memory:
[ 106.591744] BUG: KASAN: vmalloc-out-of-bounds in do_fault+0x38/0x480
[ 106.
EHL and JSL add the 'Bypass LLC' MOCS entry, which should make it
possible for userspace to bypass the GTT caching bits set by the kernel,
as per the given object cache_level. This is troublesome since the heavy
flush we apply when first acquiring the pages is skipped if the kernel
thinks the objec
== Series Details ==
Series: drm/sched dependency tracking and dma-resv fixes (rev2)
URL : https://patchwork.freedesktop.org/series/92333/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10320_full -> Patchwork_20559_full
Sum
On Fri, Jul 9, 2021 at 2:12 PM Anshuman Gupta wrote:
>
> Extend i915_lpsp_capability sysfs to xelpd and future platforms.
You're talking about sysfs but the patch is toucing a _debugfs.c file.
Something is very, very wrong here, either the commit message, or
worse, the code that's there already.
EHL and JSL add the 'Bypass LLC' MOCS entry, which should make it
possible for userspace to bypass the GTT caching bits set by the kernel,
as per the given object cache_level. This is troublesome since the heavy
flush we apply when first acquiring the pages is skipped if the kernel
thinks the objec
On Fri, Jul 9, 2021 at 1:41 PM Maarten Lankhorst
wrote:
>
> This is only used for ttm, and tells userspace that the mapping type is
> ignored. This disables the other type of mmap offsets when discrete
> memory is used, so fix the selftests as well.
>
> Document the struct as well, so it shows up
== Series Details ==
Series: series starting with [1/7] drm/i915: Settle on "adl-x" in WA comments
URL : https://patchwork.freedesktop.org/series/92342/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10320_full -> Patchwork_20558_full
===
On Thu, Jul 1, 2021 at 6:42 AM Maarten Lankhorst
wrote:
>
> This is only used for ttm, and tells userspace that the mapping type is
> ignored. This disables the other type of mmap offsets when discrete
> memory is used, so fix the selftests as well.
>
> Signed-off-by: Maarten Lankhorst
> ---
> d
== Series Details ==
Series: drm/i915/debugfs: xelpd lpsp capability
URL : https://patchwork.freedesktop.org/series/92364/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10324 -> Patchwork_20563
Summary
---
**SUCCESS*
== Series Details ==
Series: drm/i915/dg1: Compute MEM Bandwidth using MCHBAR (rev2)
URL : https://patchwork.freedesktop.org/series/92094/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10320_full -> Patchwork_20557_full
Sum
== Series Details ==
Series: drm/i915: Add TTM offset argument to mmap. (rev2)
URL : https://patchwork.freedesktop.org/series/92103/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10324 -> Patchwork_20562
Summary
---
Op 09-07-2021 om 11:30 schreef Matthew Auld:
> On Mon, 5 Jul 2021 at 15:36, Matthew Auld
> wrote:
>> On Thu, 1 Jul 2021 at 12:50, Maarten Lankhorst
>> wrote:
>>> Op 01-07-2021 om 13:42 schreef Maarten Lankhorst:
This is only used for ttm, and tells userspace that the mapping type is
ign
== Series Details ==
Series: drm/i915: Add TTM offset argument to mmap. (rev2)
URL : https://patchwork.freedesktop.org/series/92103/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
53107c2bf2c8 drm/i915: Add TTM offset argument to mmap.
-:66: WARNING:PREFER_FALLTHROUGH: Prefer 'f
== Series Details ==
Series: CT changes required for GuC submission
URL : https://patchwork.freedesktop.org/series/92330/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10320_full -> Patchwork_20556_full
Summary
---
*
Extend i915_lpsp_capability sysfs to xelpd and future platforms.
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/
Am 09.07.21 um 10:00 schrieb Daniel Vetter:
On Fri, Jul 9, 2021 at 9:23 AM Christian König wrote:
Am 09.07.21 um 09:14 schrieb Daniel Vetter:
On Fri, Jul 9, 2021 at 8:53 AM Christian König wrote:
Am 08.07.21 um 19:37 schrieb Daniel Vetter:
If it does, someone managed to set up a sched_entit
== Series Details ==
Series: drm/i915: Add missing docbook chapters for i915 uapi.
URL : https://patchwork.freedesktop.org/series/92359/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10324 -> Patchwork_20561
Summary
---
== Series Details ==
Series: Set BPP in the kernel (rev2)
URL : https://patchwork.freedesktop.org/series/92312/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10320_full -> Patchwork_20554_full
Summary
---
**FAILURE**
This is only used for ttm, and tells userspace that the mapping type is
ignored. This disables the other type of mmap offsets when discrete
memory is used, so fix the selftests as well.
Document the struct as well, so it shows up in docbook correctly.
Changes since v1:
- Add docbook entries.
Sig
I noticed when grepping for DOC: that those were defined
in the header, but not actually used. Fix it.
Signed-off-by: Maarten Lankhorst
---
Documentation/gpu/driver-uapi.rst | 12
1 file changed, 12 insertions(+)
diff --git a/Documentation/gpu/driver-uapi.rst
b/Documentation/gpu/d
Am 09.07.21 um 09:14 schrieb Daniel Vetter:
On Fri, Jul 9, 2021 at 8:53 AM Christian König wrote:
Am 08.07.21 um 19:37 schrieb Daniel Vetter:
If it does, someone managed to set up a sched_entity without
schedulers, which is just a driver bug.
NAK, it is perfectly valid for rq selection to fai
Am 08.07.21 um 23:54 schrieb Daniel Vetter:
It might be good enough on x86 with just READ_ONCE, but the write side
should then at least be WRITE_ONCE because x86 has total store order.
It's definitely not enough on arm.
Fix this proplery, which means
- explain the need for the barrier in both
Am 08.07.21 um 19:37 schrieb Daniel Vetter:
If it does, someone managed to set up a sched_entity without
schedulers, which is just a driver bug.
NAK, it is perfectly valid for rq selection to fail.
See drm_sched_pick_best():
if (!sched->ready) {
DRM_WAR
On Mon, 5 Jul 2021 at 15:36, Matthew Auld
wrote:
>
> On Thu, 1 Jul 2021 at 12:50, Maarten Lankhorst
> wrote:
> >
> > Op 01-07-2021 om 13:42 schreef Maarten Lankhorst:
> > > This is only used for ttm, and tells userspace that the mapping type is
> > > ignored. This disables the other type of mmap
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