On Mon, Jul 05, 2021 at 08:03:52PM +0100, Will Deacon wrote:
> So at this point, the AMD IOMMU driver does:
>
> swiotlb= (iommu_default_passthrough() || sme_me_mask) ? 1 : 0;
>
> where 'swiotlb' is a global variable indicating whether or not swiotlb
> is in use. It's picked up a bit
The customer service informed me that the Intel XE graphics card supports
SR-IOV, which is used to replace the removed GVT. But the SR-IOV driver of
Intel XE graphics card does not appear in the Linux kernel. Is there any
plan to write the SR-IOV driver?
On Mon, 05 Jul 2021, venkata.sai.patn...@intel.com wrote:
> From: Anusha Srivatsa
>
> Set compress BPP in kernel while connector DP or eDP
>
> Cc: Vandita Kulkarni
> Cc: Navare Manasi D
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Patnana Venkata Sai
> ---
> drivers/gpu/drm/i915/display/
On Mon, 05 Jul 2021, venkata.sai.patn...@intel.com wrote:
> From: Patnana Venkata Sai
>
> [What]:
> This patch creates a per connector debugfs node to expose
> the Input and Compressed BPP.
>
> The same node can be used from userspace to force
> DSC to a certain BPP(all accepted values).
>
> [Why]
Am 01.07.21 um 15:24 schrieb Pekka Paalanen:
> On Thu, 1 Jul 2021 14:50:13 +0200
> Werner Sembach wrote:
>
>> Am 01.07.21 um 10:07 schrieb Pekka Paalanen:
>>
>>> On Wed, 30 Jun 2021 11:20:18 +0200
>>> Werner Sembach wrote:
>>>
Am 30.06.21 um 10:41 schrieb Pekka Paalanen:
> On
== Series Details ==
Series: series starting with [v3,1/5] drm/i915: use consistent CPU mappings for
pin_map users
URL : https://patchwork.freedesktop.org/series/92209/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10305 -> Patchwork_20531
== Series Details ==
Series: series starting with [v3,1/5] drm/i915: use consistent CPU mappings for
pin_map users
URL : https://patchwork.freedesktop.org/series/92209/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a003ccd3dd56 drm/i915: use consistent CPU mappings for pin_map
On 05/07/2021 15:25, Daniel Vetter wrote:
On Mon, Jul 05, 2021 at 09:34:22AM +0100, Tvrtko Ursulin wrote:
On 02/07/2021 20:22, Daniel Vetter wrote:
On Fri, Jul 02, 2021 at 03:31:08PM +0100, Tvrtko Ursulin wrote:
On 01/07/2021 16:10, Matthew Auld wrote:
The CPU domain should be static for d
On Thu, 1 Jul 2021 at 12:50, Maarten Lankhorst
wrote:
>
> Op 01-07-2021 om 13:42 schreef Maarten Lankhorst:
> > This is only used for ttm, and tells userspace that the mapping type is
> > ignored. This disables the other type of mmap offsets when discrete
> > memory is used, so fix the selftests a
On Mon, Jul 05, 2021 at 10:15:45AM +0800, Desmond Cheong Zhi Xi wrote:
> On 3/7/21 3:07 am, Daniel Vetter wrote:
> > On Fri, Jul 02, 2021 at 12:53:53AM +0800, Desmond Cheong Zhi Xi wrote:
> > > This patch series addresses potential use-after-free errors when
> > > dereferencing pointers to struct
On Mon, Jul 05, 2021 at 09:34:22AM +0100, Tvrtko Ursulin wrote:
> On 02/07/2021 20:22, Daniel Vetter wrote:
> > On Fri, Jul 02, 2021 at 03:31:08PM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 01/07/2021 16:10, Matthew Auld wrote:
> > > > The CPU domain should be static for discrete, and on DG1 we d
The CPU domain should be static for discrete, and on DG1 we don't need
any flushing since everything is already coherent, so really all this
does is an object wait, for which we have an ioctl. Longer term the
desired caching should be an immutable creation time property for the
BO, which can be set
Convert all the drm_i915_gem_set_domain bits to proper kernel doc.
Suggested-by: Daniel Vetter
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Maarten Lankhorst
Cc: Tvrtko Ursulin
Cc: Jordan Justen
Cc: Kenneth Graunke
Cc: Jason Ekstrand
Cc: Daniel Vetter
Cc: Ramalingam C
---
includ
It's a noop on DG1, and in the future when need to support other devices
which let us control the coherency, then it should be an immutable
creation time property for the BO. This will likely be controlled
through a new gem_create_ext extension.
v2: add some kernel doc for the discrete changes, an
Convert all the drm_i915_gem_caching bits to proper kernel doc.
Suggested-by: Daniel Vetter
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Maarten Lankhorst
Cc: Tvrtko Ursulin
Cc: Jordan Justen
Cc: Kenneth Graunke
Cc: Jason Ekstrand
Cc: Daniel Vetter
Cc: Ramalingam C
---
include/u
For discrete, users of pin_map() needs to obey the same rules at the TTM
backend, where we map system only objects as WB, and everything else as
WC. The simplest for now is to just force the correct mapping type as
per the new rules for discrete.
Suggested-by: Thomas Hellström
Signed-off-by: Matt
== Series Details ==
Series: drm/i915/hdcp: Dsiplay13 HDCP support over MST (rev2)
URL : https://patchwork.freedesktop.org/series/92202/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10305 -> Patchwork_20530
Summary
---
== Series Details ==
Series: drm/i915/hdcp: Dsiplay13 HDCP support over MST
URL : https://patchwork.freedesktop.org/series/92202/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10305 -> Patchwork_20529
Summary
---
**F
Earlier HDCP over MST support was added for TGL Platform.
Extending it to all future platfroms.
v2:
- Remove the platform check and commit log changes. [Jani]
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 ---
1 file changed, 4 insertions(+), 7 delet
== Series Details ==
Series: drm/i915/display/dsc: Set BPP in the kernel (rev7)
URL : https://patchwork.freedesktop.org/series/91917/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10305 -> Patchwork_20528
Summary
---
== Series Details ==
Series: drm/i915/display/dsc: Set BPP in the kernel (rev7)
URL : https://patchwork.freedesktop.org/series/91917/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/
On Mon, 05 Jul 2021, Anshuman Gupta wrote:
> Adding HDCP support over DP MST for Display13 Platforms.
Why do we have the condition at all? Usually we assume it'll work, and
we disable or change later when a platform shows up where it doesn't
work.
BR,
Jani.
>
> Signed-off-by: Anshuman Gupta
>
On Fri, 02 Jul 2021, Tvrtko Ursulin wrote:
> On 01/07/2021 21:23, Matt Roper wrote:
>> From: Lucas De Marchi
>>
>> Besides the arch version returned by GRAPHICS_VER(), new platforms
>> contain a "release id" to make clear the difference from one platform to
>> another. Although for the first one
Adding HDCP support over DP MST for Display13 Platforms.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
in
Quoting Daniel Vetter (2021-07-02 23:17:08)
> We're not consistently recommending these for developers only.
>
> I stumbled over this due to DRM_I915_LOW_LEVEL_TRACEPOINTS, which was
> added in
>
> commit 354d036fcf70654cff2e2cbdda54a835d219b9d2
> Author: Tvrtko Ursulin
> Date: Tue Feb 21 11:0
== Series Details ==
Series: drm/i915/display/dsc: Set BPP in the kernel (rev6)
URL : https://patchwork.freedesktop.org/series/91917/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10305 -> Patchwork_20527
Summary
---
On Tue, 29 Jun 2021, "Souza, Jose" wrote:
> On Mon, 2021-06-28 at 16:50 -0700, Madhumitha Tolakanahalli Pradeep wrote:
>> PCH display HPD IRQ is not detected with default filter value.
>> So, PP_CONTROL is manually reprogrammed.
>>
>> Signed-off-by: Madhumitha Tolakanahalli Pradeep
>>
>> ---
>>
== Series Details ==
Series: drm/i915/display/dsc: Set BPP in the kernel (rev6)
URL : https://patchwork.freedesktop.org/series/91917/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/
On Thu, 01 Jul 2021, Anusha Srivatsa wrote:
> intel_step.c has stepping_info for most platforms. With DMC using
> display_step from here, lets add the info for all older platforms
> as well
Same here as previous patch. These should be added one platform per
patch, converting the IS_FOO_REVID() m
On Thu, 01 Jul 2021, Anusha Srivatsa wrote:
> On the dmc side,we maintain a lookup table with different display
> stepping-substepping combinations.
>
> Instead of adding new table for every new platform, lets ues
> the stepping info from RUNTIME_INFO(dev_priv)->step
>
> v2: Add stepping table for
From: Anusha Srivatsa
Set compress BPP in kernel while connector DP or eDP
Cc: Vandita Kulkarni
Cc: Navare Manasi D
Signed-off-by: Anusha Srivatsa
Signed-off-by: Patnana Venkata Sai
---
drivers/gpu/drm/i915/display/intel_dp.c | 27 ++---
1 file changed, 20 insertions(+),
From: Patnana Venkata Sai
[What]:
This patch creates a per connector debugfs node to expose
the Input and Compressed BPP.
The same node can be used from userspace to force
DSC to a certain BPP(all accepted values).
[Why]:
Useful to verify all supported/requested compression bpp's
through IGT
v
From: Patnana Venkata Sai
DSC can be supported per DP connector. This patch creates
a per connector debugfs node to expose the Input and
Compressed BPP.
The same node can be used from userspace to force
DSC to a certain BPP.
force_dsc_bpp is written through this debugfs
node to force DSC BPP to
On 02/07/2021 20:22, Daniel Vetter wrote:
On Fri, Jul 02, 2021 at 03:31:08PM +0100, Tvrtko Ursulin wrote:
On 01/07/2021 16:10, Matthew Auld wrote:
The CPU domain should be static for discrete, and on DG1 we don't need
any flushing since everything is already coherent, so really all this
Kno
On Fri, 02 Jul 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Polish the FBC stride override stuff:
> - just call it override_cfb_stride since it'll be used on
> more gens later
> - Use REG_BIT() & co. for the registers and give everything
> CHICKEN_ prefix since glk+ will have a differ
== Series Details ==
Series: Restricted DMA (rev3)
URL : https://patchwork.freedesktop.org/series/91883/
State : failure
== Summary ==
Applying: swiotlb: Refactor swiotlb init functions
Applying: swiotlb: Refactor swiotlb_create_debugfs
Applying: swiotlb: Set dev->dma_io_tlb_mem to the swiotlb
On Sat, 03 Jul 2021, Lucas De Marchi wrote:
> On Fri, Jul 02, 2021 at 10:49:05AM +0300, Jani Nikula wrote:
>>Frankly, I think all of this should be incorporated to intel_step.[ch]
>>instead of having a semi-overlapping handling here. Just look at the
>>amount of duplication already.
>
> I guess yo
On Sat, Jul 3, 2021 at 1:55 PM Nathan Chancellor wrote:
>
> Hi Will and Robin,
>
> On Fri, Jul 02, 2021 at 04:13:50PM +0100, Robin Murphy wrote:
> > On 2021-07-02 14:58, Will Deacon wrote:
> > > Hi Nathan,
> > >
> > > On Thu, Jul 01, 2021 at 12:52:20AM -0700, Nathan Chancellor wrote:
> > > > On 7/
== Series Details ==
Series: drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP enable
URL : https://patchwork.freedesktop.org/series/92188/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10304 -> Patchwork_20525
===
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