On Fri, 02 Jul 2021, Ville Syrjala <ville.syrj...@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> Polish the FBC stride override stuff:
> - just call it override_cfb_stride since it'll be used on
> more gens later
> - Use REG_BIT() & co. for the registers and give everything
> CHICKEN_ prefix since glk+ will have a different register
> for this
> - Use intel_de_rmw() for the RMW
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nik...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 27 ++++++++++++------------
> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 5 +++--
> 3 files changed, 19 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index c9cde96f330b..f5cbbc53837c 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -306,14 +306,15 @@ static void gen7_fbc_activate(struct drm_i915_private
> *dev_priv)
>
> /* Display WA #0529: skl, kbl, bxt. */
> if (DISPLAY_VER(dev_priv) == 9) {
> - u32 val = intel_de_read(dev_priv, CHICKEN_MISC_4);
> + u32 val = 0;
>
> - val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
> + if (params->override_cfb_stride)
> + val |= CHICKEN_FBC_STRIDE_OVERRIDE |
> + CHICKEN_FBC_STRIDE(params->override_cfb_stride);
>
> - if (params->gen9_wa_cfb_stride)
> - val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
> -
> - intel_de_write(dev_priv, CHICKEN_MISC_4, val);
> + intel_de_rmw(dev_priv, CHICKEN_MISC_4,
> + CHICKEN_FBC_STRIDE_OVERRIDE |
> + CHICKEN_FBC_STRIDE_MASK, val);
> }
>
> dpfc_ctl = 0;
> @@ -749,7 +750,7 @@ static bool intel_fbc_cfb_size_changed(struct
> drm_i915_private *dev_priv)
> fbc->compressed_fb.size * fbc->limit;
> }
>
> -static u16 intel_fbc_gen9_wa_cfb_stride(struct drm_i915_private *dev_priv)
> +static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *dev_priv)
> {
> struct intel_fbc *fbc = &dev_priv->fbc;
> struct intel_fbc_state_cache *cache = &fbc->state_cache;
> @@ -761,11 +762,11 @@ static u16 intel_fbc_gen9_wa_cfb_stride(struct
> drm_i915_private *dev_priv)
> return 0;
> }
>
> -static bool intel_fbc_gen9_wa_cfb_stride_changed(struct drm_i915_private
> *dev_priv)
> +static bool intel_fbc_override_cfb_stride_changed(struct drm_i915_private
> *dev_priv)
> {
> struct intel_fbc *fbc = &dev_priv->fbc;
>
> - return fbc->params.gen9_wa_cfb_stride !=
> intel_fbc_gen9_wa_cfb_stride(dev_priv);
> + return fbc->params.override_cfb_stride !=
> intel_fbc_override_cfb_stride(dev_priv);
> }
>
> static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
> @@ -950,7 +951,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc
> *crtc,
>
> params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
>
> - params->gen9_wa_cfb_stride = cache->gen9_wa_cfb_stride;
> + params->override_cfb_stride = cache->override_cfb_stride;
>
> params->plane_visible = cache->plane.visible;
> }
> @@ -984,7 +985,7 @@ static bool intel_fbc_can_flip_nuke(const struct
> intel_crtc_state *crtc_state)
> if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache))
> return false;
>
> - if (params->gen9_wa_cfb_stride != cache->gen9_wa_cfb_stride)
> + if (params->override_cfb_stride != cache->override_cfb_stride)
> return false;
>
> return true;
> @@ -1266,7 +1267,7 @@ static void intel_fbc_enable(struct intel_atomic_state
> *state,
> if (fbc->crtc) {
> if (fbc->crtc != crtc ||
> (!intel_fbc_cfb_size_changed(dev_priv) &&
> - !intel_fbc_gen9_wa_cfb_stride_changed(dev_priv)))
> + !intel_fbc_override_cfb_stride_changed(dev_priv)))
> goto out;
>
> __intel_fbc_disable(dev_priv);
> @@ -1288,7 +1289,7 @@ static void intel_fbc_enable(struct intel_atomic_state
> *state,
> goto out;
> }
>
> - cache->gen9_wa_cfb_stride = intel_fbc_gen9_wa_cfb_stride(dev_priv);
> + cache->override_cfb_stride = intel_fbc_override_cfb_stride(dev_priv);
>
> drm_dbg_kms(&dev_priv->drm, "Enabling FBC on pipe %c\n",
> pipe_name(crtc->pipe));
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6dff4ca01241..91a2d2425fd3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -401,7 +401,7 @@ struct intel_fbc {
> } fb;
>
> unsigned int fence_y_offset;
> - u16 gen9_wa_cfb_stride;
> + u16 override_cfb_stride;
> u16 interval;
> s8 fence_id;
> bool psr2_active;
> @@ -428,7 +428,7 @@ struct intel_fbc {
>
> int cfb_size;
> unsigned int fence_y_offset;
> - u16 gen9_wa_cfb_stride;
> + u16 override_cfb_stride;
> u16 interval;
> s8 fence_id;
> bool plane_visible;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 16a19239d86d..ab2bd4837efd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8131,8 +8131,9 @@ enum {
> #define GLK_CL0_PWR_DOWN (1 << 10)
>
> #define CHICKEN_MISC_4 _MMIO(0x4208c)
> -#define FBC_STRIDE_OVERRIDE (1 << 13)
> -#define FBC_STRIDE_MASK 0x1FFF
> +#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
> +#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
> +#define CHICKEN_FBC_STRIDE(x)
> REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
>
> #define _CHICKEN_PIPESL_1_A 0x420b0
> #define _CHICKEN_PIPESL_1_B 0x420b4
--
Jani Nikula, Intel Open Source Graphics Center
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