On Thu, 24 Jun 2021 at 02:20, Daniel Vetter wrote:
>
> Docs for struct dma_resv are fairly clear:
>
> "A reservation object can have attached one exclusive fence (normally
> associated with write operations) or N shared fences (read
> operations)."
>
> https://dri.freedesktop.org/docs/drm/driver-a
On 24/06/21 05:57, David Stevens wrote:
KVM supports mapping VM_IO and VM_PFNMAP memory into the guest by using
follow_pte in gfn_to_pfn. However, the resolved pfns may not have
assoicated struct pages, so they should not be passed to pfn_to_page.
This series removes such calls from the x86 and a
The new GuC interface introduces an MMIO H2G command,
INTEL_GUC_ACTION_RESET_CLIENT, which is used to implement suspend. This
MMIO tears down any active contexts generating a context reset G2H CTB
for each. Once that step completes the GuC tears down the CTB
channels. It is safe to suspend once thi
Update the bonding extension to return -ENODEV when using GuC submission
as this extension fundamentally will not work with the GuC submission
interface.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/
From: John Harrison
The serial number tracking of engines happens at the backend of
request submission and was expecting to only be given physical
engines. However, in GuC submission mode, the decomposition of virtual
to physical engines does not happen in i915. Instead, requests are
submitted to
Add intel_context tracing. These trace points are particular helpful
when debugging the GuC firmware and can be enabled via
CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS kernel config option.
Cc: John Harrison
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.c | 6 +
.../g
If submission is disabled by the backend for any reason, reset the GPU
immediately in the heartbeat code as the backend can't be reenabled
until the GPU is reset.
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 63 +++
.../gpu/drm/i915/gt/intel_en
The GuC can implement execution qunatums, detect hung contexts and
other such things but it requires the timer expired interrupt to do so.
Signed-off-by: Matthew Brost
CC: John Harrison
---
drivers/gpu/drm/i915/gt/intel_rps.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/d
From: John Harrison
Added the scheduling policy parameters to the 'guc_info' debugfs state
dump.
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 13 +
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h | 2 ++
drivers/gpu
From: John Harrison
Clear the 'disable resets' flag to allow GuC to reset hung contexts
(detected via pre-emption timeout).
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --
From: John Harrison
The driver must provide GuC with a list of mmio registers
that should be saved/restored during a GuC-based engine reset.
Unfortunately, the list must be dynamically allocated as its size is
variable. That means the driver must generate the list twice - once to
work out the siz
From: John Harrison
In the case of a full GPU reset (e.g. because GuC has died or because
GuC's hang detection has been disabled), the driver can't rely on GuC
reporting the guilty context. Instead, the driver needs to scan all
active contexts and find one that is currently executing, as per the
From: Daniele Ceraolo Spurio
Unblock GuC submission on Gen11+ platforms.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +++
GuC will issue a reset on detecting an engine hang and will notify
the driver via a G2H message. The driver will service the notification
by resetting the guilty context to a simple state or banning it
completely.
Cc: Matthew Brost
Cc: John Harrison
Signed-off-by: Matthew Brost
---
drivers/gpu
Semaphores are an optimization and not required for basic GuC submission
to work properly. Disable until we have time to do the implementation to
enable semaphores and tune them for performance. Also long direction is
just to delete semaphores from the i915 so another reason to not enable
these for
Add disable GuC interrupts to intel_guc_sanitize(). Part of this
requires moving the guc_*_interrupt wrapper function into header file
intel_guc.h.
Signed-off-by: Matthew Brost
Cc: Daniele Ceraolo Spurio ct);
}
+static inline void intel_guc_reset_interrupts(struct intel_guc *guc)
+{
+ gu
We receive notification of an engine reset from GuC at its
completion. Meaning GuC has potentially cleared any HW state
we may have been interested in capturing. GuC resumes scheduling
on the engine post-reset, as the resets are meant to be transparent,
further muddling our error state.
There is o
Hold a reference to the intel_context over life of an i915_request.
Without this an i915_request can exist after the context has been
destroyed (e.g. request retired, context closed, but user space holds a
reference to the request from an out fence). In the case of GuC
submission + virtual engine,
Disable preempt busywait when using GuC scheduling. This isn't need as
the GuC control preemption when scheduling.
Cc: John Harrison
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/dr
From: John Harrison
The media watchdog mechanism involves GuC doing a silent reset and
continue of the hung context. This requires the i915 driver provide a
golden context to GuC in the ADS.
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_gt.c
If two requests are on the same ring, they are explicitly ordered by the
HW. So, a submission fence is sufficient to ensure ordering when using
the new GuC submission interface. Conversely, if two requests share a
timeline and are on the same physical engine but different context this
doesn't ensur
From: John Harrison
It is impossible to seal all race conditions of resets occurring
concurrent to other operations. At least, not without introducing
excesive mutex locking. Instead, don't complain if it occurs. In
particular, don't complain if trying to send a H2G during a reset.
Whatever the H
Disable engine barriers for unpinning with GuC. This feature isn't
needed with the GuC as it disables context scheduling before unpinning
which guarantees the HW will not reference the context. Hence it is
not necessary to defer unpinning until a kernel context request
completes on each engine in t
With GuC virtual engines the physical engine which a request executes
and completes on isn't known to the i915. Therefore we can't attach a
request to a physical engines breadcrumbs. To work around this we create
a single breadcrumbs per engine class when using GuC submission and
direct all physica
With the introduction of non-blocking CTBs more than one CTB can be in
flight at a time. Increasing the size of the CTBs should reduce how
often software hits the case where no space is available in the CTB
buffer.
Cc: John Harrison
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/in
With GuC scheduling, it isn't safe to unpin a context while scheduling
is enabled for that context as the GuC may touch some of the pinned
state (e.g. LRC). To ensure scheduling isn't enabled when an unpin is
done, a call back is added to intel_context_unpin when pin count == 1
to disable schedulin
Remove old GuC stage descriptor, add lrc descriptor which will be used
by the new GuC interface implemented in this patch series.
Cc: John Harrison
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 4 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 65
Implement GuC context operations which includes GuC specific operations
alloc, pin, unpin, and destroy.
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.c | 5 +
drivers/gpu/drm/i915/gt/intel_context_types.h | 22 +-
drivers/gpu/drm/i9
Reset implementation for new GuC interface. This is the legacy reset
implementation which is called when the i915 owns the engine hang check.
Future patches will offload the engine hang check to GuC but we will
continue to maintain this legacy path as a fallback and this code path
is also required
Update GuC debugfs to support the new GuC structures.
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 22
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 3 ++
.../gpu/drm/i915/gt/uc/intel_guc_debugfs.c| 23 +++-
..
From: John Harrison
Changing the reset module parameter has no effect on a running GuC.
The corresponding entry in the ADS must be updated and then the GuC
informed via a Host2GuC message.
The new debugfs interface to module parameters allows this to happen.
However, connecting the parameter dat
Implement GuC virtual engines. Rather simple implementation, basically
just allocate an engine, setup context enter / exit function to virtual
engine specific functions, set all other variables / functions to guc
versions, and set the engine mask to that of all the siblings.
Cc: Daniele Ceraolo Sp
CTB writes are now in the path of command submission and should be
optimized for performance. Rather than reading CTB descriptor values
(e.g. head, tail) which could result in accesses across the PCIe bus,
store shadow local copies and only read/write the descriptor values when
absolutely necessary
GuC will notify the driver, via G2H, if it fails to
reset an engine. We recover by resorting to a full GPU
reset.
Signed-off-by: Matthew Brost
Signed-off-by: Fernando Pacheco
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 +
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 3 ++
.../gpu
From: John Harrison
Use the official driver default scheduling policies for configuring
the GuC scheduler rather than a bunch of hardcoded values.
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Cc: Jose Souza
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/dr
From: John Harrison
Add several module failure load inject points in the CT buffer creation
code path.
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 8
1 file changed, 8 insertions(+)
diff --g
Ensure G2H response has space in the buffer before sending H2G CTB as
the GuC can't handle any backpressure on the G2H interface.
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 13 +++-
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
Extend the deregistration context fence to fence whne a GuC context has
scheduling disable pending.
Cc: John Harrison
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++
1 file changed, 30 insertions(+), 7 deletions(-)
diff --git a/drivers/g
Add non blocking CTB send function, intel_guc_send_nb. GuC submission
will send CTBs in the critical path and does not need to wait for these
CTBs to complete before moving on, hence the need for this new function.
The non-blocking CTB now must have a flow control mechanism to ensure
the buffer is
When running the GuC the GPU can't be considered idle if the GuC still
has contexts pinned. As such, a call has been added in
intel_gt_wait_for_idle to idle the UC and in turn the GuC by waiting for
the number of unpinned contexts to go to zero.
v2: rtimeout -> remaining_timeout
Cc: John Harrison
Add lrc descriptor context lookup array which can resolve the
intel_context from the lrc descriptor index. In addition to lookup, it
can determine in the lrc descriptor context is currently registered with
the GuC by checking if an entry for a descriptor index is present.
Future patches in the seri
Add new GuC interface defines and structures while maintaining old ones
in parallel.
Cc: John Harrison
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 14 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 41 +++
2 files changed, 55 inserti
Implement a stall timer which fails H2G CTBs once a period of time
with no forward progress is reached to prevent deadlock.
Also update to ct_write to return -EIO rather than -EPIPE on a
corrupted descriptor.
Signed-off-by: John Harrison
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt
As discussed in [1], [2] we are enabling GuC submission support in the
i915. This is a subset of the patches in step 5 described in [1],
basically it is absolute to enable CI with GuC submission on gen11+
platforms.
This series itself will likely be broken down into smaller patch sets to
merge. Li
Add bypass tasklet submission path to GuC. The tasklet is only used if H2G
channel has backpresure.
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++
1 file changed, 29 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/i
In upcoming patch we will allow more CTB requests to be sent in
parallel to the GuC for processing, so we shouldn't assume any more
that GuC will always reply without 10ms.
Use bigger value hardcoded value of 1s instead.
v2: Add CONFIG_DRM_I915_GUC_CTB_TIMEOUT config option
v3:
(Daniel Vetter)
Sometime during context pinning a context with the same guc_id is
registered with the GuC. In this a case deregister must be before before
the context can be registered. A fence is inserted on all requests while
the deregister is in flight. Once the G2H is received indicating the
deregistration is
Add trace points for request dependencies and GuC submit. Extended
existing request trace points to include submit fence value,, guc_id,
and ring tail value.
Cc: John Harrison
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 ++
drivers/gpu/drm/i915/i915_reque
Implement GuC submission tasklet for new interface. The new GuC
interface uses H2G to submit contexts to the GuC. Since H2G use a single
channel, a single tasklet submits is used for the submission path.
Also the per engine interrupt handler has been updated to disable the
rescheduling of the phys
Improve the error message when a unsolicited CT response is received by
printing fence that couldn't be found, the last fence, and all requests
with a response outstanding.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 10 +++---
1 file changed, 7 insertions(+)
== Series Details ==
Series: drm/i915: keep backlight_enable on until turn eDP display off (rev4)
URL : https://patchwork.freedesktop.org/series/91780/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10271 -> Patchwork_20448
On Thu, Jun 24, 2021 at 1:43 PM Christoph Hellwig wrote:
>
> On Wed, Jun 23, 2021 at 02:44:34PM -0400, Qian Cai wrote:
> > is_swiotlb_force_bounce at /usr/src/linux-next/./include/linux/swiotlb.h:119
> >
> > is_swiotlb_force_bounce() was the new function introduced in this patch
> > here.
> >
> >
== Series Details ==
Series: drm/i915: keep backlight_enable on until turn eDP display off (rev4)
URL : https://patchwork.freedesktop.org/series/91780/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8f8d8fc4ecbc drm/i915: keep backlight_enable on until turn eDP display off
-:116
On Wed, Jun 23, 2021 at 02:44:34PM -0400, Qian Cai wrote:
> is_swiotlb_force_bounce at /usr/src/linux-next/./include/linux/swiotlb.h:119
>
> is_swiotlb_force_bounce() was the new function introduced in this patch here.
>
> +static inline bool is_swiotlb_force_bounce(struct device *dev)
> +{
> +
This workaround is specific for a particular panel on Google
chromebook project. When user space daemon enter idle state.
It request adjust brightness to 0, turn backlight_enable signal
off and keep eDP main link active.
On general LCD, this behavior might not be a problem.
But on this panel, its
Please ignore this last patch. It was put together as an afterthought
and wasn't properly tested.
-David
On Thu, Jun 24, 2021 at 12:59 PM David Stevens wrote:
>
> Return struct page instead of pfn from gfn_to_mfn. This function is only
> used to determine if the page is a transparent hugepage, t
== Series Details ==
Series: KVM: Remove uses of struct page from x86 and arm64 MMU
URL : https://patchwork.freedesktop.org/series/91836/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compi
Return struct page instead of pfn from gfn_to_mfn. This function is only
used to determine if the page is a transparent hugepage, to enable 2MB
huge gtt shadowing. Returning the page directly avoids the risk of
calling pfn_to_page on a VM_IO|VM_PFNMAP pfn.
This change also properly releases the re
From: David Stevens
Remove two warnings that require ref counts for pages to be non-zero, as
mapped pfns from follow_pfn may not have an initialized ref count.
Signed-off-by: David Stevens
---
arch/x86/kvm/mmu/mmu.c | 7 ---
virt/kvm/kvm_main.c| 2 +-
2 files changed, 1 insertion(+), 8
From: David Stevens
Avoid converting pfns returned by follow_fault_pfn to struct pages to
transiently take a reference. The reference was originally taken to
match the reference taken by gup. However, pfns returned by
follow_fault_pfn may not have a struct page set up for reference
counting.
Sig
From: David Stevens
Avoid converting pfns returned by follow_fault_pfn to struct pages to
transiently take a reference. The reference was originally taken to
match the reference taken by gup. However, pfns returned by
follow_fault_pfn may not have a struct page set up for reference
counting.
Sig
From: David Stevens
Return a struct kvm_pfn_page containing both a pfn and an optional
struct page from the gfn_to_pfn family of functions. This differentiates
the gup and follow_fault_pfn cases, which allows callers that only need
a pfn to avoid touching the page struct in the latter case. For c
From: David Stevens
Signed-off-by: David Stevens
---
arch/x86/kvm/mmu/mmu_audit.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/kvm/mmu/mmu_audit.c b/arch/x86/kvm/mmu/mmu_audit.c
index cedc17b2f60e..97ff184084b4 100644
--- a/arch/x86/kvm/mmu/mmu_audit.c
+++ b/arch/x86/kvm/mmu/m
KVM supports mapping VM_IO and VM_PFNMAP memory into the guest by using
follow_pte in gfn_to_pfn. However, the resolved pfns may not have
assoicated struct pages, so they should not be passed to pfn_to_page.
This series removes such calls from the x86 and arm64 secondary MMU. To
do this, this serie
On Thu, 24 June 2021, Jani Nikula wrote:
>On Tue, 22 Jun 2021, Lee Shawn C wrote:
>> This workaround is specific for a particular panel on Google
>> chromebook project. When user space daemon enter idle state.
>> It request adjust brightness to 0, turn backlight_enable signal off
>> and keep eD
On Mon, May 31, 2021 at 09:48:45AM +0300, Stanislav Lisovskiy wrote:
> PSF GV points are an additional factor that can limit the
> bandwidth available to display, separate from the traditional
> QGV points. Whereas traditional QGV points represent possible
> memory clock frequencies, PSF GV points
On Mon, May 31, 2021 at 09:48:44AM +0300, Stanislav Lisovskiy wrote:
> According to BSpec there is now also a code 0x02,
> which corresponds to QGV point being rejected,
> this code so lets extend mask to check this.
>
> Signed-off-by: Stanislav Lisovskiy
Reviewed-by: Matt Roper
> ---
> drive
== Series Details ==
Series: drm/i915/display: Fix shared dpll mismatch for bigjoiner slave
URL : https://patchwork.freedesktop.org/series/91830/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10268_full -> Patchwork_20446_full
==
On 6/16/2021 11:43 PM, Dale B Stimson wrote:
As part of the System Managemenent Interface (SMI), use the HWMON
subsystem to display power utilization.
The following standard HWMON power sensors are currently supported
(and appropriately scaled):
/sys/class/drm/card0/device/hwmon/hwmon
Hi Matthew,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next drm/drm-next v5.13-rc7 next-20210623]
[If your patch is applied to the wrong git tree
== Series Details ==
Series: implicit fencing/dma-resv rules for shared buffers (rev5)
URL : https://patchwork.freedesktop.org/series/91789/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10268_full -> Patchwork_20444_full
S
== Series Details ==
Series: drm/i915/ttm: fix static warning
URL : https://patchwork.freedesktop.org/series/91821/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10268_full -> Patchwork_20443_full
Summary
---
**FAILU
Hi Matthew,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next drm/drm-next v5.13-rc7 next-20210623]
[If your patch is applied to the wrong git tree
== Series Details ==
Series: drm/i915/display: Fix shared dpll mismatch for bigjoiner slave
URL : https://patchwork.freedesktop.org/series/91830/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10268 -> Patchwork_20446
Summar
On Wed, 23 Jun 2021 at 20:15, Daniel Vetter wrote:
>
> On Wed, Jun 23, 2021 at 06:27:06PM +0100, Matthew Auld wrote:
> > Looks like it got lost along the way, so add it back. This is needed for
> > the region query uAPI where we want to report a snapshot of how much
> > lmem is available.
> >
> >
Looks good to me.
Reviewed-by: Gwan-gyeong Mun
On 6/16/21 11:31 PM, José Roberto de Souza wrote:
Another WA that is required for PSR2.
BSpec: 54369
Cc: Gwan-gyeong Mun
Cc: Matt Atwood
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 15 +++
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: support forcing the page size
with lmem
URL : https://patchwork.freedesktop.org/series/91820/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10268_full -> Patchwork_20442_full
On Wed, Jun 23, 2021 at 06:47:37PM +0200, Boris Brezillon wrote:
> On Tue, 22 Jun 2021 18:55:02 +0200
> Daniel Vetter wrote:
>
> > Currently this has no practial relevance I think because there's not
> > many who can pull off a setup with panfrost and another gpu in the
> > same system. But the r
Am 23.06.21 um 17:12 schrieb Daniel Vetter:
On Wed, Jun 23, 2021 at 05:07:17PM +0200, Christian König wrote:
Am 23.06.21 um 17:03 schrieb Daniel Vetter:
On Wed, Jun 23, 2021 at 04:58:27PM +0200, Bas Nieuwenhuizen wrote:
On Wed, Jun 23, 2021 at 4:50 PM Daniel Vetter wrote:
On Wed, Jun 23, 202
On Wed, Jun 23, 2021 at 06:27:06PM +0100, Matthew Auld wrote:
> Looks like it got lost along the way, so add it back. This is needed for
> the region query uAPI where we want to report a snapshot of how much
> lmem is available.
>
> This time around let's push it directly into the allocator, which
== Series Details ==
Series: drm/i915/display: Fix shared dpll mismatch for bigjoiner slave
URL : https://patchwork.freedesktop.org/series/91830/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9fd0e560efbd drm/i915/display: Fix shared dpll mismatch for bigjoiner slave
-:10: WARN
Am 23.06.21 um 17:03 schrieb Daniel Vetter:
On Wed, Jun 23, 2021 at 04:58:27PM +0200, Bas Nieuwenhuizen wrote:
On Wed, Jun 23, 2021 at 4:50 PM Daniel Vetter wrote:
On Wed, Jun 23, 2021 at 4:02 PM Christian König
wrote:
Am 23.06.21 um 15:49 schrieb Daniel Vetter:
On Wed, Jun 23, 2021 at 3:44
On 6/16/21 11:31 PM, José Roberto de Souza wrote:
Implements changes around PSR for alderlake-P:
- EDP_SU_TRACK_ENABLE was removed and bit 30 now has other function
- Some bits of PSR2_MAN_TRK_CTL moved and SF_PARTIAL_FRAME_UPDATE was
removed setting SU_REGION_START/END_ADDR will do this job
Currently when we do the HW state readout, we dont set the shared dpll to NULL
for the bigjoiner slave which should not have a DPLL assigned. So it has
some garbage while the HW state readout is NULL. So explicitly reset
the shared dpll for bigjoiner slave pipe.
Bug: https://gitlab.freedesktop.org
== Series Details ==
Series: drm/i915: Move system memory to TTM for discrete (rev9)
URL : https://patchwork.freedesktop.org/series/90898/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10268_full -> Patchwork_20441_full
Sum
looks good to me
Reviewed-by: Gwan-gyeong Mun
On 6/16/21 11:31 PM, José Roberto de Souza wrote:
PSR2 is not compatible with DC3CO or VRR in this stepping, so not
enabling PSR2 if VRR will be enabled or not enabling DC3CO if PSR2 is
possible.
BSpec: 54369
Cc: Gwan-gyeong Mun
Cc: Matt Atwood
looks good to me.
Reviewed-by: Gwan-gyeong Mun
On 6/16/21 11:31 PM, José Roberto de Souza wrote:
In some modes there is not enough time during hblank to transmit PSR2
SDP plus the pixels CRC SDP, if such case happens PSR2 needs to be
disabled.
But eDP spec 1.4b allows to transmit PSR2 SDP in a
== Series Details ==
Series: drm/i915: add back the avail tracking
URL : https://patchwork.freedesktop.org/series/91826/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10268 -> Patchwork_20445
Summary
---
**FAILURE**
Am 23.06.21 um 15:49 schrieb Daniel Vetter:
On Wed, Jun 23, 2021 at 3:44 PM Christian König
wrote:
Am 23.06.21 um 15:38 schrieb Bas Nieuwenhuizen:
On Wed, Jun 23, 2021 at 2:59 PM Christian König
wrote:
Am 23.06.21 um 14:18 schrieb Daniel Vetter:
On Wed, Jun 23, 2021 at 11:45 AM Bas Nieuwenh
Am 23.06.21 um 15:38 schrieb Bas Nieuwenhuizen:
On Wed, Jun 23, 2021 at 2:59 PM Christian König
wrote:
Am 23.06.21 um 14:18 schrieb Daniel Vetter:
On Wed, Jun 23, 2021 at 11:45 AM Bas Nieuwenhuizen
wrote:
On Tue, Jun 22, 2021 at 6:55 PM Daniel Vetter wrote:
WARNING: Absolutely untested bey
== Series Details ==
Series: series starting with [1/2] ALSA: hda: Release controller display power
during shutdown/reboot
URL : https://patchwork.freedesktop.org/series/91815/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10268_full -> Patchwork_20440_full
==
== Series Details ==
Series: implicit fencing/dma-resv rules for shared buffers (rev5)
URL : https://patchwork.freedesktop.org/series/91789/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10268 -> Patchwork_20444
Summary
---
Hi Daniel, looks good.
On Wed, Jun 23, 2021 at 06:24:56PM +0200, Daniel Vetter wrote:
> It's tedious to review this all the time, and my audit showed that
> arcpgu actually forgot to set this.
>
> Make this the default and stop worrying.
>
> Again I sprinkled WARN_ON_ONCE on top to make sure we
Hi Daniel, looks good.
On Wed, Jun 23, 2021 at 06:17:12PM +0200, Daniel Vetter wrote:
> Also review & update everything while we're at it.
>
> This is prep work to smash a ton of stuff into the kerneldoc for
> @resv.
>
> v2: Move the doc for sysfs_entry.attachment_uid to the right place too
> (S
Looks like it got lost along the way, so add it back. This is needed for
the region query uAPI where we want to report a snapshot of how much
lmem is available.
This time around let's push it directly into the allocator, which
simplifies things, like not having to care about internal fragmentation
== Series Details ==
Series: implicit fencing/dma-resv rules for shared buffers (rev5)
URL : https://patchwork.freedesktop.org/series/91789/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers
== Series Details ==
Series: implicit fencing/dma-resv rules for shared buffers (rev5)
URL : https://patchwork.freedesktop.org/series/91789/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ec4dbdd1b8f4 dma-resv: Fix kerneldoc
-:11: ERROR:GIT_COMMIT_ID: Please use git commit descr
== Series Details ==
Series: drm/i915/ttm: fix static warning
URL : https://patchwork.freedesktop.org/series/91821/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10268 -> Patchwork_20443
Summary
---
**SUCCESS**
No
Am 23.06.21 um 14:18 schrieb Daniel Vetter:
On Wed, Jun 23, 2021 at 11:45 AM Bas Nieuwenhuizen
wrote:
On Tue, Jun 22, 2021 at 6:55 PM Daniel Vetter wrote:
WARNING: Absolutely untested beyond "gcc isn't dying in agony".
Implicit fencing done properly needs to treat the implicit fencing
slots
On Tue, 22 Jun 2021 18:55:00 +0200
Daniel Vetter wrote:
> drm/scheduler requires a lock between _init and _push_job, but the
> reservation lock dance doesn't. So shrink the critical section a
> notch.
>
> v2: Lucas pointed out how this should really work, I got it all wrong
> in v1.
>
> Signed-
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