On Mon, May 31, 2021 at 09:48:44AM +0300, Stanislav Lisovskiy wrote:
> According to BSpec there is now also a code 0x02,
> which corresponds to QGV point being rejected,
> this code so lets extend mask to check this.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovs...@intel.com>
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4979b4965a82..0037e3d4049a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9349,7 +9349,7 @@ enum {
> #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) <<
> 16) | (0x1 << 8))
> #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
> #define ICL_PCODE_POINTS_RESTRICTED 0x0
> -#define ICL_PCODE_POINTS_RESTRICTED_MASK 0x1
> +#define ICL_PCODE_POINTS_RESTRICTED_MASK 0x3
> #define GEN6_PCODE_READ_D_COMP 0x10
> #define GEN6_PCODE_WRITE_D_COMP 0x11
> #define ICL_PCODE_EXIT_TCCOLD 0x12
> --
> 2.24.1.485.gad05a3d8e5
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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