== Series Details ==
Series: drm/i915: complete eDP MSO support (rev3)
URL : https://patchwork.freedesktop.org/series/87536/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9825_full -> Patchwork_19754_full
Summary
---
== Series Details ==
Series: i915/query: Correlate engine and cpu timestamps with better accuracy
(rev2)
URL : https://patchwork.freedesktop.org/series/87552/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9825_full -> Patchwork_19753_full
=
On 3/3/2021 4:10 PM, Daniele Ceraolo Spurio wrote:
On 3/3/2021 3:42 PM, Lionel Landwerlin wrote:
On 04/03/2021 01:25, Daniele Ceraolo Spurio wrote:
On 3/3/2021 3:16 PM, Lionel Landwerlin wrote:
On 03/03/2021 23:59, Daniele Ceraolo Spurio wrote:
On 3/3/2021 12:39 PM, Lionel Landwerlin
On 3/3/2021 2:04 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:52)
From: "Huang, Sean Z"
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. Additional
On 3/3/2021 2:08 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:51)
+static inline bool intel_pxp_is_active(const struct intel_pxp *pxp)
+{
+ return pxp->arb_is_in_play;
+}
+static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
+{
+ stru
On 3/3/2021 3:42 PM, Lionel Landwerlin wrote:
On 04/03/2021 01:25, Daniele Ceraolo Spurio wrote:
On 3/3/2021 3:16 PM, Lionel Landwerlin wrote:
On 03/03/2021 23:59, Daniele Ceraolo Spurio wrote:
On 3/3/2021 12:39 PM, Lionel Landwerlin wrote:
On 01/03/2021 21:31, Daniele Ceraolo Spurio wr
Quoting Umesh Nerlige Ramappa (2021-03-03 21:28:00)
> Perf measurements rely on CPU and engine timestamps to correlate
> events of interest across these time domains. Current mechanisms get
> these timestamps separately and the calculated delta between these
> timestamps lack enough accuracy.
>
>
On 04/03/2021 01:25, Daniele Ceraolo Spurio wrote:
On 3/3/2021 3:16 PM, Lionel Landwerlin wrote:
On 03/03/2021 23:59, Daniele Ceraolo Spurio wrote:
On 3/3/2021 12:39 PM, Lionel Landwerlin wrote:
On 01/03/2021 21:31, Daniele Ceraolo Spurio wrote:
From: Bommu Krishnaiah
This api allow use
== Series Details ==
Series: drm/i915: complete eDP MSO support (rev3)
URL : https://patchwork.freedesktop.org/series/87536/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9825 -> Patchwork_19754
Summary
---
**SUCCESS
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:57)
> From: Bommu Krishnaiah
>
> This api allow user mode to create Protected buffers. Only contexts
> marked as protected are allowed to operate on protected buffers.
>
> We only allow setting the flags at creation time.
>
> All protected object
On 3/3/2021 3:16 PM, Lionel Landwerlin wrote:
On 03/03/2021 23:59, Daniele Ceraolo Spurio wrote:
On 3/3/2021 12:39 PM, Lionel Landwerlin wrote:
On 01/03/2021 21:31, Daniele Ceraolo Spurio wrote:
From: Bommu Krishnaiah
This api allow user mode to create Protected buffers. Only contexts
ma
== Series Details ==
Series: drm/i915: complete eDP MSO support (rev3)
URL : https://patchwork.freedesktop.org/series/87536/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:55)
> Usage of protected objects, coming in a follow-up patch, will be
> restricted to protected contexts. Contexts can only be marked as
> protected at creation time and they must be both bannable and not
> recoverable.
>
> When a PXP teardown occu
On 03/03/2021 23:59, Daniele Ceraolo Spurio wrote:
On 3/3/2021 12:39 PM, Lionel Landwerlin wrote:
On 01/03/2021 21:31, Daniele Ceraolo Spurio wrote:
From: Bommu Krishnaiah
This api allow user mode to create Protected buffers. Only contexts
marked as protected are allowed to operate on prote
== Series Details ==
Series: i915/query: Correlate engine and cpu timestamps with better accuracy
(rev2)
URL : https://patchwork.freedesktop.org/series/87552/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9825 -> Patchwork_19753
===
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:54)
> +int intel_pxp_runtime_resume(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + int ret;
> +
> + if (!intel_pxp_is_enabled(pxp))
> + return 0;
> +
> + intel_pxp_irq_enable(pxp);
> +
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:53)
> +static int pxp_terminate(struct intel_pxp *pxp)
> +{
> + int ret = 0;
> +
> + mutex_lock(&pxp->mutex);
> +
> + pxp->global_state_attacked = true;
global_state_attacked is serialised by pxp->work
> +
> + ret = intel_px
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:53)
> From: "Huang, Sean Z"
>
> The HW will generate a teardown interrupt when session termination is
> required, which requires i915 to submit a terminating batch. Once the HW
> is done with the termination it will generate another interrupt, at
>
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:48)
> @@ -232,6 +235,13 @@ ktime_t intel_engine_get_busy_time(struct
> intel_engine_cs *engine,
>
> u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
>
> +struct intel_context *
> +intel_engine_pinned_context_create(struct intel_eng
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:51)
> +static inline bool intel_pxp_is_active(const struct intel_pxp *pxp)
> +{
> + return pxp->arb_is_in_play;
> +}
> +static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
> +{
> + struct intel_gt *gt = pxp_to_gt(pxp)
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:52)
> From: "Huang, Sean Z"
>
> Teardown is triggered when the display topology changes and no
> long meets the secure playback requirement, and hardware trashes
> all the encryption keys for display. Additionally, we want to emit a
> teardown oper
On 3/3/2021 12:39 PM, Lionel Landwerlin wrote:
On 01/03/2021 21:31, Daniele Ceraolo Spurio wrote:
From: Bommu Krishnaiah
This api allow user mode to create Protected buffers. Only contexts
marked as protected are allowed to operate on protected buffers.
We only allow setting the flags at cr
Perf measurements rely on CPU and engine timestamps to correlate
events of interest across these time domains. Current mechanisms get
these timestamps separately and the calculated delta between these
timestamps lack enough accuracy.
To improve the accuracy of these time measurements to within a f
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:53)
> From: "Huang, Sean Z"
>
> The HW will generate a teardown interrupt when session termination is
> required, which requires i915 to submit a terminating batch. Once the HW
> is done with the termination it will generate another interrupt, at
>
On 01/03/2021 21:31, Daniele Ceraolo Spurio wrote:
From: Bommu Krishnaiah
This api allow user mode to create Protected buffers. Only contexts
marked as protected are allowed to operate on protected buffers.
We only allow setting the flags at creation time.
All protected objects that have back
On Wed, Mar 03, 2021 at 10:47:44AM +0200, Pekka Paalanen wrote:
> On Tue, 2 Mar 2021 12:41:32 -0800
> Manasi Navare wrote:
>
> > In case of a modeset where a mode gets split across mutiple CRTCs
> > in the driver specific implementation (bigjoiner in i915) we wrongly count
> > the affected CRTCs
== Series Details ==
Series: i915/query: Correlate engine and cpu timestamps with better accuracy
URL : https://patchwork.freedesktop.org/series/87552/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9823_full -> Patchwork_19746_full
=
On Mon, Mar 01, 2021 at 11:32:00AM -0800, Daniele Ceraolo Spurio wrote:
> Note that discrete cards can support PXP as well, but we haven't tested
> on those yet so keeping it disabled for now.
>
> Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i91
== Series Details ==
Series: drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9
(rev6)
URL : https://patchwork.freedesktop.org/series/81764/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9824 -> Patchwork_19752
On Mon, Mar 01, 2021 at 11:31:45AM -0800, Daniele Ceraolo Spurio wrote:
> This will be used for communication between the i915 driver and the mei
> one. Defining it in a stand-alone patch to avoid circualr dependedencies
> between the patches modifying the 2 drivers.
>
> Split out from an original
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Move dc3co_exitline
variable to struct intel_psr
URL : https://patchwork.freedesktop.org/series/87596/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9824 -> Patchwork_19751
=
== Series Details ==
Series: drm/i915: complete eDP MSO support (rev2)
URL : https://patchwork.freedesktop.org/series/87536/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9824 -> Patchwork_19750
Summary
---
**FAILURE
== Series Details ==
Series: drm/i915: complete eDP MSO support (rev2)
URL : https://patchwork.freedesktop.org/series/87536/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/
== Series Details ==
Series: drm/atomic: Add the crtc to affected crtc only if uapi.enable = true
URL : https://patchwork.freedesktop.org/series/87555/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9824 -> Patchwork_19747
S
== Series Details ==
Series: series starting with [1/4] drm/i915/gen12: Add recommended hardware
tuning value (rev2)
URL : https://patchwork.freedesktop.org/series/87560/
State : failure
== Summary ==
Applying: drm/i915/gen12: Add recommended hardware tuning value
Applying: drm/i915/icl: add
== Series Details ==
Series: Public i915 CI shardruns are disabled
URL : https://patchwork.freedesktop.org/series/87558/
State : failure
== Summary ==
Applying: Public i915 CI shardruns are disabled
Using index info to reconstruct a base tree...
M include/linux/swap.h
M mm/page_io.
WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Gen9 to
resolve VP8 hardware encoding system hang up on GT1 sku for
ChromiumOS projects
Slice specific MMIO read inaccurate so MGSR needs to be programmed
appropriately to get correct reads from these slicet-related MMIOs.
It dictates that
== Series Details ==
Series: drm/atomic: Add the crtc to affected crtc only if uapi.enable = true
URL : https://patchwork.freedesktop.org/series/87555/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bf128dc47afb drm/atomic: Add the crtc to affected crtc only if uapi.enable =
tr
patch 1 is a nack for the reasons that Ville explained.
This one could be simplified even more.
intel_psr_enable_locked() should have all the dev_priv->psr.* initialization
from crtc_state + intel_dp_compute_psr_vsc_sdp().
Then add a function(_intel_psr_enable_locked() or other better name that
On Wed, 2021-03-03 at 18:42 +0200, Gwan-gyeong Mun wrote:
> It removes intel_crtc_state from function argument of
> intel_psr_enable_source() in order to use intel_psr_enable_source()
> without intel_crtc_state on other psr internal functions.
> And we can get cpu_trancoder from intel_psr, therefor
== Series Details ==
Series: i915/query: Correlate engine and cpu timestamps with better accuracy
URL : https://patchwork.freedesktop.org/series/87552/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9823 -> Patchwork_19746
S
On Wed, Mar 03, 2021 at 06:41:59PM +0200, Gwan-gyeong Mun wrote:
> dc3co_exitline is indirectly called by intel_psr_compute_config().
> And it will not be changed until the next calling of
> intel_psr_compute_config(). So in order to use dc3co_exitline without
> intel_crtc_state on other psr intern
This introduces the following function that can enable and disable psr
without intel_crtc_state when intel_psr is already enabled with current
intel_crtc_state information.
- intel_psr_pause(): Pause current PSR. it deactivates current psr state.
- intel_psr_resume(): Resume paused PSR without int
It removes intel_crtc_state from function argument of
intel_psr_enable_source() in order to use intel_psr_enable_source()
without intel_crtc_state on other psr internal functions.
And we can get cpu_trancoder from intel_psr, therefore we don't need to
pass intel_crtc_state to this function.
Cc: Jo
dc3co_exitline is indirectly called by intel_psr_compute_config().
And it will not be changed until the next calling of
intel_psr_compute_config(). So in order to use dc3co_exitline without
intel_crtc_state on other psr internal function, it moves dc3co_exitline
variable to struct intel_psr.
And it
On 03/03/2021 18:27, Umesh Nerlige Ramappa wrote:
On Wed, Mar 03, 2021 at 11:21:39AM +0200, Lionel Landwerlin wrote:
On 03/03/2021 02:12, Umesh Nerlige Ramappa wrote:
On Tue, Mar 02, 2021 at 10:35:19PM +0200, Lionel Landwerlin wrote:
Thanks a bunch for sharing this!
On 02/03/2021 20:29, Umesh
On Wed, Mar 03, 2021 at 11:21:39AM +0200, Lionel Landwerlin wrote:
On 03/03/2021 02:12, Umesh Nerlige Ramappa wrote:
On Tue, Mar 02, 2021 at 10:35:19PM +0200, Lionel Landwerlin wrote:
Thanks a bunch for sharing this!
On 02/03/2021 20:29, Umesh Nerlige Ramappa wrote:
Perf measurements rely on
> -Original Message-
> From: Nikula, Jani
> Sent: Tuesday, March 2, 2021 4:33 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma ; Nikula, Jani
> ;
> Varide, Nischal
> Subject: [PATCH v4 1/4] drm/i915/mso: add splitter state readout for
> platforms that
> support it
>
> Add
Hi Dave, Daniel,
Here's the first round of drm-misc-next changes for 5.13.
Maxime
drm-misc-next-2021-03-03:
drm-misc-next for 5.13:
UAPI Changes:
Cross-subsystem Changes:
Core Changes:
- %p4cc printk format modifier
- atomic: introduce drm_crtc_commit_wait, rework atomic plane state
h
On 03/03/2021 02:12, Umesh Nerlige Ramappa wrote:
On Tue, Mar 02, 2021 at 10:35:19PM +0200, Lionel Landwerlin wrote:
Thanks a bunch for sharing this!
On 02/03/2021 20:29, Umesh Nerlige Ramappa wrote:
Perf measurements rely on CPU and engine timestamps to correlate
events of interest across the
On Tue, 2 Mar 2021 12:41:32 -0800
Manasi Navare wrote:
> In case of a modeset where a mode gets split across mutiple CRTCs
> in the driver specific implementation (bigjoiner in i915) we wrongly count
> the affected CRTCs based on the drm_crtc_mask and indicate the stolen CRTC as
> an affected CR
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