patch 1 is a nack for the reasons that Ville explained.
This one could be simplified even more.
intel_psr_enable_locked() should have all the dev_priv->psr.* initialization
from crtc_state + intel_dp_compute_psr_vsc_sdp().
Then add a function(_intel_psr_enable_locked() or other better name that you
can think) with the error checking + intel_write_dp_vsc_sdp() +
intel_psr_enable_sink() + intel_psr_enable_source() + intel_psr_activate()...
intel_psr_resume()
take loock
checks
_intel_psr_enable_locked()
unlock()
On Wed, 2021-03-03 at 18:42 +0200, Gwan-gyeong Mun wrote:
> This introduces the following function that can enable and disable psr
> without intel_crtc_state when intel_psr is already enabled with current
> intel_crtc_state information.
>
> - intel_psr_pause(): Pause current PSR. it deactivates current psr state.
> - intel_psr_resume(): Resume paused PSR without intel_crtc_state.
> It activates paused psr state.
>
> Cc: José Roberto de Souza <jose.so...@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovs...@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong....@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 111 +++++++++++++++---
> drivers/gpu/drm/i915/display/intel_psr.h | 2 +
> 3 files changed, 97 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f69bd1caebbf..d49b79a0691a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1454,6 +1454,7 @@ struct intel_psr {
> u16 su_x_granularity;
> u32 dc3co_exitline;
> u32 dc3co_exit_delay;
> + bool paused;
> struct delayed_work dc3co_work;
> struct drm_dp_vsc_sdp vsc;
> };
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index ea8f9598e6a3..533fc21f4352 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -957,26 +957,11 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp)
> IGNORE_PSR2_HW_TRACKING : 0);
> }
>
>
> -static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *crtc_state,
> - const struct drm_connector_state
> *conn_state)
> +static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
> {
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_encoder *encoder = &dig_port->base;
> u32 val;
>
>
> - drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> -
> - intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> - intel_dp->psr.busy_frontbuffer_bits = 0;
> - intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> - intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> - /* DC5/DC6 requires at least 6 idle frames */
> - val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
> - intel_dp->psr.dc3co_exit_delay = val;
> - intel_dp->psr.psr2_sel_fetch_enabled =
> crtc_state->enable_psr2_sel_fetch;
> -
> /*
> * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
> * will still keep the error set even after the reset done in the
> @@ -997,9 +982,36 @@ static void intel_psr_enable_locked(struct intel_dp
> *intel_dp,
> intel_dp->psr.sink_not_reliable = true;
> drm_dbg_kms(&dev_priv->drm,
> "PSR interruption error set, not enabling PSR\n");
> - return;
> + return false;
> }
>
>
> + return true;
> +}
> +
> +static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state,
> + const struct drm_connector_state
> *conn_state)
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_encoder *encoder = &dig_port->base;
> + u32 val;
> +
> + drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> +
> + intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> + intel_dp->psr.busy_frontbuffer_bits = 0;
> + intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> + intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> + /* DC5/DC6 requires at least 6 idle frames */
> + val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
> + intel_dp->psr.dc3co_exit_delay = val;
> + intel_dp->psr.psr2_sel_fetch_enabled =
> crtc_state->enable_psr2_sel_fetch;
> + intel_dp->psr.paused = false;
> +
> + if (!psr_interrupt_error_check(intel_dp))
> + return;
> +
> drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
> intel_dp->psr.psr2_enabled ? "2" : "1");
> intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
> @@ -1149,6 +1161,71 @@ void intel_psr_disable(struct intel_dp *intel_dp,
> cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
> }
>
>
> +/**
> + * intel_psr_pause - Pause PSR
> + * @intel_dp: Intel DP
> + *
> + * This function need to be called after enabling psr.
> + */
> +void intel_psr_pause(struct intel_dp *intel_dp)
> +{
> + struct intel_psr *psr = &intel_dp->psr;
> +
> + if (!CAN_PSR(intel_dp))
> + return;
> +
> + mutex_lock(&psr->lock);
> +
> + if (!psr->enabled || psr->paused) {
> + mutex_unlock(&psr->lock);
> + return;
> + }
> +
> + intel_psr_disable_locked(intel_dp);
> + psr->paused = true;
> +
> + mutex_unlock(&psr->lock);
> +
> + cancel_work_sync(&psr->work);
> + cancel_delayed_work_sync(&psr->dc3co_work);
> +}
> +
> +/**
> + * intel_psr_resume - Resume PSR
> + * @intel_dp: Intel DP
> + *
> + * This function need to be called after pausing psr.
> + */
> +void intel_psr_resume(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_psr *psr = &intel_dp->psr;
> +
> + if (!CAN_PSR(intel_dp))
> + return;
> +
> + mutex_lock(&psr->lock);
> +
> + if (psr->enabled || !psr->paused)
> + goto unlock;
> +
> + psr->paused = false;
> +
> + if (!psr_interrupt_error_check(intel_dp))
> + goto unlock;
> +
> + drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
> + psr->psr2_enabled ? "2" : "1");
> + intel_psr_enable_sink(intel_dp);
> + intel_psr_enable_source(intel_dp);
> + intel_dp->psr.enabled = true;
> +
> + intel_psr_activate(intel_dp);
> +
> +unlock:
> + mutex_unlock(&psr->lock);
> +}
> +
> static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index 0491a49ffd50..8cc5e78fb1d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -48,5 +48,7 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane
> *plane,
> const struct intel_crtc_state
> *crtc_state,
> const struct intel_plane_state
> *plane_state,
> int color_plane);
> +void intel_psr_pause(struct intel_dp *intel_dp);
> +void intel_psr_resume(struct intel_dp *intel_dp);
>
>
> #endif /* __INTEL_PSR_H__ */
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