On 2020-11-06 at 10:52:03 +0530, Anshuman Gupta wrote:
> On 2020-11-05 at 21:04:03 +0530, Ramalingam C wrote:
> > On 2020-10-27 at 22:11:58 +0530, Anshuman Gupta wrote:
> > > Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
> > > in TRANS_DDI_FUNC_CTL in order to enable/disable
On 2020-11-06 at 10:20:35 +0530, Anshuman Gupta wrote:
> On 2020-11-05 at 22:09:12 +0530, Ramalingam C wrote:
> > On 2020-10-27 at 22:12:00 +0530, Anshuman Gupta wrote:
> > > Pass dig_port as an argument to intel_hdcp_init()
> > > and intel_hdcp2_init().
> > > This will be required for HDCP 2.2 str
On 2020-11-05 at 21:11:52 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:11:59 +0530, Anshuman Gupta wrote:
> > Enable HDCP 1.4 over DP MST for Gen12.
> > This also enable the stream encryption support for
> > older generations, which was missing earlier.
> It will be nice to have them in separat
On 2020-11-05 at 22:04:15 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:12:04 +0530, Anshuman Gupta wrote:
> > Add support for multiple mst stream in hdcp port data
> > which will be used by RepeaterAuthStreamManage msg and
> > HDCP 2.2 security f/w for m' validation.
> >
> > v2:
> > Init the h
On Thu, 05 Nov 2020, Lucas De Marchi wrote:
> On Thu, Nov 05, 2020 at 10:47:15AM +0530, Anshuman Gupta wrote:
>>On 2020-11-03 at 17:06:42 -0500, Rodrigo Vivi wrote:
>>> On Fri, Oct 30, 2020 at 11:46:58AM +0530, Anshuman Gupta wrote:
>>> > From: Bob Paauwe
>>> >
>>> > The WA specifies that we need
On 2020-11-05 at 21:04:03 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:11:58 +0530, Anshuman Gupta wrote:
> > Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
> > in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
> > encryption over DP MST Transport Link.
> >
> >
On 2020-11-05 at 22:15:37 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:12:05 +0530, Anshuman Gupta wrote:
> > This requires for HDCP 2.2 MST check link.
> >
> > Cc: Ramalingam C
> > Reviewed-by: Uma Shankar
> > Signed-off-by: Anshuman Gupta
> > ---
> > drivers/gpu/drm/i915/display/intel_di
== Series Details ==
Series: Big Joiner End End enabling with 8K@30, 60
URL : https://patchwork.freedesktop.org/series/83556/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9276 -> Patchwork_18865
Summary
---
**FAILUR
On 2020-11-05 at 22:09:12 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:12:00 +0530, Anshuman Gupta wrote:
> > Pass dig_port as an argument to intel_hdcp_init()
> > and intel_hdcp2_init().
> > This will be required for HDCP 2.2 stream encryption.
> >
> > Cc: Ramalingam C
> > Reviewed-by: Uma S
== Series Details ==
Series: Big Joiner End End enabling with 8K@30, 60
URL : https://patchwork.freedesktop.org/series/83556/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915
== Series Details ==
Series: Big Joiner End End enabling with 8K@30, 60
URL : https://patchwork.freedesktop.org/series/83556/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c255c8a307f4 drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner
modes
3140cb9ed5f5 drm/i91
== Series Details ==
Series: drm/i915: Correctly set SFC capability for video engines
URL : https://patchwork.freedesktop.org/series/83551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9274_full -> Patchwork_18864_full
Sum
Make vdsc work when no output is enabled. The big joiner needs VDSC
on the slave, so enable it and set the appropriate bits.
So remove encoder usage from dsc functions.
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.
Maarten Lankhorst (6):
drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
drm/i915: Try to make bigjoiner work in atomic check
drm/i915: Link planes in a bigjoiner configuration, v3.
drm/i915: Add bigjoi
No functional changes here, just adds a from_crtc_state
as a prep for bigjoiner
v2:
* More prep with intel_atomic_state (Ville)
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic.c | 9 +
drivers/gpu/drm/i915/displa
From: Maarten Lankhorst
Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.
v13:
* Allow bigjoiner if hdisplay >5120
v12:
* slice_count logic simplify (Ville)
* Fix unnecessary changes in downstream_mo
From: Maarten Lankhorst
With bigjoiner, there will be 2 pipes driving 2 halves of 1 transcoder,
because of this, we need a pipe_mode for various calculations, including
for example watermarks, plane clipping, etc.
v10:
* remove redundant pipe_mode assignment (Ville)
v9:
* pipe_mode in state dump
No functional changes, to align with previous cleanups pass
intel_atomic_state instead of drm_atomic_state.
Also pass this intel_atomic_state with crtc_state to
some of the atomic_check functions.
v2:
* Squash some changes from next patch (Ville)
Signed-off-by: Manasi Navare
Reviewed-by: Ville S
Enabling is done in a special sequence and so should plane updates
be. Ideally the end user never notices the second pipe is used.
This way ideally everything will be tear free, and updates are
really atomic as userspace expects it.
This uses generic modeset_enables() calls like trans port sync
b
From: Maarten Lankhorst
When the clock is higher than the dotclock, try with 2 pipes enabled.
If we can enable 2, then we will go into big joiner mode, and steal
the adjacent crtc.
This only links the crtc's in software, no hardware or plane
programming is done yet. Blobs are also copied fr
From: Maarten Lankhorst
We need to look at hw.fb for the framebuffer, and add the translation
for the slave_plane_state. With these changes we set the correct
rectangle on the bigjoiner slave, and don't set incorrect
src/dst/visibility on the slave plane.
v2:
* Manual rebase (Manasi)
v3:
* hw.r
Skip iterating over bigjoiner slaves, only the master has the state we
care about.
Add the width of the bigjoiner slave to the reconstructed fb.
Hide the bigjoiner slave to userspace, and double the mode on bigjoiner
master.
And last, disable bigjoiner slave from primary if reconstruction fails.
Create a new function intel_crtc_get_pipe_config()
that calls platform specific hooks for get_pipe_config()
No functional change here.
Suggested-by: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 14 +++---
1 fil
No functional changes. This patch just moves some mode checks
around to prepare for adding bigjoiner related mode validation
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
1 file changed, 6 insertions(+),
No functional changes, create a separate intel_encoder_get_config()
function that calls encoder->get_config hook.
This is needed so that later we can add beigjoienr related
readout here.
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 1
From: Maarten Lankhorst
Dump debugfs and planar links as well, this will make it easier to debug
when things go wrong.
v4:
* Rebase
Changes since v1:
- Report planar slaves as such, now that we have the plane_state switch.
Changes since v2:
- Rebase on top of the new plane format dumping
Signed
From: Maarten Lankhorst
Make sure that when a plane is set in a bigjoiner mode, we will add
their counterpart to the atomic state as well. This will allow us to
make sure all state is available when planes are checked.
Because of the funny interactions with bigjoiner and planar YUV
formats, w
== Series Details ==
Series: drm/i915: Correctly set SFC capability for video engines
URL : https://patchwork.freedesktop.org/series/83551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9274 -> Patchwork_18864
Summary
-
== Series Details ==
Series: drm/i915/gem: Drop free_work for GEM contexts (rev2)
URL : https://patchwork.freedesktop.org/series/83537/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9273_full -> Patchwork_18862_full
Summary
From: Venkata Sandeep Dhanalakota
SFC capability of video engines is not set correctly because i915
is testing for incorrect bits.
Fixes: c5d3e39caa45 ("drm/i915: Engine discovery query")
Cc: Matt Roper
Cc: Tvrtko Ursulin
Signed-off-by: Venkata Sandeep Dhanalakota
Signed-off-by: Daniele Cerao
Hi,
Here the failures are happening in:
i915_gem_object_create_stolen_for_preallocated causing the BAT failure.
Thsi is unrelated to the changes in this patch.
Manasi
On Thu, Nov 05, 2020 at 11:43:41PM +, Patchwork wrote:
> == Series Details ==
>
> Series: Final prep series for bigjoiner
>
== Series Details ==
Series: Final prep series for bigjoiner
URL : https://patchwork.freedesktop.org/series/83547/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9274 -> Patchwork_18863
Summary
---
**FAILURE**
Seri
== Series Details ==
Series: Final prep series for bigjoiner
URL : https://patchwork.freedesktop.org/series/83547/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a1e5aa27e03c drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner
modes
5c583972c6ab drm/i915: Move enc
On Thu, Nov 05, 2020 at 10:47:15AM +0530, Anshuman Gupta wrote:
On 2020-11-03 at 17:06:42 -0500, Rodrigo Vivi wrote:
On Fri, Oct 30, 2020 at 11:46:58AM +0530, Anshuman Gupta wrote:
> From: Bob Paauwe
>
> The WA specifies that we need to toggle a SDE chicken bit on and then
> off as the final st
Create a new function intel_crtc_get_pipe_config()
that calls platform specific hooks for get_pipe_config()
No functional change here.
Suggested-by: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 14 +++---
1 fil
Addressed all review comments in this, sending this to get final
CI results
Maarten Lankhorst (2):
drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
Manasi Navare (5):
drm/i915/dp: Some reshuffling in mode_v
No functional changes here, just adds a from_crtc_state
as a prep for bigjoiner
v2:
* More prep with intel_atomic_state (Ville)
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic.c | 9 +
drivers/gpu/drm/i915/displa
From: Maarten Lankhorst
Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.
v13:
* Allow bigjoiner if hdisplay >5120
v12:
* slice_count logic simplify (Ville)
* Fix unnecessary changes in downstream_mo
No functional changes. This patch just moves some mode checks
around to prepare for adding bigjoiner related mode validation
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
1 file changed, 6 insertions(+),
No functional changes, create a separate intel_encoder_get_config()
function that calls encoder->get_config hook.
This is needed so that later we can add beigjoienr related
readout here.
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 1
No functional changes, to align with previous cleanups pass
intel_atomic_state instead of drm_atomic_state.
Also pass this intel_atomic_state with crtc_state to
some of the atomic_check functions.
v2:
* Squash some changes from next patch (Ville)
Signed-off-by: Manasi Navare
Reviewed-by: Ville S
From: Maarten Lankhorst
With bigjoiner, there will be 2 pipes driving 2 halves of 1 transcoder,
because of this, we need a pipe_mode for various calculations, including
for example watermarks, plane clipping, etc.
v10:
* remove redundant pipe_mode assignment (Ville)
v9:
* pipe_mode in state dump
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gem: Allow backends to override
pread implementation
URL : https://patchwork.freedesktop.org/series/83541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9271_full -> Patchwork_18861_full
=
== Series Details ==
Series: drm/i915/gem: Drop free_work for GEM contexts (rev2)
URL : https://patchwork.freedesktop.org/series/83537/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9273 -> Patchwork_18862
Summary
---
On Thu, Nov 05, 2020 at 06:15:11PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 05, 2020 at 08:03:01AM -0800, Navare, Manasi wrote:
> > On Thu, Nov 05, 2020 at 05:13:04PM +0200, Ville Syrjälä wrote:
> > > On Mon, Nov 02, 2020 at 03:04:00PM -0800, Manasi Navare wrote:
> > > > From: Maarten Lankhorst
>
== Series Details ==
Series: series starting with [RFC,1/2] drm/i915: Improve record of hung engines
in error state (rev2)
URL : https://patchwork.freedesktop.org/series/83497/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9269_full -> Patchwork_18859_full
===
The free_list and worker was introduced in commit 5f09a9c8ab6b ("drm/i915:
Allow contexts to be unreferenced locklessly"), but subsequently made
redundant by the removal of the last sleeping lock in commit 2935ed5339c4
("drm/i915: Remove logical HW ID"). As we can now free the GEM context
immediate
Use userfault to arbitrarily delay the completion of copy_from_user() in
order to trap many, many threads inside the core of
gem_pread/gem_pwrite. This allows us to exhaust the preferred paths and
potentially trip over unexpected fallback paths.
Suggested-by: Matthew Auld
Signed-off-by: Chris Wil
Quoting Chris Wilson (2020-11-05 15:49:34)
> Move the specialised interactions with the physical GEM object from the
> pread/pwrite ioctl handler into the phys backend.
>
Fixes: c6790dc22312 ("drm/i915: Wean off drm_pci_alloc/drm_pci_free")
Testcase: igt/gem_pwrite/exhaustion
> Signed-off-by: Chr
> -Original Message-
> From: Souza, Jose
> Sent: Thursday, November 5, 2020 11:09 PM
> To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/display/tgl: Disable FBC with
> PSR2
>
> On Thu, 2020-11-05 at 21:57 +0530, Shankar, Uma wrote:
> >
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gem: Allow backends to override
pread implementation
URL : https://patchwork.freedesktop.org/series/83541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9271 -> Patchwork_18861
===
On Thu, 2020-11-05 at 21:57 +0530, Shankar, Uma wrote:
>
> > -Original Message-
> > From: Souza, Jose
> > Sent: Thursday, November 5, 2020 9:38 PM
> > To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/display/tgl: Disable FBC with
> > PS
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gem: Allow backends to override
pread implementation
URL : https://patchwork.freedesktop.org/series/83541/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit wo
Hi Dave and Daniel,
This includes gvt-fixes that had come last week, now with clean tags
for dim.
Also, 306bb61d6bb3 ("drm/i915/gt: Expose more parameters for emitting writes
into the ring") is only a dependency of its following patch.
In summary:
drm-intel-fixes-2020-11-05:
- GVT fixes includ
On 2020-10-27 at 22:12:06 +0530, Anshuman Gupta wrote:
> Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
> and HDCP2_AUTH_STREAM register in i915_reg header.
Reviewed-by: Ramalingam C
>
> Cc: Ramalingam C
> Reviewed-by: Uma Shankar
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/i915_re
On 2020-10-27 at 22:12:05 +0530, Anshuman Gupta wrote:
> This requires for HDCP 2.2 MST check link.
>
> Cc: Ramalingam C
> Reviewed-by: Uma Shankar
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c
On 2020-10-27 at 22:12:00 +0530, Anshuman Gupta wrote:
> Pass dig_port as an argument to intel_hdcp_init()
> and intel_hdcp2_init().
> This will be required for HDCP 2.2 stream encryption.
>
> Cc: Ramalingam C
> Reviewed-by: Uma Shankar
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i
On 2020-10-27 at 22:12:04 +0530, Anshuman Gupta wrote:
> Add support for multiple mst stream in hdcp port data
> which will be used by RepeaterAuthStreamManage msg and
> HDCP 2.2 security f/w for m' validation.
>
> v2:
> Init the hdcp port data k for HDMI/DP SST strem.
>
> v3:
> Cosmetic changes.
On Wed, 2020-11-04 at 08:43 +, Patchwork wrote:
Patch Details
Series: drm/i915/ehl: Implement W/A 22010492432 (rev3)
URL:https://patchwork.freedesktop.org/series/83135/
State: failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18848/index.html
CI Bug Log - changes
> -Original Message-
> From: Souza, Jose
> Sent: Thursday, November 5, 2020 9:38 PM
> To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/display/tgl: Disable FBC with
> PSR2
>
> On Thu, 2020-11-05 at 01:26 +0530, Uma Shankar wrote:
> > Th
On Tue, Nov 03, 2020 at 08:00:40AM -0800, Manasi Navare wrote:
> From: Maarten Lankhorst
>
> Small changes to intel_dp_mode_valid(), allow listing modes that
> can only be supported in the bigjoiner configuration, which is
> not supported yet.
>
> v13:
> * Allow bigjoiner if hdisplay >5120
> v12
Quoting Matthew Auld (2020-11-05 16:02:38)
> On Thu, 5 Nov 2020 at 15:45, Chris Wilson wrote:
> >
> > Quoting Matthew Auld (2020-11-05 15:40:20)
> > > On Thu, 5 Nov 2020 at 15:39, Matthew Auld
> > > wrote:
> > > >
> > > > On Thu, 5 Nov 2020 at 10:11, Chris Wilson
> > > > wrote:
> > > > >
> > >
On Thu, Nov 05, 2020 at 08:09:38AM -0800, Navare, Manasi wrote:
> On Thu, Nov 05, 2020 at 05:23:33PM +0200, Ville Syrjälä wrote:
> > On Thu, Nov 05, 2020 at 05:21:31PM +0200, Ville Syrjälä wrote:
> > > On Mon, Nov 02, 2020 at 01:19:05PM -0800, Manasi Navare wrote:
> > > > No functional changes here
On Thu, Nov 05, 2020 at 08:03:01AM -0800, Navare, Manasi wrote:
> On Thu, Nov 05, 2020 at 05:13:04PM +0200, Ville Syrjälä wrote:
> > On Mon, Nov 02, 2020 at 03:04:00PM -0800, Manasi Navare wrote:
> > > From: Maarten Lankhorst
> > >
> > > With bigjoiner, there will be 2 pipes driving 2 halves of 1
== Series Details ==
Series: drm/i915/gem: Drop free_work for GEM contexts
URL : https://patchwork.freedesktop.org/series/83537/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9269 -> Patchwork_18860
Summary
---
**FAI
@Ville, any feedback on this patch here?
Or should this be usptreamed as part of the core series
since this actually allows the 8K modes
Manasi
On Tue, Nov 03, 2020 at 08:00:40AM -0800, Manasi Navare wrote:
> From: Maarten Lankhorst
>
> Small changes to intel_dp_mode_valid(), allow listing mod
On 2020-10-27 at 22:12:03 +0530, Anshuman Gupta wrote:
> Let's define Maximum MST content streams up to four
> generically which can be supported by modern display
> controllers.
>
> Cc: Sean Paul
> Cc: Ramalingam C
> Acked-by: Maarten Lankhorst
> Reviewed-by: Uma Shankar
> Signed-off-by: Ansh
On Thu, Nov 05, 2020 at 05:23:33PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 05, 2020 at 05:21:31PM +0200, Ville Syrjälä wrote:
> > On Mon, Nov 02, 2020 at 01:19:05PM -0800, Manasi Navare wrote:
> > > No functional changes here. Just pass intel_atomic_state
> > > along with crtc_state to certain at
On Thu, 2020-11-05 at 01:26 +0530, Uma Shankar wrote:
> There are some corner cases wrt underrun when we enable
> FBC with PSR2 on TGL. Recommendation from hardware is to
> keep this combination disabled.
Do you have any references to this? HSD? BSpec?
>
> Signed-off-by: Uma Shankar
> ---
> dr
On 2020-10-27 at 22:12:02 +0530, Anshuman Gupta wrote:
> Fix the size of WIRED_REPEATER_AUTH_STREAM_REQ cmd buffer size.
> It is based upon the actual number of MST streams and size
> of wired_cmd_repeater_auth_stream_req_in.
> Excluding the size of hdcp_cmd_header.
>
> v2:
> hdcp_cmd_header size
On Thu, 5 Nov 2020 at 15:45, Chris Wilson wrote:
>
> Quoting Matthew Auld (2020-11-05 15:40:20)
> > On Thu, 5 Nov 2020 at 15:39, Matthew Auld
> > wrote:
> > >
> > > On Thu, 5 Nov 2020 at 10:11, Chris Wilson
> > > wrote:
> > > >
> > > > More the specialised interation with the physical GEM objec
On Thu, Nov 05, 2020 at 05:13:04PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 02, 2020 at 03:04:00PM -0800, Manasi Navare wrote:
> > From: Maarten Lankhorst
> >
> > With bigjoiner, there will be 2 pipes driving 2 halves of 1 transcoder,
> > because of this, we need a pipe_mode for various calculat
== Series Details ==
Series: series starting with [RFC,1/2] drm/i915: Improve record of hung engines
in error state (rev2)
URL : https://patchwork.freedesktop.org/series/83497/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9269 -> Patchwork_18859
=
Move the specialised interactions with the physical GEM object from the
pread/pwrite ioctl handler into the phys backend.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 55
drivers/gpu/drm/i915/i915_gem.c |
From: Matthew Auld
As there are more and more complicated interactions between the different
backing stores and userspace, push the control into the backends rather
than accumulate them all inside the ioctl handlers.
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wi
Quoting Matthew Auld (2020-11-05 15:40:20)
> On Thu, 5 Nov 2020 at 15:39, Matthew Auld
> wrote:
> >
> > On Thu, 5 Nov 2020 at 10:11, Chris Wilson wrote:
> > >
> > > More the specialised interation with the physical GEM object from the
> >
> > Move interaction
> >
> > > p
On 2020-10-27 at 22:11:59 +0530, Anshuman Gupta wrote:
> Enable HDCP 1.4 over DP MST for Gen12.
> This also enable the stream encryption support for
> older generations, which was missing earlier.
It will be nice to have them in separate patches.
-Ram
>
> v2:
> - Added debug print for stream encr
On Thu, 5 Nov 2020 at 15:39, Matthew Auld
wrote:
>
> On Thu, 5 Nov 2020 at 10:11, Chris Wilson wrote:
> >
> > More the specialised interation with the physical GEM object from the
>
> Move interaction
>
> > pread/pwrite ioctl handler into the phys backend.
> >
> > Signed
On Thu, 5 Nov 2020 at 10:11, Chris Wilson wrote:
>
> More the specialised interation with the physical GEM object from the
Move interaction
> pread/pwrite ioctl handler into the phys backend.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
__
On 2020-10-27 at 22:11:58 +0530, Anshuman Gupta wrote:
> Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
> in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
> encryption over DP MST Transport Link.
>
> HDCP 1.4 stream encryption requires to validate the stream encry
== Series Details ==
Series: series starting with [RFC,1/2] drm/i915: Improve record of hung engines
in error state (rev2)
URL : https://patchwork.freedesktop.org/series/83497/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit
On Thu, Nov 05, 2020 at 05:21:31PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 02, 2020 at 01:19:05PM -0800, Manasi Navare wrote:
> > No functional changes here. Just pass intel_atomic_state
> > along with crtc_state to certain atomic_check functions.
> > This will lay the foundation for adding bigjo
On Mon, Nov 02, 2020 at 01:19:05PM -0800, Manasi Navare wrote:
> No functional changes here. Just pass intel_atomic_state
> along with crtc_state to certain atomic_check functions.
> This will lay the foundation for adding bigjoiner master/slave
> states in atomic check.
>
> v2:
> * More prep with
On Mon, Nov 02, 2020 at 01:19:02PM -0800, Manasi Navare wrote:
> No functional changes, create a separate intel_encoder_get_config()
> function that calls encoder->get_config hook.
> This is needed so that later we can add beigjoienr related
> readout here.
>
> Signed-off-by: Manasi Navare
Revie
On Mon, Nov 02, 2020 at 01:19:04PM -0800, Manasi Navare wrote:
> No functional changes, to align with previous cleanups pass
> intel_atomic_state instead of drm_atomic_state.
> Also pass this intel_atomic_state with crtc_state to
> some of the atomic_check functions.
>
> Signed-off-by: Manasi Nava
On Mon, Nov 02, 2020 at 03:04:00PM -0800, Manasi Navare wrote:
> From: Maarten Lankhorst
>
> With bigjoiner, there will be 2 pipes driving 2 halves of 1 transcoder,
> because of this, we need a pipe_mode for various calculations, including
> for example watermarks, plane clipping, etc.
>
> v9:
>
The free_list and worker was introduced in commit 5f09a9c8ab6b ("drm/i915:
Allow contexts to be unreferenced locklessly"), but subsequently made
redundant by the removal of the last sleeping lock in commit 2935ed5339c4
("drm/i915: Remove logical HW ID"). As we can now free the GEM context
immediate
On Wed, Nov 04, 2020 at 10:36:55AM +0530, Tejas Upadhyay wrote:
> As per W/A implemented for TGL to program half of the nominal
> DCO divider fraction value which is also applicable on EHL.
>
> Changes since V2:
> - Apply stepping B0 till FOREVER
> - B0 - revid update as per Bspec 2915
On 2020-10-27 at 22:11:57 +0530, Anshuman Gupta wrote:
> DP MST stream encryption status requires time of a link frame
> in order to change its status, but as there were some HDCP
> encryption timeout observed earlier, it is safer to use
> ENCRYPT_STATUS_CHANGE_TIMEOUT_MS timeout for stream status
On 2020-10-27 at 22:11:56 +0530, Anshuman Gupta wrote:
> Gen12 has H/W delta with respect to HDCP{1.x,2.x} display engine
> instances lies in Transcoder instead of DDI as in Gen11.
>
> This requires hdcp driver to use mst_master_transcoder for link
> authentication and stream transcoder for stream
On Tue, 2020-11-03 at 07:07 +, Patchwork wrote:
> Patch Details
> Series: drm/i915/display: Use initial_fastset_check() to compute and apply
> the initial PSR state URL:
> https://patchwork.freedesktop.org/series/83375/ State: success Details:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchw
== Series Details ==
Series: series starting with [01/22] drm/i915/gem: Allow backends to override
pread implementation
URL : https://patchwork.freedesktop.org/series/83531/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9268 -> Patchwork_18858
On 2020-11-05 at 18:51:57 +0530, Ramalingam C wrote:
> On 2020-11-05 at 18:48:02 +0530, Ramalingam C wrote:
> > On 2020-10-27 at 22:11:53 +0530, Anshuman Gupta wrote:
> > > When crtc state need_modeset is true it is not necessary
> > > it is going to be a real modeset, it can turns to be a
> > > fa
On 2020-10-27 at 22:11:54 +0530, Anshuman Gupta wrote:
> Get DRM connector reference count while scheduling a prop work
> to avoid any possible destroy of DRM connector when it is in
> DRM_CONNECTOR_REGISTERED state.
>
> Fixes: a6597faa2d59 ("drm/i915: Protect workers against disappearing
> conne
On 2020-11-05 at 18:48:02 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:11:53 +0530, Anshuman Gupta wrote:
> > When crtc state need_modeset is true it is not necessary
> > it is going to be a real modeset, it can turns to be a
> > fastset instead of modeset.
> > This turns content protection pro
On 2020-10-27 at 22:11:53 +0530, Anshuman Gupta wrote:
> When crtc state need_modeset is true it is not necessary
> it is going to be a real modeset, it can turns to be a
> fastset instead of modeset.
> This turns content protection property to be DESIRED and hdcp
> update_pipe left with property t
== Series Details ==
Series: series starting with [01/22] drm/i915/gem: Allow backends to override
pread implementation
URL : https://patchwork.freedesktop.org/series/83531/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6fbdba27ca31 drm/i915/gem: Allow backends to override pre
Quoting Tvrtko Ursulin (2020-11-05 11:38:42)
> From: Tvrtko Ursulin
>
> Instead of printing out the internal engine mask, which can change between
> kernel versions making it difficult to map to actual engines, present a
> bitmask of hanging engines ABI classes. For example:
>
> [drm] GPU HANG
From: Tvrtko Ursulin
Instead of printing out the internal engine mask, which can change between
kernel versions making it difficult to map to actual engines, present a
bitmask of hanging engines ABI classes. For example:
[drm] GPU HANG: ecode 9:8:24dd, in gem_exec_schedu [1334]
Engine ABI
On Tue, Oct 27, 2020 at 10:39:51PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Generalize icl_get_first_dbuf_slice_offset() into something that
> just gives us the start+end of the dbuf chunk covered by the
> specified slices as a standard ddb entry. Initial idea was to use
> it during
1 - 100 of 128 matches
Mail list logo
