[Intel-gfx] [CI 1/2] drm/i915: don't conflate is_dgfx with fake lmem

2020-09-30 Thread Lucas De Marchi
When using fake lmem for tests, we are overriding the setting in device info for dgfx devices. Current users of IS_DGFX() except one are correct. However, as we add support for DG1, we are going to use it in additional places to trigger dgfx-only code path. In future if we need we can use HAS_LMEM

[Intel-gfx] [CI 2/2] drm/i915/dg1: Wait for pcode/uncore handshake at startup

2020-09-30 Thread Lucas De Marchi
From: Matt Roper DG1 does some additional pcode/uncore handshaking at boot time; this handshaking must complete before various other pcode commands are effective and before general work is submitted to the GPU. We need to poll a new pcode mailbox during startup until it reports that this handshak

Re: [Intel-gfx] [PATCH v6 23/24] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

2020-09-30 Thread Lucas De Marchi
On Wed, Sep 30, 2020 at 10:20:41AM -0700, Matt Roper wrote: On Tue, Sep 29, 2020 at 11:42:33PM -0700, Lucas De Marchi wrote: From: Anshuman Gupta DGFX devices have different DMC_DEBUG* counter MMIO address offset. Incorporate these changes in i915_reg.h for DG1 and handle i915_dmc_info accordi

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix TGL DKL PHY DP vswing handling

2020-09-30 Thread Patchwork
== Series Details == Series: drm/i915: Fix TGL DKL PHY DP vswing handling URL : https://patchwork.freedesktop.org/series/82277/ State : success == Summary == CI Bug Log - changes from CI_DRM_9083_full -> Patchwork_18603_full Summary ---

Re: [Intel-gfx] [PATCH] drm/i915: Fix TGL DKL PHY DP vswing handling

2020-09-30 Thread Kulkarni, Vandita
> -Original Message- > From: Ville Syrjala > Sent: Thursday, October 1, 2020 4:07 AM > To: intel-gfx@lists.freedesktop.org > Cc: sta...@vger.kernel.org; Kulkarni, Vandita ; > Shankar, Uma > Subject: [PATCH] drm/i915: Fix TGL DKL PHY DP vswing handling > > From: Ville Syrjälä > > The HD

Re: [Intel-gfx] [PATCH 2/4] drm/i915/guc: Improved reporting when GuC fails to load

2020-09-30 Thread Daniele Ceraolo Spurio
On 9/25/2020 4:26 PM, john.c.harri...@intel.com wrote: From: John Harrison Rather than just saying 'GuC failed to load: -110', actually print out the GuC status register and break it down into the individual fields. Signed-off-by: John Harrison Reviewed-by: Daniele Ceraolo Spurio Danie

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Skip over MI_NOOP when parsing

2020-09-30 Thread Patchwork
== Series Details == Series: drm/i915: Skip over MI_NOOP when parsing URL : https://patchwork.freedesktop.org/series/82268/ State : success == Summary == CI Bug Log - changes from CI_DRM_9081_full -> Patchwork_18601_full Summary ---

Re: [Intel-gfx] [PATCH 1/4] drm/i915/guc: Update to use firmware v49.0.1

2020-09-30 Thread Daniele Ceraolo Spurio
On 9/25/2020 4:26 PM, john.c.harri...@intel.com wrote: From: John Harrison The latest GuC firmware includes a number of interface changes that require driver updates to match. * Starting from Gen11, the ID to be provided to GuC needs to contain the engine class in bits [0..2] and the ins

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix TGL DKL PHY DP vswing handling

2020-09-30 Thread Patchwork
== Series Details == Series: drm/i915: Fix TGL DKL PHY DP vswing handling URL : https://patchwork.freedesktop.org/series/82277/ State : success == Summary == CI Bug Log - changes from CI_DRM_9083 -> Patchwork_18603 Summary --- **SUCC

Re: [Intel-gfx] [PATCH] drm/i915: Fix TGL DKL PHY DP vswing handling

2020-09-30 Thread Souza, Jose
On Thu, 2020-10-01 at 01:36 +0300, Ville Syrjala wrote: > From: Ville Syrjälä < > ville.syrj...@linux.intel.com > > > > The HDMI vs. not-HDMI check got inverted whem the bogus encoder->type > checks were eliminated. So now we're using 0 as the link rate on DP > and potentially non-zero on HDMI, wh

[Intel-gfx] [PATCH] drm/i915: Fix TGL DKL PHY DP vswing handling

2020-09-30 Thread Ville Syrjala
From: Ville Syrjälä The HDMI vs. not-HDMI check got inverted whem the bogus encoder->type checks were eliminated. So now we're using 0 as the link rate on DP and potentially non-zero on HDMI, which is exactly the opposite of what we want. The original bogus check actually worked more correctly by

Re: [Intel-gfx] [PATCH] i915: Introduce quirk for shifting eDP brightness.

2020-09-30 Thread Lyude Paul
On Wed, 2020-09-30 at 16:25 -0400, Lyude Paul wrote: > On Tue, 2020-09-29 at 13:32 -0600, Kevin Chowski wrote: > > Thank you for the reply. And in regards to digging into it further, > > thanks for requesting that I do some more due diligence here :) > > > > Also if you did get around to it, thank

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Read DIMM size in Gb rather than GB

2020-09-30 Thread Souza, Jose
On Wed, 2020-09-30 at 11:24 +, Patchwork wrote: > Patch Details > Series: drm/i915: Read DIMM size in Gb rather than GB > URL: https://patchwork.freedesktop.org/series/82210/ > State:success > Details: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18591/index.html >

Re: [Intel-gfx] [PATCH] i915: Introduce quirk for shifting eDP brightness.

2020-09-30 Thread Lyude Paul
On Tue, 2020-09-29 at 13:32 -0600, Kevin Chowski wrote: > Thank you for the reply. And in regards to digging into it further, > thanks for requesting that I do some more due diligence here :) > > Also if you did get around to it, thanks for double-checking with > Bill! Let me know if you'd like me

Re: [Intel-gfx] [PATCH v2] drm/i915/display/ehl: Limit eDP to HBR2

2020-09-30 Thread Souza, Jose
On Wed, 2020-09-30 at 15:56 +, Surendrakumar Upadhyay, TejaskumarX wrote: > > -Original Message- > From: Intel-gfx < > intel-gfx-boun...@lists.freedesktop.org > > On Behalf Of José Roberto de Souza > Sent: 29 September 2020 01:33 > To: > intel-gfx@lists.freedesktop.org > > Subject: [

[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [01/10] mm: update the documentation for vfree

2020-09-30 Thread Patchwork
== Series Details == Series: series starting with [01/10] mm: update the documentation for vfree URL : https://patchwork.freedesktop.org/series/82271/ State : failure == Summary == Applying: mm: update the documentation for vfree Applying: mm: add a VM_MAP_PUT_PAGES flag for vmap Applying: mm:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Skip over MI_NOOP when parsing

2020-09-30 Thread Patchwork
== Series Details == Series: drm/i915: Skip over MI_NOOP when parsing URL : https://patchwork.freedesktop.org/series/82268/ State : success == Summary == CI Bug Log - changes from CI_DRM_9081 -> Patchwork_18601 Summary --- **SUCCESS*

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: don't conflate is_dgfx with fake lmem

2020-09-30 Thread Patchwork
== Series Details == Series: drm/i915: don't conflate is_dgfx with fake lmem URL : https://patchwork.freedesktop.org/series/82265/ State : success == Summary == CI Bug Log - changes from CI_DRM_9079_full -> Patchwork_18598_full Summary

Re: [Intel-gfx] [PATCH v2 10/11] drm/i915: Plumb crtc_state to link training

2020-09-30 Thread Ville Syrjälä
On Wed, Sep 30, 2020 at 07:36:24PM +0300, Imre Deak wrote: > On Wed, Sep 30, 2020 at 02:34:48AM +0300, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Get rid of mode crtc->config usage, and some ad-hoc intel_dp state > > usage by plumbing the crtc state all the way down to the link training

Re: [Intel-gfx] remove alloc_vm_area v2

2020-09-30 Thread Daniel Vetter
On Wed, Sep 30, 2020 at 4:48 PM Christoph Hellwig wrote: > > On Tue, Sep 29, 2020 at 03:43:30PM +0300, Joonas Lahtinen wrote: > > Hmm, those are both committed after our last -next pull request, so they > > would normally only target next merge window. drm-next closes the merge > > window around -

Re: [Intel-gfx] [PATCH v2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2

2020-09-30 Thread Matt Roper
On Wed, Sep 30, 2020 at 03:57:58PM +0300, Jani Nikula wrote: > On Wed, 30 Sep 2020, Ville Syrjälä wrote: > > Now we have an actual difference between EHL and JSL so we > > should split. Granted it's a bit annoying to have to do it > > just for some vswing tables. Ideally that stuff would be > > sp

[Intel-gfx] [PATCH 07/10] drm/i915: use vmap in i915_gem_object_map

2020-09-30 Thread Christoph Hellwig
i915_gem_object_map implements fairly low-level vmap functionality in a driver. Split it into two helpers, one for remapping kernel memory which can use vmap, and one for I/O memory that uses vmap_pfn. The only practical difference is that alloc_vm_area prefeaults the vmalloc area PTEs, which doe

[Intel-gfx] [PATCH 08/10] xen/xenbus: use apply_to_page_range directly in xenbus_map_ring_pv

2020-09-30 Thread Christoph Hellwig
Replacing alloc_vm_area with get_vm_area_caller + apply_page_range allows to fill put the phys_addr values directly instead of doing another loop over all addresses. Signed-off-by: Christoph Hellwig Reviewed-by: Boris Ostrovsky --- drivers/xen/xenbus/xenbus_client.c | 30 ---

[Intel-gfx] [PATCH 10/10] mm: remove alloc_vm_area

2020-09-30 Thread Christoph Hellwig
All users are gone now. Signed-off-by: Christoph Hellwig --- include/linux/vmalloc.h | 5 + mm/nommu.c | 7 -- mm/vmalloc.c| 48 - 3 files changed, 1 insertion(+), 59 deletions(-) diff --git a/include/linux/vmalloc.h b/i

[Intel-gfx] remove alloc_vm_area v3

2020-09-30 Thread Christoph Hellwig
Hi Andrew, this series removes alloc_vm_area, which was left over from the big vmalloc interface rework. It is a rather arkane interface, basicaly the equivalent of get_vm_area + actually faulting in all PTEs in the allocated area. It was originally addeds for Xen (which isn't modular to start w

[Intel-gfx] [PATCH 04/10] mm: allow a NULL fn callback in apply_to_page_range

2020-09-30 Thread Christoph Hellwig
Besides calling the callback on each page, apply_to_page_range also has the effect of pre-faulting all PTEs for the range. To support callers that only need the pre-faulting, make the callback optional. Based on a patch from Minchan Kim . Signed-off-by: Christoph Hellwig --- mm/memory.c | 16 +

[Intel-gfx] [PATCH 09/10] x86/xen: open code alloc_vm_area in arch_gnttab_valloc

2020-09-30 Thread Christoph Hellwig
Replace the last call to alloc_vm_area with an open coded version using an iterator in struct gnttab_vm_area instead of the triple indirection magic in alloc_vm_area. Signed-off-by: Christoph Hellwig Reviewed-by: Boris Ostrovsky --- arch/x86/xen/grant-table.c | 27 --- 1

[Intel-gfx] [PATCH 03/10] mm: add a vmap_pfn function

2020-09-30 Thread Christoph Hellwig
Add a proper helper to remap PFNs into kernel virtual space so that drivers don't have to abuse alloc_vm_area and open coded PTE manipulation for it. Signed-off-by: Christoph Hellwig --- include/linux/vmalloc.h | 1 + mm/Kconfig | 3 +++ mm/vmalloc.c| 45 ++

[Intel-gfx] [PATCH 01/10] mm: update the documentation for vfree

2020-09-30 Thread Christoph Hellwig
From: "Matthew Wilcox (Oracle)" * Document that you can call vfree() on an address returned from vmap() * Remove the note about the minimum size -- the minimum size of a vmalloc allocation is one page * Add a Context: section * Fix capitalisation * Reword the prohibition on calling from N

[Intel-gfx] [PATCH 05/10] zsmalloc: switch from alloc_vm_area to get_vm_area

2020-09-30 Thread Christoph Hellwig
Just manually pre-fault the PTEs using apply_to_page_range. Co-developed-by: Minchan Kim Signed-off-by: Christoph Hellwig --- mm/zsmalloc.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/mm/zsmalloc.c b/mm/zsmalloc.c index c36fdff9a37131..918c7b019b3d78 100644 --

[Intel-gfx] [PATCH 02/10] mm: add a VM_MAP_PUT_PAGES flag for vmap

2020-09-30 Thread Christoph Hellwig
Add a flag so that vmap takes ownership of the passed in page array. When vfree is called on such an allocation it will put one reference on each page, and free the page array itself. Signed-off-by: Christoph Hellwig --- include/linux/vmalloc.h | 1 + mm/vmalloc.c| 9 +++-- 2 fil

[Intel-gfx] [PATCH 06/10] drm/i915: use vmap in shmem_pin_map

2020-09-30 Thread Christoph Hellwig
shmem_pin_map somewhat awkwardly reimplements vmap using alloc_vm_area and manual pte setup. The only practical difference is that alloc_vm_area prefeaults the vmalloc area PTEs, which doesn't seem to be required here (and could be added to vmap using a flag if actually required). Switch to use v

Re: [Intel-gfx] [PATCH v6 19/24] drm/i915/dg1: enable PORT C/D aka D/E

2020-09-30 Thread Matt Roper
On Tue, Sep 29, 2020 at 11:42:29PM -0700, Lucas De Marchi wrote: > For DG1 we have a little of mix up wrt to DDI/port names and indexes. > Bspec refers to the ports as DDIA, DDIB, DDI USBC1 and DDI USBC2 > (besides the DDIA, DDIB, DDIC, DDID), but the previous naming is the > most unambiguous one.

[Intel-gfx] [PATCH] drm/i915: Skip over MI_NOOP when parsing

2020-09-30 Thread Chris Wilson
Though less likely in practice, igt uses MI_NOOP frequently to pad out its the batch buffers. The lookup and valiation of the MI_NOOP command description is noticeable, though the side-effect of poisoning the last-validate-command cache is more likely to impact upon real CS. Signed-off-by: Chris W

Re: [Intel-gfx] [PATCH v6 23/24] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

2020-09-30 Thread Matt Roper
On Tue, Sep 29, 2020 at 11:42:33PM -0700, Lucas De Marchi wrote: > From: Anshuman Gupta > > DGFX devices have different DMC_DEBUG* counter MMIO address > offset. Incorporate these changes in i915_reg.h for DG1 > and handle i915_dmc_info accordingly. > > Cc: Uma Shankar > Signed-off-by: Anshuman

Re: [Intel-gfx] [PATCH v2 11/11] drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl, status}

2020-09-30 Thread Imre Deak
On Wed, Sep 30, 2020 at 02:34:49AM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Now that we've plumbed the crtc state all the way down we can > eliminate the DP_TP_{CTL,STATUS} register offsets from intel_dp, > and instead we derive them directly from the crtc state. > > And thus we can

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915/gt: Signal cancelled requests

2020-09-30 Thread Patchwork
== Series Details == Series: series starting with [CI,1/3] drm/i915/gt: Signal cancelled requests URL : https://patchwork.freedesktop.org/series/82267/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9079 -> Patchwork_18600 S

Re: [Intel-gfx] [PATCH rdma-next v4 4/4] RDMA/umem: Move to allocate SG table from pages

2020-09-30 Thread Jason Gunthorpe
On Wed, Sep 30, 2020 at 06:05:15PM +0300, Maor Gottlieb wrote: > This is right only for the last iteration. E.g. in the first iteration in > case that there are more pages (left_pages), then we allocate > SG_MAX_SINGLE_ALLOC.  We don't know how many pages from the second iteration > will be squashe

Re: [Intel-gfx] [PATCH rdma-next v4 4/4] RDMA/umem: Move to allocate SG table from pages

2020-09-30 Thread Maor Gottlieb
On 9/30/2020 6:14 PM, Jason Gunthorpe wrote: On Wed, Sep 30, 2020 at 06:05:15PM +0300, Maor Gottlieb wrote: This is right only for the last iteration. E.g. in the first iteration in case that there are more pages (left_pages), then we allocate SG_MAX_SINGLE_ALLOC.  We don't know how many pages

Re: [Intel-gfx] [PATCH rdma-next v4 4/4] RDMA/umem: Move to allocate SG table from pages

2020-09-30 Thread Maor Gottlieb
On 9/30/2020 2:58 PM, Jason Gunthorpe wrote: On Wed, Sep 30, 2020 at 02:53:58PM +0300, Maor Gottlieb wrote: On 9/30/2020 2:45 PM, Jason Gunthorpe wrote: On Wed, Sep 30, 2020 at 12:53:21PM +0300, Leon Romanovsky wrote: On Tue, Sep 29, 2020 at 04:59:29PM -0300, Jason Gunthorpe wrote: On Sun, S

Re: [Intel-gfx] [PATCH rdma-next v4 4/4] RDMA/umem: Move to allocate SG table from pages

2020-09-30 Thread Leon Romanovsky
On Wed, Sep 30, 2020 at 12:14:06PM -0300, Jason Gunthorpe wrote: > On Wed, Sep 30, 2020 at 06:05:15PM +0300, Maor Gottlieb wrote: > > This is right only for the last iteration. E.g. in the first iteration in > > case that there are more pages (left_pages), then we allocate > > SG_MAX_SINGLE_ALLOC. 

Re: [Intel-gfx] [PATCH v6 22/24] drm/i915/dg1: DG1 does not support DC6

2020-09-30 Thread Matt Roper
On Tue, Sep 29, 2020 at 11:42:32PM -0700, Lucas De Marchi wrote: > From: Anshuman Gupta > > DC6 is not supported on DG1, so change the allowed DC mask for DG1. > > Cc: Uma Shankar > Signed-off-by: Anshuman Gupta Do we have a bspec reference for this? I can't find anything specific about this

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/3] drm/i915/gt: Signal cancelled requests

2020-09-30 Thread Patchwork
== Series Details == Series: series starting with [CI,1/3] drm/i915/gt: Signal cancelled requests URL : https://patchwork.freedesktop.org/series/82267/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separatel

Re: [Intel-gfx] [PATCH v2 10/11] drm/i915: Plumb crtc_state to link training

2020-09-30 Thread Imre Deak
On Wed, Sep 30, 2020 at 02:34:48AM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Get rid of mode crtc->config usage, and some ad-hoc intel_dp state > usage by plumbing the crtc state all the way down to the link training > code. > > Unfortunately we do have to keep some cached state in i

[Intel-gfx] [CI 3/3] drm/i915/gt: Retire cancelled requests on unload

2020-09-30 Thread Chris Wilson
If we manage to hit the intel_gt_set_wedged_on_fini() while active, i.e. module unload during a stress test, we may cancel the requests but not clean up. This leads to a very slow module unload as we wait for something or other to trigger the retirement flushing, or timeout and unload with a bunch

[Intel-gfx] [CI 1/3] drm/i915/gt: Signal cancelled requests

2020-09-30 Thread Chris Wilson
After marking the requests on an engine as cancelled upon wedging, send any signals for their completions. Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/gt/intel_lrc.c | 1 + drivers/gpu/drm/i915/gt/intel_ring_submission.c | 1 + 2 files changed, 2 i

[Intel-gfx] [CI 2/3] drm/i915/selftests: Finish pending mock requests on cancellation.

2020-09-30 Thread Chris Wilson
Flush all the pending requests from the mock engine when they are cancelled. Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/gt/mock_engine.c | 29 +++ 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/m

Re: [Intel-gfx] [PATCH] drm/i915: don't conflate is_dgfx with fake lmem

2020-09-30 Thread Lucas De Marchi
On Wed, Sep 30, 2020 at 04:58:42PM +0100, Matthew Auld wrote: On Wed, 30 Sep 2020 at 16:30, Lucas De Marchi wrote: When using fake lmem for tests, we are overriding the setting in device info for dgfx devices. Current users of IS_DGFX() are correct, but as we add support for DG1, we are going

Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Signal cancelled requests

2020-09-30 Thread Chris Wilson
Quoting Matthew Auld (2020-09-30 17:25:35) > On Tue, 29 Sep 2020 at 09:29, Chris Wilson wrote: > > > > After marking the requests on an engine as cancelled upon wedging, send > > any signals for their completions. > > > > Signed-off-by: Chris Wilson > > Fwiw these were all previously reviewed at

Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Signal cancelled requests

2020-09-30 Thread Matthew Auld
On Tue, 29 Sep 2020 at 09:29, Chris Wilson wrote: > > After marking the requests on an engine as cancelled upon wedging, send > any signals for their completions. > > Signed-off-by: Chris Wilson Fwiw these were all previously reviewed at: https://patchwork.freedesktop.org/series/81729/ _

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: don't conflate is_dgfx with fake lmem

2020-09-30 Thread Patchwork
== Series Details == Series: drm/i915: don't conflate is_dgfx with fake lmem URL : https://patchwork.freedesktop.org/series/82265/ State : success == Summary == CI Bug Log - changes from CI_DRM_9079 -> Patchwork_18598 Summary --- **S

Re: [Intel-gfx] [PATCH v6 20/24] drm/i915/dg1: Load DMC

2020-09-30 Thread Lucas De Marchi
On Wed, Sep 30, 2020 at 09:10:43AM -0700, Matt Roper wrote: On Tue, Sep 29, 2020 at 11:42:30PM -0700, Lucas De Marchi wrote: From: Matt Atwood Add support to load DMC v2.0.2 on DG1 While we're at it, make TGL use the same GEN12 firmware size definition and remove obsolete comment. Bpec: 4923

Re: [Intel-gfx] [PATCH v6 12/24] drm/i915/dg1: gmbus pin mapping

2020-09-30 Thread Matt Roper
On Tue, Sep 29, 2020 at 11:42:22PM -0700, Lucas De Marchi wrote: > Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC. > From spec we have registers GPIO_CTL[1-4], so we should not do the 4->9 > mapping as in ICL/TGL. > > The values for VBT seem wrong in BSpec. For the current

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/display/ehl: Limit eDP to HBR2 (rev3)

2020-09-30 Thread Patchwork
== Series Details == Series: drm/i915/display/ehl: Limit eDP to HBR2 (rev3) URL : https://patchwork.freedesktop.org/series/82162/ State : failure == Summary == Applying: drm/i915/display/ehl: Limit eDP to HBR2 error: corrupt patch at line 37 error: could not build fake ancestor hint: Use 'git

Re: [Intel-gfx] [PATCH v6 20/24] drm/i915/dg1: Load DMC

2020-09-30 Thread Matt Roper
On Tue, Sep 29, 2020 at 11:42:30PM -0700, Lucas De Marchi wrote: > From: Matt Atwood > > Add support to load DMC v2.0.2 on DG1 > > While we're at it, make TGL use the same GEN12 firmware size definition > and remove obsolete comment. > > Bpec: 49230 > > v2: do not replace GEN12_CSR_MAX_FW_SIZE

Re: [Intel-gfx] [PATCH] drm/i915: don't conflate is_dgfx with fake lmem

2020-09-30 Thread Matthew Auld
On Wed, 30 Sep 2020 at 16:30, Lucas De Marchi wrote: > > When using fake lmem for tests, we are overriding the setting in > device info for dgfx devices. Current users of IS_DGFX() are correct, > but as we add support for DG1, we are going to use it in additional > places to trigger dgfx-only code

Re: [Intel-gfx] [PATCH v2] drm/i915/display/ehl: Limit eDP to HBR2

2020-09-30 Thread Surendrakumar Upadhyay, TejaskumarX
-Original Message- From: Intel-gfx On Behalf Of José Roberto de Souza Sent: 29 September 2020 01:33 To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v2] drm/i915/display/ehl: Limit eDP to HBR2 Recent update in documentation defeatured eDP HBR3 for EHL and JSL. v2: - Rem

Re: [Intel-gfx] [PATCH v6 04/24] drm/i915/dg1: Add DG1 power wells

2020-09-30 Thread Matt Roper
On Tue, Sep 29, 2020 at 11:42:14PM -0700, Lucas De Marchi wrote: > From: Uma Shankar > > Most of TGL power wells are re-used for DG1. However, AUDIO Power > Domain is moved from PG3 to PG0. Handle the change and initialize This note is no longer valid. Although audio MMIO and verbs have moved t

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Plumb crtc state to link training code (rev4)

2020-09-30 Thread Patchwork
== Series Details == Series: drm/i915: Plumb crtc state to link training code (rev4) URL : https://patchwork.freedesktop.org/series/76993/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9077_full -> Patchwork_18596_full Summ

[Intel-gfx] [PATCH] drm/i915: don't conflate is_dgfx with fake lmem

2020-09-30 Thread Lucas De Marchi
When using fake lmem for tests, we are overriding the setting in device info for dgfx devices. Current users of IS_DGFX() are correct, but as we add support for DG1, we are going to use it in additional places to trigger dgfx-only code path. In future if we need we can use HAS_LMEM() instead of IS

Re: [Intel-gfx] [PATCH v2 09/11] drm/i915: Split TGL DKL PHY buf trans per output type

2020-09-30 Thread Imre Deak
On Wed, Sep 30, 2020 at 02:34:47AM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Make the mess inside the buf trans funcs a bit more manageable by > splitting along the lines of output type. > > Signed-off-by: Ville Syrjälä Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/display

Re: [Intel-gfx] [PATCH v2 08/11] drm/i915: Split TGL combo PHY buf trans per output type

2020-09-30 Thread Imre Deak
On Wed, Sep 30, 2020 at 02:34:46AM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Make the mess inside the buf trans funcs a bit more manageable by > splitting along the lines of output type. > > Signed-off-by: Ville Syrjälä Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/display

Re: [Intel-gfx] [PATCH v2 07/11] drm/i915: Split EHL combo PHY buf trans per output type

2020-09-30 Thread Imre Deak
On Wed, Sep 30, 2020 at 02:34:45AM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Make the mess inside the buf trans funcs a bit more manageable by > splitting along the lines of output type. > > Signed-off-by: Ville Syrjälä Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/display

Re: [Intel-gfx] [PATCH v2 06/11] drm/i915: Split ICL MG PHY buf trans per output type

2020-09-30 Thread Imre Deak
On Wed, Sep 30, 2020 at 02:34:44AM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Make the mess inside the buf trans funcs a bit more manageable by > splitting along the lines of output type. > > Signed-off-by: Ville Syrjälä Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/display

Re: [Intel-gfx] [PATCH v2 05/11] drm/i915: Split ICL combo PHY buf trans per output type

2020-09-30 Thread Imre Deak
On Wed, Sep 30, 2020 at 02:34:43AM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Make the mess inside the buf trans funcs a bit more manageable by > splitting along the lines of output type. > > Signed-off-by: Ville Syrjälä Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/display

Re: [Intel-gfx] [PATCH v3 04/11] drm/i915: Shove the PHY test into the hotplug work

2020-09-30 Thread Imre Deak
On Wed, Sep 30, 2020 at 01:04:12PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Doing nay kind modeset stuff from the short hpd handler is > verboten. The ad-hoc PHY test modeset code violates this. And > by calling various link training related functions it's now > blocking further work

[Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915: Force state->modeset=true when distrust_bios_wm==true"

2020-09-30 Thread Patchwork
== Series Details == Series: Revert "drm/i915: Force state->modeset=true when distrust_bios_wm==true" URL : https://patchwork.freedesktop.org/series/82261/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9078 -> Patchwork_18597 ===

Re: [Intel-gfx] remove alloc_vm_area v2

2020-09-30 Thread Christoph Hellwig
On Tue, Sep 29, 2020 at 03:43:30PM +0300, Joonas Lahtinen wrote: > Hmm, those are both committed after our last -next pull request, so they > would normally only target next merge window. drm-next closes the merge > window around -rc5 already. > > But, in this specific case those are both Fixes: p

Re: [Intel-gfx] [PATCH v6 01/24] drm/i915/dg1: add more PCI ids

2020-09-30 Thread Matt Roper
On Tue, Sep 29, 2020 at 11:42:11PM -0700, Lucas De Marchi wrote: > Synchronize with the current list of DG1 PCI IDs. > > Signed-off-by: Lucas De Marchi Reviewed-by: Matt Roper > --- > include/drm/i915_pciids.h | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/inclu

Re: [Intel-gfx] [PATCH v2 03/11] drm/i915: Make intel_dp_process_phy_request() static

2020-09-30 Thread Imre Deak
On Wed, Sep 30, 2020 at 02:34:41AM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > intel_dp_process_phy_request() has no business being externally > visible. Make it static. > > Signed-off-by: Ville Syrjälä Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/display/intel_dp.c | 2 +-

Re: [Intel-gfx] [PATCH v2 02/11] drm/i915: s/old_crtc_state/crtc_state/

2020-09-30 Thread Imre Deak
On Wed, Sep 30, 2020 at 02:34:40AM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > intel_dp_enable_port() is called during the enable sequence, > so there is nothing old about the passed in crtc state. > Rename it. > > Signed-off-by: Ville Syrjälä Reviewed-by: Imre Deak > --- > driver

Re: [Intel-gfx] [PATCH v2 01/11] drm/i915: s/pre_empemph/preemph/

2020-09-30 Thread Imre Deak
On Wed, Sep 30, 2020 at 02:34:39AM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > I managed to fumble some functions names. Fix them. > > Signed-off-by: Ville Syrjälä Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/display/intel_dp.c | 8 > 1 file changed, 4 insertions(+

[Intel-gfx] [PATCH] Revert "drm/i915: Force state->modeset=true when distrust_bios_wm==true"

2020-09-30 Thread Stefan Joosten
The fix of flagging state->modeset whenever distrust_bios_wm is set causes a regression when initializing display(s) attached to a Lenovo USB-C docking station. The display remains blank until the dock is reattached. Revert to bring the behavior of the functional v5.6 stable. This reverts commit 0

[Intel-gfx] [PATCH v4 44/52] docs: gpu: i915.rst: Fix several C duplication warnings

2020-09-30 Thread Mauro Carvalho Chehab
As reported by Sphinx: ./Documentation/gpu/i915:646: ./drivers/gpu/drm/i915/i915_perf.c:1147: WARNING: Duplicate C declaration, also defined in 'gpu/i915'. Declaration is 'i915_oa_wait_unlocked'. ./Documentation/gpu/i915:646: ./drivers/gpu/drm/i915/i915_perf.c:1169: WARNI

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Plumb crtc state to link training code (rev3)

2020-09-30 Thread Patchwork
== Series Details == Series: drm/i915: Plumb crtc state to link training code (rev3) URL : https://patchwork.freedesktop.org/series/76993/ State : success == Summary == CI Bug Log - changes from CI_DRM_9075_full -> Patchwork_18594_full Summ

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/3] drm/i915/vbt: Fix backlight parsing for VBT 234+

2020-09-30 Thread Patchwork
== Series Details == Series: series starting with [v2,1/3] drm/i915/vbt: Fix backlight parsing for VBT 234+ URL : https://patchwork.freedesktop.org/series/82229/ State : success == Summary == CI Bug Log - changes from CI_DRM_9075_full -> Patchwork_18593_full ==

Re: [Intel-gfx] [PATCH v2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2

2020-09-30 Thread Jani Nikula
On Wed, 30 Sep 2020, Ville Syrjälä wrote: > Now we have an actual difference between EHL and JSL so we > should split. Granted it's a bit annoying to have to do it > just for some vswing tables. Ideally that stuff would be > specified in a sane way by the VBT. But since VBT is generally > useless

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/vbt: Fix backlight parsing for VBT 234+

2020-09-30 Thread Patchwork
== Series Details == Series: series starting with [1/3] drm/i915/vbt: Fix backlight parsing for VBT 234+ URL : https://patchwork.freedesktop.org/series/82227/ State : success == Summary == CI Bug Log - changes from CI_DRM_9075_full -> Patchwork_18592_full =

Re: [Intel-gfx] [PATCH rdma-next v4 4/4] RDMA/umem: Move to allocate SG table from pages

2020-09-30 Thread Jason Gunthorpe
On Wed, Sep 30, 2020 at 12:53:21PM +0300, Leon Romanovsky wrote: > On Tue, Sep 29, 2020 at 04:59:29PM -0300, Jason Gunthorpe wrote: > > On Sun, Sep 27, 2020 at 09:46:47AM +0300, Leon Romanovsky wrote: > > > @@ -296,11 +223,17 @@ static struct ib_umem *__ib_umem_get(struct > > > ib_device *device,

Re: [Intel-gfx] [PATCH rdma-next v4 4/4] RDMA/umem: Move to allocate SG table from pages

2020-09-30 Thread Jason Gunthorpe
On Wed, Sep 30, 2020 at 02:53:58PM +0300, Maor Gottlieb wrote: > > On 9/30/2020 2:45 PM, Jason Gunthorpe wrote: > > On Wed, Sep 30, 2020 at 12:53:21PM +0300, Leon Romanovsky wrote: > > > On Tue, Sep 29, 2020 at 04:59:29PM -0300, Jason Gunthorpe wrote: > > > > On Sun, Sep 27, 2020 at 09:46:47AM +03

Re: [Intel-gfx] [PATCH rdma-next v4 4/4] RDMA/umem: Move to allocate SG table from pages

2020-09-30 Thread Maor Gottlieb
On 9/30/2020 2:45 PM, Jason Gunthorpe wrote: On Wed, Sep 30, 2020 at 12:53:21PM +0300, Leon Romanovsky wrote: On Tue, Sep 29, 2020 at 04:59:29PM -0300, Jason Gunthorpe wrote: On Sun, Sep 27, 2020 at 09:46:47AM +0300, Leon Romanovsky wrote: @@ -296,11 +223,17 @@ static struct ib_umem *__ib_um

Re: [Intel-gfx] [PATCH v2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2

2020-09-30 Thread Jani Nikula
On Tue, 29 Sep 2020, "Souza, Jose" wrote: > On Tue, 2020-09-29 at 23:02 +0300, Ville Syrjälä wrote: >> If the thing has nothing to do PCH then it should not use the PCH type >> for the the check. Instead we should just do the EHL/JSL split. > > In the first version Matt Roper suggested to use PCH

Re: [Intel-gfx] [PULL] topic/gvt-ww-lock

2020-09-30 Thread Maarten Lankhorst
Hey, Op 22-09-2020 om 13:51 schreef Wang, Zhi A: > > Hi, > > Here's the patch which introduces GVT-g ww lock support against > drm-intel-gt-next branch. > > Thanks > > -- > > The following changes since commit 4316b19dee27cc5cd34a95fdbc0a3a5237507701: > >   drm/i915: Fix uninitialised variable i

Re: [Intel-gfx] [PATCH][next] drm/i915: Fix inconsistent IS_ERR and PTR_ERR

2020-09-30 Thread Chris Wilson
Quoting Gustavo A. R. Silva (2020-09-25 16:35:12) > Hi all, > > Friendly ping: who can take this? We had picked up the same patch from Dan Carpenter, thanks. commit 68ba71e3ae6dd86a23486655e33c5f8c9bd90777 Author: Dan Carpenter Date: Fri Sep 11 10:52:43 2020 +0300 drm/i915: Fix an error

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Read DIMM size in Gb rather than GB

2020-09-30 Thread Patchwork
== Series Details == Series: drm/i915: Read DIMM size in Gb rather than GB URL : https://patchwork.freedesktop.org/series/82210/ State : success == Summary == CI Bug Log - changes from CI_DRM_9075_full -> Patchwork_18591_full Summary --

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/edp/jsl: Update vswing table for HBR and HBR2

2020-09-30 Thread Patchwork
== Series Details == Series: drm/i915/edp/jsl: Update vswing table for HBR and HBR2 URL : https://patchwork.freedesktop.org/series/82206/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9075_full -> Patchwork_18590_full Summa

Re: [Intel-gfx] [PATCH v2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2

2020-09-30 Thread Ville Syrjälä
On Tue, Sep 29, 2020 at 04:38:22PM -0700, Matt Roper wrote: > On Wed, Sep 30, 2020 at 12:59:58AM +0300, Ville Syrjälä wrote: > > On Wed, Sep 30, 2020 at 12:11:48AM +0300, Ville Syrjälä wrote: > > > On Tue, Sep 29, 2020 at 02:01:44PM -0700, Matt Roper wrote: > > > > On Tue, Sep 29, 2020 at 11:30:22P

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev4)

2020-09-30 Thread Patchwork
== Series Details == Series: drm/i915: Plumb crtc state to link training code (rev4) URL : https://patchwork.freedesktop.org/series/76993/ State : warning == Summary == $ dim checkpatch origin/drm-tip accbc4f3f980 drm/i915: s/pre_empemph/preemph/ 27807980feec drm/i915: s/old_crtc_state/crtc_st

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Scrub HW state on remove

2020-09-30 Thread Patchwork
== Series Details == Series: drm/i915/gt: Scrub HW state on remove URL : https://patchwork.freedesktop.org/series/82201/ State : success == Summary == CI Bug Log - changes from CI_DRM_9074_full -> Patchwork_18589_full Summary --- **S

[Intel-gfx] [PATCH v3 04/11] drm/i915: Shove the PHY test into the hotplug work

2020-09-30 Thread Ville Syrjala
From: Ville Syrjälä Doing nay kind modeset stuff from the short hpd handler is verboten. The ad-hoc PHY test modeset code violates this. And by calling various link training related functions it's now blocking further work to plumb the crtc state down into the link training code. Let's hack arou

Re: [Intel-gfx] [PATCH rdma-next v4 4/4] RDMA/umem: Move to allocate SG table from pages

2020-09-30 Thread Leon Romanovsky
On Tue, Sep 29, 2020 at 04:59:29PM -0300, Jason Gunthorpe wrote: > On Sun, Sep 27, 2020 at 09:46:47AM +0300, Leon Romanovsky wrote: > > @@ -296,11 +223,17 @@ static struct ib_umem *__ib_umem_get(struct ib_device > > *device, > > goto umem_release; > > > > cur_base +

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Introduce DG1

2020-09-30 Thread Matthew Auld
On 30/09/2020 09:01, Lucas De Marchi wrote: +Matthew Auld On Wed, Sep 30, 2020 at 07:44:25AM +, Patchwork wrote: == Series Details == Series: Introduce DG1 URL   : https://patchwork.freedesktop.org/series/82241/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9077 -> Patch

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/gt: Signal cancelled requests

2020-09-30 Thread Patchwork
== Series Details == Series: series starting with [1/3] drm/i915/gt: Signal cancelled requests URL : https://patchwork.freedesktop.org/series/82189/ State : success == Summary == CI Bug Log - changes from CI_DRM_9073_full -> Patchwork_18588_full

Re: [Intel-gfx] [PATCH v2 04/11] drm/i915: Shove the PHY test into the hotplug work

2020-09-30 Thread kernel test robot
to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Plumb-crtc-state-to-link-training-code/20200930-073629 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: x86_64-randc

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Introduce DG1

2020-09-30 Thread Lucas De Marchi
+Matthew Auld On Wed, Sep 30, 2020 at 07:44:25AM +, Patchwork wrote: == Series Details == Series: Introduce DG1 URL : https://patchwork.freedesktop.org/series/82241/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9077 -> Patchwork_18595 ==

[Intel-gfx] ✗ Fi.CI.BAT: failure for Introduce DG1

2020-09-30 Thread Patchwork
== Series Details == Series: Introduce DG1 URL : https://patchwork.freedesktop.org/series/82241/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9077 -> Patchwork_18595 Summary --- **FAILURE** Serious unknown change

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce DG1

2020-09-30 Thread Patchwork
== Series Details == Series: Introduce DG1 URL : https://patchwork.freedesktop.org/series/82241/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1311:5: war

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1

2020-09-30 Thread Patchwork
== Series Details == Series: Introduce DG1 URL : https://patchwork.freedesktop.org/series/82241/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2ab727864817 drm/i915/dg1: add more PCI ids 02a93e492718 drm/i915/dg1: Initialize RAWCLK properly 90eb98d91e8e drm/i915/dg1: Define MOC