== Series Details ==
Series: HuC Updates (rev2)
URL : https://patchwork.freedesktop.org/series/66504/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6863_full -> Patchwork_14351_full
Summary
---
**FAILURE**
Serious
On 11/09/2019 09:16, Saarinen, Jani wrote:
> Hi,
>
>
>> -Original Message-
>> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
>> Of Matt
>> Roper
>> Sent: keskiviikko 11. syyskuuta 2019 6.43
>> To: intel-gfx@lists.freedesktop.org
>> Subject: Re: [Intel-gfx] ✓
Hi,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Matt
> Roper
> Sent: keskiviikko 11. syyskuuta 2019 6.43
> To: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] ✓ Fi.CI.IGT: success for cdclk consolidation and
> rework
== Series Details ==
Series: drm/i915: Whitelist COMMON_SLICE_CHICKEN2
URL : https://patchwork.freedesktop.org/series/66503/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6863_full -> Patchwork_14350_full
Summary
---
Hi,
On 9/9/19 7:00 PM, Chris Wilson wrote:
Despite the widespread and complete failure of Broadwell integrated
graphics when DMAR is enabled, known over the years, we have never been
able to root cause the issue. Instead, we let the failure undermine our
confidence in the iommu system itself whe
== Series Details ==
Series: drm/i915/guc: Enable guc logging on guc log relay write
URL : https://patchwork.freedesktop.org/series/66502/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6863_full -> Patchwork_14349_full
Summ
On Tue, Sep 10, 2019 at 11:55:40PM +, Patchwork wrote:
> == Series Details ==
>
> Series: cdclk consolidation and rework for BXT-TGL (rev6)
> URL : https://patchwork.freedesktop.org/series/66365/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6861_full -> Patchwor
== Series Details ==
Series: drm/i915: Make shrink/unshrink be atomic
URL : https://patchwork.freedesktop.org/series/66501/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6862_full -> Patchwork_14347_full
Summary
---
== Series Details ==
Series: drm/i915: Whitelist COMMON_SLICE_CHICKEN2 (rev2)
URL : https://patchwork.freedesktop.org/series/66503/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6863 -> Patchwork_14352
Summary
---
**
This allows userspace to use "legacy" mode for push constants, where
they are committed at 3DPRIMITIVE or flush time, rather than being
committed at 3DSTATE_BINDING_TABLE_POINTERS_XS time. Gen6-8 and Gen11
both use the "legacy" behavior - only Gen9 works in the "new" way.
Conflating push constant
On 9/10/19 3:46 PM, Robert M. Fosha wrote:
Creating and opening the GuC log relay file enables and starts
the relay potentially before the caller is ready to consume logs.
Change the behavior so that relay starts only on an explicit call
to the write function (with a value of '1'). Other values
== Series Details ==
Series: drm/i915/tgl: Disable rc6 for debugging (rev2)
URL : https://patchwork.freedesktop.org/series/66492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6861_full -> Patchwork_14346_full
Summary
-
== Series Details ==
Series: HuC Updates (rev2)
URL : https://patchwork.freedesktop.org/series/66504/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6863 -> Patchwork_14351
Summary
---
**SUCCESS**
No regressions fo
== Series Details ==
Series: HuC Updates (rev2)
URL : https://patchwork.freedesktop.org/series/66504/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d870e2a94ef8 drm/i915/uc: Update GuC and HuC firmware naming convention
9b0da66fbfad HAX: force enable_guc=2
-:7: WARNING:COMMIT_M
== Series Details ==
Series: drm/i915: Whitelist COMMON_SLICE_CHICKEN2
URL : https://patchwork.freedesktop.org/series/66503/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6863 -> Patchwork_14350
Summary
---
**SUCCESS
== Series Details ==
Series: cdclk consolidation and rework for BXT-TGL (rev6)
URL : https://patchwork.freedesktop.org/series/66365/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6861_full -> Patchwork_14345_full
Summary
--
== Series Details ==
Series: drm/i915: Whitelist COMMON_SLICE_CHICKEN2
URL : https://patchwork.freedesktop.org/series/66503/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
31adb9f5fd42 drm/i915: Whitelist COMMON_SLICE_CHICKEN2
-:29: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by:
== Series Details ==
Series: drm/i915/guc: Enable guc logging on guc log relay write
URL : https://patchwork.freedesktop.org/series/66502/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6863 -> Patchwork_14349
Summary
--
== Series Details ==
Series: Few loose end intel_gt cleanups
URL : https://patchwork.freedesktop.org/series/66490/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6861_full -> Patchwork_14342_full
Summary
---
**SUCCESS
Make both GuC and HuC to use "." as the separator. Hardcode
the separator in MAKE_UC_FW_PATH. Remove the usage of "ver" from HuC.
The current convention being:
_uc_..patch.bin
Update the versions of HuC being loaded of the platforms.
SKL - v2.0.0
BXT - v2.0.0
KBL - v4.0.0
GLK - v4.0.0
CFL - KBL
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b
The following changes since commit 6c6918ad8ae0dfb2cb591484eba525409980c16f:
linux-firmware: Update firmware file for Intel Bluetooth AX201 (2019-09-09
04:22:42 -0400)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware ehl_huc
for you to fetch changes up
Creating and opening the GuC log relay file enables and starts
the relay potentially before the caller is ready to consume logs.
Change the behavior so that relay starts only on an explicit call
to the write function (with a value of '1'). Other values flush
the log relay as before.
Cc: Matthew Br
This allows userspace to use "legacy" mode for push constants, where
they are committed at 3DPRIMITIVE or flush time, rather than being
committed at 3DSTATE_BINDING_TABLE_POINTERS_XS time. Gen6-8 and Gen11
both use the "legacy" behavior - only Gen9 works in the "new" way.
Conflating push constant
== Series Details ==
Series: drm/i915: Make shrink/unshrink be atomic
URL : https://patchwork.freedesktop.org/series/66501/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6862 -> Patchwork_14347
Summary
---
**SUCCESS*
== Series Details ==
Series: series starting with drm/i915: Force compilation with intel-iommu for
CI validation (rev2)
URL : https://patchwork.freedesktop.org/series/66487/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6861_full -> Patchwork_14341_full
==
== Series Details ==
Series: drm/ttm: make ttm bo a gem bo subclass (rev5)
URL : https://patchwork.freedesktop.org/series/64701/
State : failure
== Summary ==
Applying: drm/ttm: add gem base object
Using index info to reconstruct a base tree...
M include/drm/ttm/ttm_bo_api.h
Falling back
On Sat, Sep 07, 2019 at 12:21:11AM -0700, Dhinakaran Pandiyan wrote:
> Gen-12 display decompression operates on Y-tiled compressed main surface.
> The CCS is linear and has 4 bits of metadata for each main surface cache
> line pair, a size ratio of 1:256. Gen-12 display decompression is
> incompati
On Sat, Sep 07, 2019 at 09:58:46PM -0400, Ilia Mirkin wrote:
> On Wed, Aug 21, 2019 at 7:55 AM Thierry Reding
> wrote:
> >
> > On Wed, Aug 21, 2019 at 04:33:58PM +1000, Ben Skeggs wrote:
> > > On Wed, 14 Aug 2019 at 20:14, Gerd Hoffmann wrote:
> > > >
> > > > Hi,
> > > >
> > > > > > Changing t
On 9/10/19 2:35 PM, Srivatsa, Anusha wrote:
-Original Message-
From: Ceraolo Spurio, Daniele
Sent: Tuesday, September 10, 2019 2:05 PM
To: Srivatsa, Anusha ; intel-
g...@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915/uc: Update MAKE_HUC_FW_PATH macro
On 9/9/19 12:28 PM, A
> -Original Message-
> From: Ceraolo Spurio, Daniele
> Sent: Tuesday, September 10, 2019 2:05 PM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [PATCH 1/2] drm/i915/uc: Update MAKE_HUC_FW_PATH macro
>
>
>
> On 9/9/19 12:28 PM, Anusha Srivatsa wrote:
> > Upd
On Tue, Sep 10, 2019 at 12:20:05PM +0300, Jani Nikula wrote:
> On Mon, 09 Sep 2019, Manasi Navare wrote:
> > On Thu, Sep 05, 2019 at 11:03:12AM +0530, Nautiyal, Ankit K wrote:
> >> Hi,
> >>
> >> I was able to get 5K HPz27q 317b monitor for some time. Below are the
> >> observation on HPz27q Monit
On Mon, 2019-09-09 at 15:35 -0700, Rodrigo Vivi wrote:
> On Mon, Sep 09, 2019 at 02:54:59PM -0700, Vetter, Daniel wrote:
> > On Mon, 2019-09-09 at 10:24 -0700, Rodrigo Vivi wrote:
> > > Hi guys,
> > >
> > > On Fri, Sep 06, 2019 at 01:42:55PM +0800, Zhenyu Wang wrote:
> > > > Hi,
> > > >
> > > > H
Add an atomic counter and always take the spinlock around the pin/unpin
events, so that we can perform the list manipulation concurrently.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 3 +-
.../gpu/drm/i915/gem/i915_gem_object_types.
On 9/9/19 11:06 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-09-10 01:59:38)
On 9/9/19 3:55 PM, Chris Wilson wrote:
Unwedging the GPU requires a successful GPU reset before we restore the
default submission, or else we may see residual context switch events
that we were not
On Tue, Sep 10, 2019 at 11:07:30AM -0700, Manasi Navare wrote:
> On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote:
> > On Sun, 08 Sep 2019, Manasi Navare wrote:
> > > This patch series addresses all review comments and now the enable and
> > > disable paths follow the method of obtainin
On 9/9/19 12:28 PM, Anusha Srivatsa wrote:
Update MAKE_HUC_FW_PATH macro to follow the same convention
as the MAKE_GUC_FW_PATH with the separator changing from "_" to "."
and removing "ver".
The current convention being:
_uc_..patch.bin
Update the versions of huc being loaded of the platforms
== Series Details ==
Series: drm/i915: Use a high priority wq for nonblocking plane updates
URL : https://patchwork.freedesktop.org/series/66485/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6860_full -> Patchwork_14340_full
===
Quoting Matthew Auld (2019-09-10 20:56:48)
> On Tue, 10 Sep 2019 at 17:17, Chris Wilson wrote:
> >
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=111593
> > Signed-off-by: Chris Wilson
> > Cc: Mika Kuoppala
> Acked-by: Matthew Auld
Filled in the blurb and pushed. Let's see how th
On Mon, 2 Sep 2019 at 05:03, Chris Wilson wrote:
>
> As we remove the struct_mutex protection from around the vma pinning,
> counters need to be atomic and aware that there may be multiple threads
> simultaneously active.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
On Mon, 2 Sep 2019 at 05:03, Chris Wilson wrote:
>
> In preparation for reducing struct_mutex stranglehold around the vm,
> make the vma.flags atomic so that we can acquire a pin on the vma
> atomically before deciding if we need to take the mutex.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mat
On Tue, 10 Sep 2019 at 17:17, Chris Wilson wrote:
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=111593
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Acked-by: Matthew Auld
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
h
On Mon, 2 Sep 2019 at 05:03, Chris Wilson wrote:
>
> Add an atomic counter and always take the spinlock around the pin/unpin
> events, so that we can perform the list manipulation concurrently.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
Quoting Patchwork (2019-09-10 18:24:49)
> * igt@i915_selftest@live_gem_contexts:
> - {fi-tgl-u}: NOTRUN -> [DMESG-FAIL][3]
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14346/fi-tgl-u/igt@i915_selftest@live_gem_contexts.html
Doesn't that look familiar. Same breakage
== Series Details ==
Series: drm/i915/selftests: Tighten the timeout testing for partial mmaps
URL : https://patchwork.freedesktop.org/series/66484/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6860_full -> Patchwork_14339_full
Quoting Patchwork (2019-09-10 18:24:49)
> == Series Details ==
>
> Series: drm/i915/tgl: Disable rc6 for debugging (rev2)
> URL : https://patchwork.freedesktop.org/series/66492/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6861 -> Patchwork_14346
> =
On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote:
> On Sun, 08 Sep 2019, Manasi Navare wrote:
> > This patch series addresses all review comments and now the enable and
> > disable paths follow the method of obtaining slave states from master
> > and updating master-slaves in correct or
== Series Details ==
Series: drm/i915/tgl: Keep forcewake always for now
URL : https://patchwork.freedesktop.org/series/66483/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6860_full -> Patchwork_14338_full
Summary
---
Looks good. The struct perf inside drm_i915_private could also move to
i915_perf_types.h. Irrespective of that,
Reviewed-by: Umesh Nerlige Ramappa
Regards,
Umesh
On Mon, Sep 09, 2019 at 12:31:09PM +0300, Lionel Landwerlin wrote:
Following a pattern used throughout the driver.
Signed-off-by:
== Series Details ==
Series: drm/i915/tgl: Disable rc6 for debugging (rev2)
URL : https://patchwork.freedesktop.org/series/66492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6861 -> Patchwork_14346
Summary
---
**SU
== Series Details ==
Series: drm: two planes with the same zpos have undefined ordering
URL : https://patchwork.freedesktop.org/series/66480/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6860_full -> Patchwork_14337_full
S
Minor comment below. With or without it,
Reviewed-by: Umesh Nerlige Ramappa
Regards,
Umesh
On Mon, Sep 09, 2019 at 12:31:06PM +0300, Lionel Landwerlin wrote:
At some point in time there was the idea that we could have multiple
stream from the same piece of HW but that never materialized and
== Series Details ==
Series: cdclk consolidation and rework for BXT-TGL (rev6)
URL : https://patchwork.freedesktop.org/series/66365/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6861 -> Patchwork_14345
Summary
---
*
== Series Details ==
Series: cdclk consolidation and rework for BXT-TGL (rev5)
URL : https://patchwork.freedesktop.org/series/66365/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6861 -> Patchwork_14344
Summary
---
*
== Series Details ==
Series: cdclk consolidation and rework for BXT-TGL (rev6)
URL : https://patchwork.freedesktop.org/series/66365/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c43a4d52b847 drm/i915: Consolidate bxt/cnl/icl cdclk readout
-:81: CHECK:CAMELCASE: Avoid CamelCase
References: https://bugs.freedesktop.org/show_bug.cgi?id=111593
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_pm.c | 3 +--
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drive
The bspec lays out legal cdclk frequencies, PLL ratios, and CD2X
dividers in an easy-to-read table for most recent platforms. We've been
translating the data from that table into platform-specific code logic,
but it's easy to overlook an area we need to update when adding new
cdclk values or enabl
On Tue, Sep 10, 2019 at 9:21 AM Ilia Mirkin wrote:
>
> On Tue, Sep 10, 2019 at 3:34 AM Mun, Gwan-gyeong
> wrote:
> >
> > On Sat, 2019-09-07 at 21:43 -0400, Ilia Mirkin wrote:
> > > On Sat, Sep 7, 2019 at 7:20 PM Mun, Gwan-gyeong
> > > wrote:
> > > > On Fri, 2019-09-06 at 09:24 -0400, Ilia Mirkin
Quoting Patchwork (2019-09-10 17:06:36)
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14343/
>
> Known issues
>
>
> Here are the changes found in Patchwork_14343 that come from known issues:
tgl died in gem_exec_gttfill, so not rc6, or even runtime-pm, by it
== Series Details ==
Series: cdclk consolidation and rework for BXT-TGL (rev5)
URL : https://patchwork.freedesktop.org/series/66365/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c7ffbe99a9da drm/i915: Consolidate bxt/cnl/icl cdclk readout
-:81: CHECK:CAMELCASE: Avoid CamelCase
On Tue, Sep 10, 2019 at 08:42:46AM -0700, Matt Roper wrote:
...
> +struct intel_cdclk_vals {
> + u32 refclk;
Oh, I think (at least currently) refclk would fit into u16,
so we could pack this a bit tighter still.
> + u32 cdclk;
> + u8 divider; /* CD2X divider * 2 */
> + u8 rat
== Series Details ==
Series: drm/i915/tgl: Disable rc6 for debugging
URL : https://patchwork.freedesktop.org/series/66492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6861 -> Patchwork_14343
Summary
---
**SUCCESS**
Aside from a few minor register changes and some different clock values,
cdclk design hasn't changed much since gen9lp. Let's consolidate the
handlers for bxt, cnl, and icl to keep the codeflow consistent.
Also, while we're at it, s/bxt_de_pll_update/bxt_de_pll_readout/ since
"update" makes me th
On Tue, Sep 10, 2019 at 08:42:46AM -0700, Matt Roper wrote:
> The bspec lays out legal cdclk frequencies, PLL ratios, and CD2X
> dividers in an easy-to-read table for most recent platforms. We've been
> translating the data from that table into platform-specific code logic,
> but it's easy to over
On Tue, Sep 10, 2019 at 08:42:45AM -0700, Matt Roper wrote:
> Aside from a few minor register changes and some different clock values,
> cdclk design hasn't changed much since gen9lp. Let's consolidate the
> handlers for bxt, cnl, and icl to keep the codeflow consistent.
>
> Also, while we're at
The BXT and CNL functions were already basically identical, whereas
ICL's function tried to do its own sanitization rather than calling
bxt_sanitize_cdclk.
This should actually fix a bug in our ICL initialization where it would
consider the /2 CD2X divider invalid and force an unnecessary
sanitiza
When reading out the BIOS-programmed cdclk state, let's make sure that
the cdclk value is on the valid list for the platform, ensure that the
VCO matches the cdclk, and ensure that the CD2X divider was set
properly.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
dri
The CNL variant of this function is identical to the BXT variant aside
from not needing to handle SSA precharge.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 46 +-
1 file changed, 2 insertions(+), 4
We'd previously combined ICL/TGL logic into the cnl_set_cdclk function,
but BXT is pretty similar as well. Roll the cnl/icl/tgl logic back into
the bxt function; the only things we really need to handle separately
are punit notification and calling different functions to enable/disable
the cdclk P
The bspec lays out legal cdclk frequencies, PLL ratios, and CD2X
dividers in an easy-to-read table for most recent platforms. We've been
translating the data from that table into platform-specific code logic,
but it's easy to overlook an area we need to update when adding new
cdclk values or enabl
Aside from a few minor register changes and some different clock values,
cdclk design hasn't changed much since gen9lp. Let's consolidate the
handlers for bxt, cnl, and icl to keep the codeflow consistent.
Also, while we're at it, s/bxt_de_pll_update/bxt_de_pll_readout/ since
"update" makes me th
With all of the cdclk function consolidation, we can cut down on a lot
of platform if/else logic by creating a vfunc that's initialized at
startup.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 75 --
The uninitialize flow is the same on all of these platforms, aside from
calculating a different frequency level.
v2: Reverse platform conditional order for consistency. (Ville)
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk
Previous version of the series was here:
https://lists.freedesktop.org/archives/intel-gfx/2019-September/211853.html
This version incorporates Ville's comments, most of which are on the
second patch where we introduce the cdclk tables. The structure and
parsing of the tables is now done in a
References: https://bugs.freedesktop.org/show_bug.cgi?id=111593
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index fbe98a2db88e..b3cc8560696b
== Series Details ==
Series: Few loose end intel_gt cleanups
URL : https://patchwork.freedesktop.org/series/66490/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6861 -> Patchwork_14342
Summary
---
**SUCCESS**
No r
Quoting Tvrtko Ursulin (2019-09-10 15:38:23)
> From: Tvrtko Ursulin
>
> These notifications operate on intel_gt so make the code take what it
> needs.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Andi Shyti
> Cc: Chris Wilson
Soon the blocking_notifier will be relieved of duty...
I think it migh
== Series Details ==
Series: series starting with drm/i915: Force compilation with intel-iommu for
CI validation (rev2)
URL : https://patchwork.freedesktop.org/series/66487/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6861 -> Patchwork_14341
Quoting Tvrtko Ursulin (2019-09-10 15:38:22)
> From: Tvrtko Ursulin
>
> Both in the container_of and getting to gt->awake there is no need to go
> via i915 since both the wakeref and awake are members of gt.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Andi Shyti
> Cc: Chris Wilson
Have same chun
Quoting Tvrtko Ursulin (2019-09-10 15:38:21)
> From: Tvrtko Ursulin
>
> Timelines live in struct intel_gt so make wait_for_timelines take
> exactly what it needs.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Andi Shyti
> Cc: Chris Wilson
I've deleted this code, fwiw, merged it with request manage
Quoting Tvrtko Ursulin (2019-09-10 15:38:20)
> From: Tvrtko Ursulin
>
> Code in i915_gem_init_hw is all about GT init so move it to intel_gt.c
> renaming to intel_gt_init_hw.
>
> Existing intel_gt_init_hw is renamed to intel_gt_init_hw_early since it
> is currently called from driver probe.
>
>
== Series Details ==
Series: Few loose end intel_gt cleanups
URL : https://patchwork.freedesktop.org/series/66490/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4144570a45a2 drm/i915: Move GT init to intel_gt.c
-:89: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN
From: Tvrtko Ursulin
A few patches left hanging since late July. First one old in spirit but adjusted
and renamed and the rest update for latest drm-tip.
Happy to receive thoughts on whether this cleanup makes sense.
Cc: Andi Shyti
Cc: Chris Wilson
Tvrtko Ursulin (4):
drm/i915: Move GT ini
From: Tvrtko Ursulin
These notifications operate on intel_gt so make the code take what it
needs.
Signed-off-by: Tvrtko Ursulin
Cc: Andi Shyti
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/dr
From: Tvrtko Ursulin
Both in the container_of and getting to gt->awake there is no need to go
via i915 since both the wakeref and awake are members of gt.
Signed-off-by: Tvrtko Ursulin
Cc: Andi Shyti
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 6 +++---
1 file changed, 3 ins
From: Tvrtko Ursulin
Code in i915_gem_init_hw is all about GT init so move it to intel_gt.c
renaming to intel_gt_init_hw.
Existing intel_gt_init_hw is renamed to intel_gt_init_hw_early since it
is currently called from driver probe.
Signed-off-by: Tvrtko Ursulin
Cc: Andi Shyti
Cc: Chris Wilso
From: Tvrtko Ursulin
Timelines live in struct intel_gt so make wait_for_timelines take
exactly what it needs.
Signed-off-by: Tvrtko Ursulin
Cc: Andi Shyti
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/driv
== Series Details ==
Series: series starting with drm/i915: Force compilation with intel-iommu for
CI validation (rev2)
URL : https://patchwork.freedesktop.org/series/66487/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f0df04b62a3b drm/i915: Force compilation with intel-iommu
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Kconfig.debug | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug
b/drivers/gpu/drm/i915/Kconfig.debug
index 00786a142ff0..c5c00cad6ba1 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu
On Fri, Aug 09, 2019 at 01:53:43PM +0100, Chris Wilson wrote:
> Quoting Martin Wilck (2019-08-09 13:41:42)
> > This happened to me today, running kernel 5.3.0-rc3-1.g571863b-default
> > (5.3-rc3 with just a few patches on top), after starting a KVM virtual
> > machine. The X screen was frozen. Remo
== Series Details ==
Series: drm/i915: Use a high priority wq for nonblocking plane updates
URL : https://patchwork.freedesktop.org/series/66485/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6860 -> Patchwork_14340
Summary
== Series Details ==
Series: drm/i915/execlists: Clear STOP_RING bit on reset (rev2)
URL : https://patchwork.freedesktop.org/series/66473/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6857_full -> Patchwork_14336_full
Summ
Despite the widespread and complete failure of Broadwell integrated
graphics when DMAR is enabled, known over the years, we have never been
able to root cause the issue. Instead, we let the failure undermine our
confidence in the iommu system itself when we should be pushing for it to
be always ena
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Kconfig.debug | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug
b/drivers/gpu/drm/i915/Kconfig.debug
index 00786a142ff0..06709dd6a2e0 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/
---
drivers/iommu/intel-iommu.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 34f6a3d93ae2..c98cdfd91691 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -439,8 +439,6 @@ static int __init intel_iom
Quoting Mika Kuoppala (2019-09-10 12:35:47)
> Forcewake handling is a prime suspect now. Keep ref
> always on tgl to test the theory and reveal the coverage.
>
> Testcase: igt/gem_sync
> Cc: Chris Wilson
> Suggested-by: Chris Wilson
> Signed-off-by: Mika Kuoppala
Gets us as far as reload, befo
== Series Details ==
Series: drm/i915/selftests: Tighten the timeout testing for partial mmaps
URL : https://patchwork.freedesktop.org/series/66484/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6860 -> Patchwork_14339
Summ
On Tue, Sep 10, 2019 at 3:34 AM Mun, Gwan-gyeong
wrote:
>
> On Sat, 2019-09-07 at 21:43 -0400, Ilia Mirkin wrote:
> > On Sat, Sep 7, 2019 at 7:20 PM Mun, Gwan-gyeong
> > wrote:
> > > On Fri, 2019-09-06 at 09:24 -0400, Ilia Mirkin wrote:
> > > > On Fri, Sep 6, 2019 at 7:43 AM Ville Syrjälä
> > > >
== Series Details ==
Series: drm/i915/selftests: Tighten the timeout testing for partial mmaps
URL : https://patchwork.freedesktop.org/series/66484/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8b28c802b06b drm/i915/selftests: Tighten the timeout testing for partial mmaps
-:27
On Sat, Sep 07, 2019 at 09:05:00PM -0700, Matt Roper wrote:
> The bspec lays out legal cdclk frequencies, PLL ratios, and CD2X
> dividers in an easy-to-read table for most recent platforms. We've been
> translating the data from that table into platform-specific code logic,
> but it's easy to over
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