== Series Details ==
Series: HuC updates (rev3)
URL : https://patchwork.freedesktop.org/series/66361/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6854_full -> Patchwork_14333_full
Summary
---
**SUCCESS**
No regr
== Series Details ==
Series: drm/i915: include GTT page-size info in error state
URL : https://patchwork.freedesktop.org/series/66450/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6854_full -> Patchwork_14332_full
Summary
Quoting Daniele Ceraolo Spurio (2019-09-10 01:59:38)
>
>
> On 9/9/19 3:55 PM, Chris Wilson wrote:
> > Unwedging the GPU requires a successful GPU reset before we restore the
> > default submission, or else we may see residual context switch events
> > that we were not expecting.
> >
> > Reported
On Fri, 2019-09-06 at 19:13 +0100, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-09-02 14:42:44)
> >
> > On 24/07/2019 14:05, Tvrtko Ursulin wrote:
> > >
> > > On 23/07/2019 16:49, Stuart Summers wrote:
> > > > +u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu,
> > > > u8 slice)
== Series Details ==
Series: drm/i915/display: Mark the modesetting wq as WQ_HIGHPRI
URL : https://patchwork.freedesktop.org/series/66439/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6854_full -> Patchwork_14330_full
Summ
> -Original Message-
> From: Manna, Animesh
> Sent: Monday, September 9, 2019 10:27 PM
> To: Sharma, Shashank ; intel-
> g...@lists.freedesktop.org
> Cc: Thierry, Michel ; Nikula, Jani
> ;
> Vivi, Rodrigo
> Subject: Re: [PATCH v5 05/11] drm/i915/dsb: Check DSB engine status.
>
>
>
>
== Series Details ==
Series: series starting with [1/3] drm/i915: export color_differs
URL : https://patchwork.freedesktop.org/series/66433/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6854_full -> Patchwork_14329_full
Su
On 2019.09.09 15:35:10 -0700, Rodrigo Vivi wrote:
> On Mon, Sep 09, 2019 at 02:54:59PM -0700, Vetter, Daniel wrote:
> > On Mon, 2019-09-09 at 10:24 -0700, Rodrigo Vivi wrote:
> > > Hi guys,
> > >
> > > On Fri, Sep 06, 2019 at 01:42:55PM +0800, Zhenyu Wang wrote:
> > > > Hi,
> > > >
> > > > Here's
== Series Details ==
Series: adding gamma state checker for CHV and i965 (rev2)
URL : https://patchwork.freedesktop.org/series/66297/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6854_full -> Patchwork_14328_full
Summary
-
== Series Details ==
Series: drm/i915/ringbuffer: Flush writes before RING_TAIL update
URL : https://patchwork.freedesktop.org/series/66426/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6854_full -> Patchwork_14327_full
Su
On 9/9/19 3:55 PM, Chris Wilson wrote:
Unwedging the GPU requires a successful GPU reset before we restore the
default submission, or else we may see residual context switch events
that we were not expecting.
Reported-by: Janusz Krzysztofik
Signed-off-by: Chris Wilson
Cc: Janusz Krzysztofik
Reviewed-by: Umesh Nerlige Ramappa
Regards,
Umesh
On Mon, Sep 09, 2019 at 12:31:07PM +0300, Lionel Landwerlin wrote:
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i91
== Series Details ==
Series: drm/i915/tgl: Implement Wa_1409142259 (rev2)
URL : https://patchwork.freedesktop.org/series/66364/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6855 -> Patchwork_14335
Summary
---
**SUCC
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Allow clobbering gpu resets if
the display is off
URL : https://patchwork.freedesktop.org/series/66459/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6855 -> Patchwork_14334
=
Disable CPS aware color pipe by setting chicken bit.
BSpec: 52890
HSDES: 1409142259
v2: Move WA to ctx WA's(Daniele)
Cc: Daniele Ceraolo Spurio
Cc: Stuart Summers
Cc: Matt Roper
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
drivers/gpu/drm/i915
If the display is inactive, we need not worry about the gpu reset
clobbering the display!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_reset.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/
Unwedging the GPU requires a successful GPU reset before we restore the
default submission, or else we may see residual context switch events
that we were not expecting.
Reported-by: Janusz Krzysztofik
Signed-off-by: Chris Wilson
Cc: Janusz Krzysztofik
Cc: Daniele Ceraolo Spurio
---
drivers/g
On 10/09/2019 00:06, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-09-09 10:31:05)
v9: After explanations on
https://lists.freedesktop.org/archives/dri-devel/2019-August/229287.html
drop the ordering check from v8 (Lionel)
Designing an interface to be antirobust. Userspace shoot
On Mon, Sep 09, 2019 at 02:54:59PM -0700, Vetter, Daniel wrote:
> On Mon, 2019-09-09 at 10:24 -0700, Rodrigo Vivi wrote:
> > Hi guys,
> >
> > On Fri, Sep 06, 2019 at 01:42:55PM +0800, Zhenyu Wang wrote:
> > > Hi,
> > >
> > > Here's gvt-next-fixes with two recent fixes, one for recent
> > > guest
On Mon, Sep 09, 2019 at 02:50:20PM +0300, Joonas Lahtinen wrote:
> Quoting Prathap Kumar Valsan (2019-08-26 01:48:01)
> > To provide shared last-level-cache isolation to cpu workloads running
> > concurrently with gpu workloads, the gpu allocation of cache lines needs
> > to be restricted to certai
On Mon, 2019-09-09 at 10:24 -0700, Rodrigo Vivi wrote:
> Hi guys,
>
> On Fri, Sep 06, 2019 at 01:42:55PM +0800, Zhenyu Wang wrote:
> > Hi,
> >
> > Here's gvt-next-fixes with two recent fixes, one for recent
> > guest hang regression and another for guest reset fix.
> >
> > Thanks.
> > --
> > The
Quoting Chris Wilson (2019-09-07 09:39:52)
> Quoting Daniele Ceraolo Spurio (2019-09-06 23:28:05)
> >
> >
> > On 9/5/19 2:09 AM, Janusz Krzysztofik wrote:
> > > When trying to reset a device with reset capability disabled or not
> > > supported while rings are full of requests, it has been observ
Quoting Daniele Ceraolo Spurio (2019-09-09 17:27:47)
>
>
> On 9/7/19 1:39 AM, Chris Wilson wrote:
> > Quoting Daniele Ceraolo Spurio (2019-09-06 23:28:05)
> >>
> >>
> >> On 9/5/19 2:09 AM, Janusz Krzysztofik wrote:
> >>> When trying to reset a device with reset capability disabled or not
> >>> su
== Series Details ==
Series: HuC updates (rev3)
URL : https://patchwork.freedesktop.org/series/66361/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6854 -> Patchwork_14333
Summary
---
**SUCCESS**
No regressions fo
== Series Details ==
Series: drm/i915: include GTT page-size info in error state
URL : https://patchwork.freedesktop.org/series/66450/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6854 -> Patchwork_14332
Summary
---
Quoting Lionel Landwerlin (2019-09-09 10:31:05)
> v9: After explanations on
> https://lists.freedesktop.org/archives/dri-devel/2019-August/229287.html
> drop the ordering check from v8 (Lionel)
Designing an interface to be antirobust. Userspace shooting itself in
the foot is fine; userspac
== Series Details ==
Series: HuC updates (rev3)
URL : https://patchwork.freedesktop.org/series/66361/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3e2f37ffcdcc drm/i915/uc: Update MAKE_HUC_FW_PATH macro
81ceadb0ec8e HAX: force enable_guc=2
-:7: WARNING:COMMIT_MESSAGE: Missing
== Series Details ==
Series: Remaining patches to enable Transcoder Port Sync for tiled displays
(rev3)
URL : https://patchwork.freedesktop.org/series/66403/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6854 -> Patchwork_14331
/commits/Chris-Wilson/drm-i915-selftests-Take-runtime-wakeref-for-igt_ggtt_lowlevel/20190909-201355
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a004-201936 (attached as .config)
compiler: gcc-5 (Ubuntu 5.5.0-12ubuntu1) 5.5.0 20171010
reproduce
== Series Details ==
Series: Remaining patches to enable Transcoder Port Sync for tiled displays
(rev3)
URL : https://patchwork.freedesktop.org/series/66403/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
___
Intel
== Series Details ==
Series: drm/i915/display: Mark the modesetting wq as WQ_HIGHPRI
URL : https://patchwork.freedesktop.org/series/66439/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6854 -> Patchwork_14330
Summary
--
Update MAKE_HUC_FW_PATH macro to follow the same convention
as the MAKE_GUC_FW_PATH with the separator changing from "_" to "."
and removing "ver".
The current convention being:
_uc_..patch.bin
Update the versions of huc being loaded of the platforms.
SKL - v2.0.0
BXT - v2.0.0
KBL - v4.0.0
GLK -
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b
linux-firmware: Update firmware file for Intel Bluetooth AX201 (2019-09-09
04:22:42 -0400)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware ehl_huc
for you to fetch changes up to 44a6d7e577ca3df16d804c560de16cb8483c4306:
i915: Add HuC firmware v9.0.0
Quoting Matthew Auld (2019-09-09 18:16:46)
> It might prove useful in the future to know if the vma is utilising
> huge-GTT-pages. Related to this is the GTT cache, where there is some HW
> "quirkiness" where it must be disabled if using 2M pages, so include
> that for good measure.
>
> Suggested-
== Series Details ==
Series: series starting with [1/2] drm/i915: Show the logical context ring
state on dumping
URL : https://patchwork.freedesktop.org/series/66422/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6853_full -> Patchwork_14323_full
=
== Series Details ==
Series: series starting with [1/3] drm/i915: export color_differs
URL : https://patchwork.freedesktop.org/series/66433/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6854 -> Patchwork_14329
Summary
On Thu, Sep 05, 2019 at 11:03:12AM +0530, Nautiyal, Ankit K wrote:
> Hi,
>
> I was able to get 5K HPz27q 317b monitor for some time. Below are the
> observation on HPz27q Monitor with two DP cables connected to a KBL machine.
>
> *General Observation*
> The monitor settings has two modes,
Searching on the kernel warnings and errors didn't bring it up, but in browsing
bugzilla I stumbled on this.
Bug 111501 - [CFL] Kernel 5.3.0-rc6: i915 fails at typec_displayport 5120x1440
https://bugs.freedesktop.org/show_bug.cgi?id=111501
It's the same monitor and connection type.
Is the rela
== Series Details ==
Series: adding gamma state checker for CHV and i965 (rev2)
URL : https://patchwork.freedesktop.org/series/66297/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6854 -> Patchwork_14328
Summary
---
== Series Details ==
Series: adding gamma state checker for CHV and i965 (rev2)
URL : https://patchwork.freedesktop.org/series/66297/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d02e018c92fe drm/i915/display: Add gamma precision function for CHV
73751624de48 drm/i915/display:
== Series Details ==
Series: drm/i915/ringbuffer: Flush writes before RING_TAIL update
URL : https://patchwork.freedesktop.org/series/66426/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6854 -> Patchwork_14327
Summary
Hi guys,
On Fri, Sep 06, 2019 at 01:42:55PM +0800, Zhenyu Wang wrote:
>
> Hi,
>
> Here's gvt-next-fixes with two recent fixes, one for recent
> guest hang regression and another for guest reset fix.
>
> Thanks.
> --
> The following changes since commit c36beba6b296b3c05a0f29753b04775e5ae23886:
It might prove useful in the future to know if the vma is utilising
huge-GTT-pages. Related to this is the GTT cache, where there is some HW
"quirkiness" where it must be disabled if using 2M pages, so include
that for good measure.
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Chri
Hello,
5.2.13 is working fine (great) still with a Dell U4919DW connected via USB-C
from a X1 Carbon Gen 6.
5.3-rc8 so far is not (blank screen) and errors:
https://pastebin.com/tXFi6AfK
Seems there has been some refactoring for just this kind of connection in 5.3?
Is there perhaps and issue
On 9/9/2019 6:51 PM, Sharma, Shashank wrote:
On 9/7/2019 4:37 PM, Animesh Manna wrote:
The lifetime of command buffer can be controlled by the dsb user
throuh refcount. Added refcount mechanism is dsb get/put call
which create/destroy dsb context.
Cc: Jani Nikula
Cc: Shashank Sharma
Signed
On 9/9/2019 6:43 PM, Sharma, Shashank wrote:
On 9/7/2019 4:37 PM, Animesh Manna wrote:
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-o
On 9/9/2019 6:28 PM, Sharma, Shashank wrote:
On 9/7/2019 4:37 PM, Animesh Manna wrote:
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the sam
On 9/9/2019 6:26 PM, Sharma, Shashank wrote:
On 9/7/2019 4:37 PM, Animesh Manna wrote:
+void intel_dsb_put(struct intel_dsb *dsb)
+{
+struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+if (!dsb)
+re
== Series Details ==
Series: series starting with [1/6] drm/i915/selftests: Take runtime wakeref for
igt_ggtt_lowlevel
URL : https://patchwork.freedesktop.org/series/66425/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6854 -> Patchwork_14326
=
/commits/Chris-Wilson/drm-i915-selftests-Take-runtime-wakeref-for-igt_ggtt_lowlevel/20190909-201355
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-s2-201936 (attached as .config)
compiler: gcc-7 (Debian 7.4.0-11) 7.4.0
reproduce:
# save the attached
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: add INTEL_NUM_PIPES() and use
it (rev2)
URL : https://patchwork.freedesktop.org/series/66281/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6854 -> Patchwork_14325
===
On 9/6/19 6:10 PM, Matt Roper wrote:
On Fri, Sep 06, 2019 at 03:46:42PM -0700, Daniele Ceraolo Spurio wrote:
On 9/6/19 3:41 PM, Radhakrishna Sripada wrote:
Disable CPS aware color pipe by setting chicken bit.
BSpec: 52890
HSDES: 1409142259
Cc: Stuart Summers
Cc: Matt Roper
Signed-off-by
kms_rotation_crc manually starts and stops CRC collection and reads
single CRC values when it needs them. Depending on how long the other
test setup and execution operations take, the CRC buffer (128 entries)
can fill up CRC values that the test never reads or uses. Our CI system
has stumbled ove
On 9/7/19 1:39 AM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-09-06 23:28:05)
On 9/5/19 2:09 AM, Janusz Krzysztofik wrote:
When trying to reset a device with reset capability disabled or not
supported while rings are full of requests, it has been observed when
running in execl
On 2019-09-08 at 19:44:35 +0300, Imre Deak wrote:
> On Sat, Sep 07, 2019 at 10:44:39PM +0530, Anshuman Gupta wrote:
Hi Imre,
Thanks for reviewing the pacthes i will rework the patches.
There are few comments from my side which will help to rework.
> > Add max_dc_state and tgl_set_target_dc_state()
== Series Details ==
Series: series starting with [1/6] drm/i915/selftests: Take runtime wakeref for
igt_ggtt_lowlevel
URL : https://patchwork.freedesktop.org/series/66425/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7386b0ebc23c drm/i915/selftests: Take runtime wakeref for
In the transcoder port sync mode, the slave transcoders mask their vblanks
until master transcoder's vblank so while disabling them, make
sure slaves are disabled first and then the masters.
v4:
* Obtain slave state from master (Maarten)
v3:
* Rebase
v2:
* Use the intel_old_crtc_state_disables() h
As per the display enable sequence, we need to follow the enable sequence
for slaves first with DP_TP_CTL set to Idle and configure the transcoder
port sync register to select the corersponding master, then follow the
enable sequence for master leaving DP_TP_CTL to idle.
At this point the transcode
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: add INTEL_NUM_PIPES() and use
it (rev2)
URL : https://patchwork.freedesktop.org/series/66281/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
cfe700484f5b drm/i915: add INTEL_NUM_PIPES() and use it
34659bd2039a
On Mon, Sep 09, 2019 at 05:14:05PM +0300, Jani Nikula wrote:
> On Mon, 09 Sep 2019, "Sharma, Swati2" wrote:
> > On 30-Aug-19 6:17 PM, Jani Nikula wrote:
> >> On Fri, 30 Aug 2019, Swati Sharma wrote:
> >>> Add func intel_color_lut_equal() to compare hw/sw gamma
> >>> lut values. Since hw/sw gamma
On Mon, 09 Sep 2019, "Sharma, Swati2" wrote:
> On 30-Aug-19 6:17 PM, Jani Nikula wrote:
>> On Fri, 30 Aug 2019, Swati Sharma wrote:
>>> Add func intel_color_lut_equal() to compare hw/sw gamma
>>> lut values. Since hw/sw gamma lut sizes and lut entries comparison
>>> will be different for differen
== Series Details ==
Series: drm/i915: Vulkan performance query support (rev17)
URL : https://patchwork.freedesktop.org/series/60916/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6853 -> Patchwork_14324
Summary
---
On 30-Aug-19 6:17 PM, Jani Nikula wrote:
On Fri, 30 Aug 2019, Swati Sharma wrote:
Add func intel_color_lut_equal() to compare hw/sw gamma
lut values. Since hw/sw gamma lut sizes and lut entries comparison
will be different for different gamma modes, add gamma mode dependent
checks.
v3: -Rebase
== Series Details ==
Series: drm/i915: Vulkan performance query support (rev17)
URL : https://patchwork.freedesktop.org/series/60916/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: introduce a mechanism to extend execbuf2
Okay!
Commit: drm/i
Quoting Lionel Landwerlin (2019-07-26 14:38:40)
> On 17/07/2019 21:09, Tvrtko Ursulin wrote:
> >
> > On 17/07/2019 15:06, Chris Wilson wrote:
> >> Quoting Tvrtko Ursulin (2019-07-17 14:46:15)
> >>>
> >>> On 17/07/2019 14:35, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-07-17 14:23:55)
>
== Series Details ==
Series: drm/i915: Vulkan performance query support (rev17)
URL : https://patchwork.freedesktop.org/series/60916/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f668eec43e67 drm/i915: introduce a mechanism to extend execbuf2
-:141: CHECK:SPACING: spaces prefe
Hi Fernando,
On Wednesday, August 28, 2019 2:45:57 AM CEST Fernando Pacheco wrote:
> It is not enough to check that uc supports GuC submission now
> that we can continue to load the driver after GuC initialization
> failure (support != enabled). Instead we should explicitly check
> that we enabled
We wish to avoid our presentation worker from being blocked by normal
workloads if we want to maintain an interactive frame update.
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Heinrich Fink
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 delet
On 9/7/2019 4:37 PM, Animesh Manna wrote:
The lifetime of command buffer can be controlled by the dsb user
throuh refcount. Added refcount mechanism is dsb get/put call
which create/destroy dsb context.
Cc: Jani Nikula
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i9
== Series Details ==
Series: series starting with [1/2] drm/i915: Show the logical context ring
state on dumping
URL : https://patchwork.freedesktop.org/series/66422/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6853 -> Patchwork_14323
===
On 9/7/2019 4:37 PM, Animesh Manna wrote:
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneou
On 9/7/2019 4:37 PM, Animesh Manna wrote:
DSB will be used for performance improvement for some special scenario.
DSB engine will be enabled based on need and after completion of its work
will be disabled. Api added for enable/disable operation by using DSB_CTRL
register.
v1: Initial version.
v
On 9/7/2019 4:37 PM, Animesh Manna wrote:
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915
On 9/7/2019 4:37 PM, Animesh Manna wrote:
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. DSB feature can be used for bulk register
programming e.g. gamma lut programming, HDR meta data programming.
v1: initial version.
v2: simplified code by using ALI
Quoting Matthew Auld (2019-09-09 13:40:52)
> Try to tidy up the cache-coloring such that we rid the code of any
> mm.color_adjust assumptions, this should hopefully make it more obvious
> in the code when we need to actually use the cache-level as the color,
> and as a bonus should make adding a di
On 9/7/2019 4:37 PM, Animesh Manna wrote:
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
v1: Initial version.
v2: Unused macro r
On 9/7/2019 4:37 PM, Animesh Manna wrote:
This patch adds a function, which will internally get the gem buffer
for DSB engine. The GEM buffer is from global GTT, and is mapped into
CPU domain, contains the data + opcode to be feed to DSB engine.
v1: Initial version.
v2:
- removed some unwanted
== Series Details ==
Series: series starting with [1/2] drm/i915: Show the logical context ring
state on dumping
URL : https://patchwork.freedesktop.org/series/66422/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3f29fa89a00e drm/i915: Show the logical context ring state on du
Make it clear that the color adjust callback applies to the ggtt.
Signed-off-by: Matthew Auld
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 10 +-
drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 2 +-
2 files changed, 6
Try to tidy up the cache-coloring such that we rid the code of any
mm.color_adjust assumptions, this should hopefully make it more obvious
in the code when we need to actually use the cache-level as the color,
and as a bonus should make adding a different color-scheme simpler.
Signed-off-by: Matth
Export color_differs so that we can use it elsewhere.
Signed-off-by: Matthew Auld
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 11 ---
drivers/gpu/drm/i915/i915_vma.h | 6 ++
3 fil
In this patch series, added state checker to validate gamma lut values
for cherryview and i965 platforms. It's extension of the
patch series https://patchwork.freedesktop.org/patch/328246/?series=58039
which enabled the basic infrastructure and state checker for
few legacy platforms.
v2: Added la
For cherryview, add hw read out to create hw blob of gamma
lut values.
Review comments from previous series:
https://patchwork.freedesktop.org/patch/328252
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assi
For i965, add hw read out to create hw blob of gamma
lut values.
Review comments from old series:
https://patchwork.freedesktop.org/series/58039/
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning
intel_color_get_gamma_bit_precision() is extended for
cherryview by adding chv_gamma_precision(), i965 will use existing
i9xx_gamma_precision() func only.
Signed-off-by: Swati Sharma
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_color.c | 25 +++--
1 file c
== Series Details ==
Series: series starting with [CI,01/13] drm/i915: introduce a mechanism to
extend execbuf2
URL : https://patchwork.freedesktop.org/series/66418/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6852_full -> Patchwork_14322_full
==
Quoting Prathap Kumar Valsan (2019-08-26 01:48:01)
> To provide shared last-level-cache isolation to cpu workloads running
> concurrently with gpu workloads, the gpu allocation of cache lines needs
> to be restricted to certain ways. Currently GPU hardware supports four
> class-of-service(CLOS) lev
Be paranoid and make sure we flush any and all writes out of the WCB
before performing the UC mmio to update the RING_TAIL. (An UC write
should itself be enough to do the flush, hence the paranoia here.) Quite
infrequently, we see problems where the GPU seems to overshoot the
RING_TAIL and so execu
As soon as we re-enable the various functions within the HW, they may go
off and read data via a GGTT offset. Hence, if we have not yet restored
the GGTT PTE before then, they may read and even *write* random locations
in memory.
Detected by DMAR faults during resume.
Signed-off-by: Chris Wilson
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Kconfig.debug | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug
b/drivers/gpu/drm/i915/Kconfig.debug
index 00786a142ff0..ebcb6dbc2393 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/
Despite the widespread and complete failure of Broadwell integrated
graphics when DMAR is enabled, known over the years, we have never been
able to root cause the issue. Instead, we let the failure undermine our
confidence in the iommu system itself when we should be pushing for it to
be always ena
Other than Broadwell being fubar (and Ironlake + g4x being special in
their own way), there appears to be little fallout from enabling iommu.
(The biggest open question is over performance, TLB misses are much more
expensive and that impacts meda/CL/GL throughput.) Enabling iommu/dmar
makes our CI
Currently, if there is time remaining before the start of the loop, we
do one full iteration over many possible different chunks within the
object. A full loop may take 50+s (depending on speed of indirect GTT
mmapings) and we try separately with LINEAR, X and Y -- at which point
igt times out. If
Being a "low-level" test, we opt to bypass the normal bind/unbind hooks
for the lower level insert_entries/clear_range. For ggtt, the
bind/unbind hooks provide the runtime wakeref and so we must also handle
this in exercising the low level hooks.
<4> [538.151672] RPM raw-wakeref not held
<4> [538.
---
drivers/iommu/intel-iommu.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 34f6a3d93ae2..c98cdfd91691 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -439,8 +439,6 @@ static int __init intel_iom
With commit aa56a292ce623734ddd30f52d73f527d1f3529b5 (even on 5.3.0-rc8) I can
get a system freeze during chromium compilation (likely due to jumbo / high
memory usage). Sysrq still works and CPU/fan is low, so it seems like a
deadlock? and there's no disk reading. I can't read the dump gotten v
‐‐‐ Original Message ‐‐‐
On Monday, September 9, 2019 10:38 AM, wrote:
> With commit aa56a292ce623734ddd30f52d73f527d1f3529b5 (even on 5.3.0-rc8) I
> can get a system freeze during chromium compilation (likely due to jumbo /
> high memory usage). Sysrq still works and CPU/fan is low, s
Quoting Tvrtko Ursulin (2019-09-09 11:23:56)
>
> On 07/09/2019 11:50, Chris Wilson wrote:
> > As we may unwind incomplete requests (for preemption) prior to
> > processing the CSB and the schedule-out events, we may update rq->engine
> > (resetting it to point back to the parent virtual engine) pr
On Sat, Sep 07, 2019 at 11:19:55PM +, Mun, Gwan-gyeong wrote:
> On Fri, 2019-09-06 at 09:24 -0400, Ilia Mirkin wrote:
> > On Fri, Sep 6, 2019 at 7:43 AM Ville Syrjälä
> > wrote:
> > > On Fri, Sep 06, 2019 at 11:31:55AM +, Shankar, Uma wrote:
> > > >
> > > > > -Original Message-
>
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