Quoting Matt Turner (2019-02-21 03:23:51)
> From: Adam Jackson
>
> Presumably this only matters for i686 because amd64 implies sse2, but:
>
> BUILDSTDERR: In file included from gen4_vertex.c:34:
> BUILDSTDERR: gen4_vertex.c: In function 'emit_vertex':
> BUILDSTDERR: sna_render_inline.h:40:26: er
== Series Details ==
Series: drm/i915: Prevent user context creation while wedged
URL : https://patchwork.freedesktop.org/series/56983/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5643_full -> Patchwork_12267_full
Summary
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
> Sent: Thursday, February 21, 2019 1:10 AM
> To: C, Ramalingam
> Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
> daniel.vet...@ffwll.ch; Winkler, Tomas ; Shankar,
From: Adam Jackson
Presumably this only matters for i686 because amd64 implies sse2, but:
BUILDSTDERR: In file included from gen4_vertex.c:34:
BUILDSTDERR: gen4_vertex.c: In function 'emit_vertex':
BUILDSTDERR: sna_render_inline.h:40:26: error: inlining failed in call to
always_inline 'vertex_e
== Series Details ==
Series: drm/i915: Replace global_seqno with a hangcheck heartbeat seqno (rev3)
URL : https://patchwork.freedesktop.org/series/56587/
State : failure
== Summary ==
Applying: drm/i915: Add engine reset count in get-reset-stats ioctl
Applying: drm/i915: Watchdog timeout: IRQ
From: Michel Thierry
Save the watchdog threshold (in us) as part of the engine state.
v2: Only do it for gen8+ (and prevent a missing-case warn).
v3: use ctx->__engine.
v4: Rebase.
v5: Rebase.
Cc: Antonio Argenziano
Cc: Tvrtko Ursulin
Signed-off-by: Michel Thierry
Signed-off-by: Carlos Santa
This is a rebased on the original patch series from Michel Thierry
that can be found here:
https://patchwork.freedesktop.org/series/21868
Note that this series is only limited to the GPU Watchdog timeout
for execlists as it leaves out support
for GuC based submission for a later time.
PATCH v4 o
From: Chris Wilson
To determine whether an engine has 'stuck', we simply check whether or
not is still on the same seqno for several seconds. To keep this simple
mechanism intact over the loss of a global seqno, we can simply add a
new global heartbeat seqno instead. As we cannot know the sequenc
From: Michel Thierry
Final enablement patch for GPU hang detection using watchdog timeout.
Using the gem_context_setparam ioctl, users can specify the desired
timeout value in microseconds, and the driver will do the conversion to
'timestamps'.
The recommended default watchdog threshold for vide
From: Michel Thierry
Users/tests relying on the total reset count will start seeing a smaller
number since most of the hangs can be handled by engine reset.
Note that if reset engine x, context a running on engine y will be unaware
and unaffected.
To start the discussion, include just a total en
From: Michel Thierry
*** General ***
Watchdog timeout (or "media engine reset") is a feature that allows
userland applications to enable hang detection on individual batch buffers.
The detection mechanism itself is mostly bound to the hardware and the only
thing that the driver needs to do to su
From: Michel Thierry
Emit the required commands into the ring buffer for starting and
stopping the watchdog timer before/after batch buffer start during
batch buffer submission.
v2: Support watchdog threshold per context engine, merge lri commands,
and move watchdog commands emission to emit_bb_
== Series Details ==
Series: CRTC background color (rev7)
URL : https://patchwork.freedesktop.org/series/50834/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5645 -> Patchwork_12268
Summary
---
**SUCCESS**
No regr
== Series Details ==
Series: CRTC background color (rev7)
URL : https://patchwork.freedesktop.org/series/50834/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm: Add CRTC background color property (v5)
Okay!
Commit: drm/i915/gen9+: Add support for p
== Series Details ==
Series: CRTC background color (rev7)
URL : https://patchwork.freedesktop.org/series/50834/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
db7e455099da drm: Add CRTC background color property (v5)
-:239: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'shift' - p
Quoting Daniele Ceraolo Spurio (2019-02-20 16:51:33)
>
>
> On 2/19/19 5:39 PM, Sujaritha Sundaresan wrote:
> > The aim of this patch is to allow enabling and disabling
> > of CTB without requiring the mutex lock.
> >
> > v2: Phasing out ctch_is_enabled function and replacing it with
> > ctc
== Series Details ==
Series: drm/i915/icl: Drop redundant gamma mode mask
URL : https://patchwork.freedesktop.org/series/56975/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5641_full -> Patchwork_12266_full
Summary
---
The following changes since commit 710963fe53ee3f227556d36839df3858daf6e232:
Merge https://github.com/ajaykuee/linux-firmware (2019-02-13 07:42:20 -0500)
are available in the Git repository at:
guc_updates
for you to fetch changes up to 25e0c82e2ff5a2e11f16756ce145a797d9fbfdbe:
firmware/
CRTC background color kernel patches were written about 2.5 years ago
and floated on the upstream mailing list, but since no opensource
userspace materialized, we never actually merged them. However the
corresponding IGT test did get merged and has basically been dead code
ever since.
A couple ye
CRTC background color kernel patches were written about 2.5 years ago
and floated on the upstream mailing list, but since no opensource
userspace materialized, we never actually merged them. However the
corresponding IGT test did get merged and has basically been dead code
ever since.
A couple ye
When using --interactive-debug, it's sometimes desirable to ignore CRC
mismatches and let the test proceed as if they passed so that the
on-screen outcome can be inspected. Let's add a debug option to allow
this.
Cc: igt-...@lists.freedesktop.org
Signed-off-by: Matt Roper
---
lib/igt_core.c
We should support readout and verification of crtc background color as
we do with other pipe state. Note that our hardware holds less bits of
precision than the CRTC state allows, so we need to take care to only
verify the most significant bits of the color after performing readout.
At boot time
Gen9+ platforms allow CRTC's to be programmed with a background/canvas
color below the programmable planes. Let's expose this for use by
compositors.
v2:
- Split out bgcolor sanitization and programming of csc/gamma bits to a
separate patch that we can land before the ABI changes are ready to
This version is just a rebase of v5 onto the latest drm-tip, which was
posted here:
https://lists.freedesktop.org/archives/intel-gfx/2019-January/188352.html
There were some minor conflicts with Ville's csc/gamma disable series,
so the background color write has now moved to the new color_commit
Some display controllers can be programmed to present non-black colors
for pixels not covered by any plane (or pixels covered by the
transparent regions of higher planes). Compositors that want a UI with
a solid color background can potentially save memory bandwidth by
setting the CRTC background
== Series Details ==
Series: drm/i915: Prevent user context creation while wedged
URL : https://patchwork.freedesktop.org/series/56983/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5643 -> Patchwork_12267
Summary
---
== Series Details ==
Series: drm/i915: Prevent user context creation while wedged
URL : https://patchwork.freedesktop.org/series/56983/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9a4ebe5dfd5d drm/i915: Prevent user context creation while wedged
-:19: WARNING:COMMIT_LOG_LONG_
Introduce a new ABI method for detecting a wedged driver by reporting
-EIO from DRM_IOCTL_I915_GEM_CONTEXT_CREATE.
This came up in considering how to handle context recovery from
userspace. There we wish to create a new context after the original is
banned (the clients opts into the no recovery af
== Series Details ==
Series: drm/i915/icl: Update gamma mode mask
URL : https://patchwork.freedesktop.org/series/56974/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5640_full -> Patchwork_12265_full
Summary
---
**SU
On Thu, Feb 14, 2019 at 06:07:05PM -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2019-02-14 at 21:22 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On skl the crc registers were extended to provide plane crcs
> > for up to 7 planes. Add the new crc sources.
> >
> > The current code us
On Sat, Feb 16, 2019 at 11:07:03PM +0530, Ramalingam C wrote:
> HDCP transmitter is supposed to indicate the HDCP encryption status of
> the link through enc_en signals in a window of time called "window of
> opportunity" defined by HDCP HDMI spec.
>
> But on KBL this timing of signalling has an i
On Sat, Feb 16, 2019 at 11:06:51PM +0530, Ramalingam C wrote:
> Defining the mei-i915 interface functions and initialization of
> the interface.
>
> v2:
> Adjust to the new interface changes. [Tomas]
> Added further debug logs for the failures at MEI i/f.
> port in hdcp_port data is equipped
== Series Details ==
Series: drm/i915/icl: Drop redundant gamma mode mask
URL : https://patchwork.freedesktop.org/series/56975/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5641 -> Patchwork_12266
Summary
---
**SUCC
On Mon, 2019-02-18 at 19:57 +0200, Ville Syrjälä wrote:
> On Fri, Feb 15, 2019 at 09:43:37PM +, Pandiyan, Dhinakaran wrote:
> > On Fri, 2019-02-15 at 23:34 +0200, Ville Syrjälä wrote:
> > > On Fri, Feb 15, 2019 at 01:06:32PM -0800, Dhinakaran Pandiyan
> > > wrote:
> > > > On Fri, 2019-02-15 at
On Thu, Feb 14, 2019 at 3:15 PM Chris Wilson
wrote:
> Quoting Matthew Auld (2019-02-14 14:57:32)
> > From: Abdiel Janulgue
> >
> > Returns the available memory region areas supported by the HW.
>
> This should include references to the Vulkan spec to show how it can be
> used to convey the infor
== Series Details ==
Series: drm/i915/icl: Update gamma mode mask
URL : https://patchwork.freedesktop.org/series/56974/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5640 -> Patchwork_12265
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: Beware temporary wedging when determining -EIO (rev8)
URL : https://patchwork.freedesktop.org/series/56898/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5636_full -> Patchwork_12264_full
==
gamma mode mask was not considering the 30th and 31st bits.
Due to this state readout was masking these bits, causing a
mismatch and false warning, even though the registers were
updated correctly. Dropped the gamma mode mask as it is
redundant and ideally entire register content should be
matching
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Wednesday, February 20, 2019 11:54 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville ;
>Lankhorst,
>Maarten
>Subject: Re: [Intel-gfx] [PATCH] drm/i915/icl: Update gamma mode m
On Thu, Feb 21, 2019 at 12:05:50AM +0530, Uma Shankar wrote:
> Update gamma mode mask to consider even the 30th and 31st
> bits as per hardware. Due to this state readout was masking
> these bits, causing a mismatch and false warning, even though
> the registers were updated correctly. This patch f
Update gamma mode mask to consider even the 30th and 31st
bits as per hardware. Due to this state readout was masking
these bits, causing a mismatch and false warning, even though
the registers were updated correctly. This patch fixes the same.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915
On 2/19/19 5:39 PM, Sujaritha Sundaresan wrote:
The aim of this patch is to allow enabling and disabling
of CTB without requiring the mutex lock.
v2: Phasing out ctch_is_enabled function and replacing it with
ctch->enabled (Daniele)
You did a couple more things (better comments, move/ad
== Series Details ==
Series: drm/i915: Beware temporary wedging when determining -EIO (rev8)
URL : https://patchwork.freedesktop.org/series/56898/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5636 -> Patchwork_12264
Summar
== Series Details ==
Series: drm/i915: Beware temporary wedging when determining -EIO (rev8)
URL : https://patchwork.freedesktop.org/series/56898/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Beware temporary wedging when determining -EIO
-
Hi Dave and Daniel, one final fix for v5.0, cc: stable.
BR,
Jani.
The following changes since commit a3b22b9f11d9fbc48b0291ea92259a5a810e9438:
Linux 5.0-rc7 (2019-02-17 18:46:40 -0800)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes
Chris Wilson writes:
> Limit deboosting and boosting to keep ourselves at the extremes
> when in the respective power modes (i.e. slowly decrease frequencies
> while in the HIGH_POWER zone and slowly increase frequencies while
> in the LOW_POWER zone). On idle, we will hit the timeout and drop
>
At a few points in our uABI, we check to see if the driver is wedged and
report -EIO back to the user in that case. However, as we perform the
check and reset asynchronously (where once before they were both
serialised by the struct_mutex), we may instead see the temporary wedging
used to cancel in
Chris Wilson writes:
> The idea of taking the reset lock around writing the fence register was
> to serialise the mmio write we also perform during the reset where those
> registers get clobbered. However, the lock is overkill as write tearing
> between reset and fence_update() is harmless; the f
Chris Wilson writes:
> At a few points in our uABI, we check to see if the driver is wedged and
> report -EIO back to the user in that case. However, as we perform the
> check and reset asynchronously, we may instead see the temporary wedging
> used to cancel inflight rendering to avoid a deadloc
Chris Wilson writes:
> norecovery intentionally issues a GPU reset, but we should only do so
> after confirming with the kernel that this can work.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> tests/i915/gem_ctx_exec.c | 5 +
> 1 file changed, 5 insertions(+)
>
> di
Quoting Lyude Paul (2019-02-19 21:00:08)
> Should this maybe be CC'd for stable for v4.20? If so I've already got a
> working port of this patch that I can send to you (I've been running it on my
> laptop for a while now, seems to work fine)
I wouldn't say no (I am still wondering if we can do bet
As we already have the previous portion of the mmap mlocked, we only
need to mlock() the fresh portion for testing available memory.
v2: Fixup the uint64_t pointer arithmetric and only use a single mmap to
avoid subsequent mlock fail (for reasons unknown, but bet on mm/).
Signed-off-by: Chris Wil
== Series Details ==
Series: Enable P0xx (planar), Y2xx/Y4xx (packed) pixel formats (rev2)
URL : https://patchwork.freedesktop.org/series/56606/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5634_full -> Patchwork_12263_full
Quoting Daniel Vetter (2019-02-19 09:55:27)
> Hi all,
>
> topic/mei-hdcp-2019-02-19:
> Prep patches + headers for the mei-hdcp/i915 component interfaces
>
> Also contains the prep work in the component helpers plus adjustements
> for the snd-hda/i915 component interface.
>
> Plus one small stati
norecovery intentionally issues a GPU reset, but we should only do so
after confirming with the kernel that this can work.
Signed-off-by: Chris Wilson
---
tests/i915/gem_ctx_exec.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
inde
>-Original Message-
>From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
>Sent: Wednesday, February 20, 2019 2:27 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Add Colorspace connector
>property
>interface (rev16)
== Series Details ==
Series: Enable P0xx (planar), Y2xx/Y4xx (packed) pixel formats (rev2)
URL : https://patchwork.freedesktop.org/series/56606/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5634 -> Patchwork_12263
Summary
== Series Details ==
Series: Enable P0xx (planar), Y2xx/Y4xx (packed) pixel formats (rev2)
URL : https://patchwork.freedesktop.org/series/56606/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Add P010, P012, P016 plane control definitions
Oka
== Series Details ==
Series: Enable P0xx (planar), Y2xx/Y4xx (packed) pixel formats (rev2)
URL : https://patchwork.freedesktop.org/series/56606/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d2477734f515 drm/i915: Add P010, P012, P016 plane control definitions
d9f13172c49c drm/
Op 20-02-2019 om 07:01 schreef Shankar, Uma:
>
>> -Original Message-
>> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>> Patchwork
>> Sent: Wednesday, February 20, 2019 2:43 AM
>> To: intel-gfx@lists.freedesktop.org
>> Subject: [Intel-gfx] ✗ Fi.CI.IGT: failur
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