On Thu, Feb 21, 2019 at 12:05:50AM +0530, Uma Shankar wrote:
> Update gamma mode mask to consider even the 30th and 31st
> bits as per hardware. Due to this state readout was masking
> these bits, causing a mismatch and false warning, even though
> the registers were updated correctly. This patch fixes the same.
>
> Signed-off-by: Uma Shankar <uma.shan...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a5a4736..df1b844 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7142,7 +7142,7 @@ enum {
> #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
> #define PRE_CSC_GAMMA_ENABLE (1 << 31)
> #define POST_CSC_GAMMA_ENABLE (1 << 30)
> -#define GAMMA_MODE_MODE_MASK (3 << 0)
> +#define GAMMA_MODE_MODE_MASK ((3 << 30) | (3 << 0))a
IMO we should just drop the mask entirely. What we have in the state
should match the entire hw register.
> #define GAMMA_MODE_MODE_8BIT (0 << 0)
> #define GAMMA_MODE_MODE_10BIT (1 << 0)
> #define GAMMA_MODE_MODE_12BIT (2 << 0)
> --
> 1.9.1
>
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--
Ville Syrjälä
Intel
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