On 2018.10.30 15:08:01 +0800, intel-gfx-boun...@lists.freedesktop.org wrote:
> From: Hang Yuan
>
> This reverts commit c9e666880de5a1fed04dc412b046916d542b72dd.
>
> Checked GVT codes that guest PPGTT PTE flag bits are propagated
> to shadow PTE. Read/write bit is not changed. Further tested by
>
== Series Details ==
Series: series starting with [v2,1/5] drm/i915/debugfs: Do not print cached
information of a disconnected sink
URL : https://patchwork.freedesktop.org/series/51782/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5057_full -> Patchwork_10654_full =
== Su
On Tue, 2018-10-30 at 19:52 +0200, Ville Syrjälä wrote:
> On Wed, Oct 10, 2018 at 02:35:07PM -0700, José Roberto de Souza
> wrote:
> > Some USB type-C dongles requires some time to power on before being
> > able to process aux channel transactions.
> > It was not a problem for older gens because th
DP 1.4 has Forward Error Correction Support(FEC).
Add helper function to check if the sink device
supports FEC.
v2: Separate the helper and the code that uses the helper into
two separate patches. (Manasi)
v3:
- Move the code to drm_dp_helper.c (Manasi)
- change the return type, code style change
Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error correction on other scenarios too
if needed.
v2:
- Control compression_enable with the fec_enable
parameter in crtc state and with intel_dp_supports
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
Check if the sink supports FEC using the helper.
v2: Mention External DP where ever FEC is mentioned
in the code.Check return status of dpcd reads. (Gaurav)
- Do regular mode check ev
Similar to DSC DPCD registers, let us cache
FEC_CAPABLE register to avoid using stale
values. With this we can avoid aux reads
everytime and instead read the cached values.
v2: Avoid using memset and array for a single
field. (Manasi,Jani)
v3:
Suggested-by: Jani Nikula
Cc: Jani Nikula
Cc: Vill
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased. (r-b Manasi)
v4: Use fec crtc state, be
With Display Compression, the bit error in the pixel
stream can turn into a significant corruption on
the screen. The DP1.4 adds FEC - Forward Error Correction
scheme which uses Reed-Solomon parity/correction check
generated by the source and used by the sink to detect
and correct small numbers of
If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.
The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is already active while enabling
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)
Cc: Gaurav K Singh
Cc: Jani Nikula
C
On Wed, 2018-10-31 at 02:33 +0200, Imre Deak wrote:
> On Wed, Oct 31, 2018 at 02:17:36AM +0200, Souza, Jose wrote:
> > On Wed, 2018-10-31 at 02:04 +0200, Imre Deak wrote:
> > > On Wed, Oct 31, 2018 at 01:52:58AM +0200, Souza, Jose wrote:
> > > > On Wed, 2018-10-31 at 01:28 +0200, Imre Deak wrote:
>
== Series Details ==
Series: drm/i915/icl: Fix HDMI on TypeC static ports (rev2)
URL : https://patchwork.freedesktop.org/series/51765/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5057_full -> Patchwork_10653_full =
== Summary - SUCCESS ==
No regressions found.
==
On Wed, Oct 31, 2018 at 02:17:36AM +0200, Souza, Jose wrote:
> On Wed, 2018-10-31 at 02:04 +0200, Imre Deak wrote:
> > On Wed, Oct 31, 2018 at 01:52:58AM +0200, Souza, Jose wrote:
> > > On Wed, 2018-10-31 at 01:28 +0200, Imre Deak wrote:
> > > > On Wed, Oct 31, 2018 at 01:18:09AM +0200, Souza, Jose
On Wed, 2018-10-31 at 02:04 +0200, Imre Deak wrote:
> On Wed, Oct 31, 2018 at 01:52:58AM +0200, Souza, Jose wrote:
> > On Wed, 2018-10-31 at 01:28 +0200, Imre Deak wrote:
> > > On Wed, Oct 31, 2018 at 01:18:09AM +0200, Souza, Jose wrote:
> > > > On Wed, 2018-10-31 at 01:12 +0200, Imre Deak wrote:
>
DSC is supported on eDP starting GEN 10 display (on GLK) and on DP starting
GEN 11.
This patch implements the discovery phase of DSC. On hotplug,
source reads the DSC DPCD register set (0x00060 - 0x0006F) to
read the decompression capabilities of the sink device.
This entire block of registers is c
This patch adds helpers for calculating the maximum compressed BPP
supported with small joiner.
This also adds a helper for calculating the slice count in case
of small joiner.
These are inside intel_dp since they take into account hardware
limitations.
v6:
* Take mode_clock and mode_hdisplay as i
DP 1.4 spec defines DP secondary data packet for DSC
picture parameter set. This patch defines its payload size
according to the DP 1.4 specification.
Signed-off-by: Manasi Navare
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Revi
This patch defines the DP DSC receiver capability size that gives
total number of DP DSC DPCD registers.
This also adds a missing #defines for DP DSC support missed in the
commit id (ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature")
v3:
* MIN_SLICE_WIDTH = 2560 (Anusha)
* Define DP_DSC
This patch adds inline functions and helpers for obtaining
DP sink's supported DSC parameters like DSC sink support,
eDP compressed BPP supported, maximum slice count supported
by the sink devices, DSC line buffer bit depth supported on DP sink,
DSC sink maximum color depth by parsing corresponding
From: Anusha Srivatsa
Add the newly added slice_row_per_frame parameter
in the Picture Parameter Set registers.
This defines the number of vertically stacked slices
in a frame.
Credits to Manasi for noticing bSpec change.
Suggested-by: Manasi Navare
Cc: Manasi Navare
Signed-off-by: Anusha Sri
When DSC is supported we need to validate the modes based on the
maximum supported compressed BPP and maximum supported slice count.
This allows us to allow the modes with pixel clock greater than the
available link BW as long as it meets the compressed BPP
and slice count requirements.
v3:
* Use
On Wed, Oct 31, 2018 at 01:52:58AM +0200, Souza, Jose wrote:
> On Wed, 2018-10-31 at 01:28 +0200, Imre Deak wrote:
> > On Wed, Oct 31, 2018 at 01:18:09AM +0200, Souza, Jose wrote:
> > > On Wed, 2018-10-31 at 01:12 +0200, Imre Deak wrote:
> > > > On Wed, Oct 31, 2018 at 01:07:04AM +0200, Souza, Jose
On Wed, Oct 24, 2018 at 08:30:11PM +0530, Uma Shankar wrote:
> Add support for icl pipe degamma and gamma.
>
> v2: Removed a POSTING_READ and corrected the Bit
> Definition as per Maarten's comments.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_reg.h| 3 ++
> drivers/gp
On Wed, 2018-10-31 at 00:38 +0200, Imre Deak wrote:
> On Wed, Oct 31, 2018 at 12:32:35AM +0200, Souza, Jose wrote:
> > On Tue, 2018-10-30 at 17:40 +0200, Imre Deak wrote:
> > > From ICL onwards DDI/TypeC ports - even in HDMI static mode -
> > > need to
> > > know
> > > which AUX CH belongs to them,
On Tue, 2018-10-30 at 17:40 +0200, Imre Deak wrote:
> BIOS can leave the PLL to port mapping enabled, even if the
> corresponding encoder is disabled. Disable the port mapping in this
> case.
>
Reviewed-by: José Roberto de Souza
> Cc: Paulo Zanoni
> Cc: Ville Syrjälä
> Signed-off-by: Imre Dea
On Wed, 2018-10-31 at 01:28 +0200, Imre Deak wrote:
> On Wed, Oct 31, 2018 at 01:18:09AM +0200, Souza, Jose wrote:
> > On Wed, 2018-10-31 at 01:12 +0200, Imre Deak wrote:
> > > On Wed, Oct 31, 2018 at 01:07:04AM +0200, Souza, Jose wrote:
> > > > On Tue, 2018-10-30 at 17:40 +0200, Imre Deak wrote:
>
On Wed, Oct 24, 2018 at 03:28:24PM -0700, Manasi Navare wrote:
> Basic DSC parameters and DSC configuration data needs to be computed
> for each of the requested mode during atomic check. This is
> required since for certain modes, valid DSC parameters and config
> data might not be computed in whi
On Thu, Oct 25, 2018 at 05:09:42PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:34PM -0700, Manasi Navare wrote:
> > DSC PPS secondary data packet infoframes are filled with
> > DSC picure parameter set metadata according to the DSC standard.
> > These infoframes are sent to the sink
On Wed, Oct 31, 2018 at 01:18:09AM +0200, Souza, Jose wrote:
> On Wed, 2018-10-31 at 01:12 +0200, Imre Deak wrote:
> > On Wed, Oct 31, 2018 at 01:07:04AM +0200, Souza, Jose wrote:
> > > On Tue, 2018-10-30 at 17:40 +0200, Imre Deak wrote:
> > > > For DDI/TypeC ports the AUX power domain needs to be
On Tue, 2018-10-30 at 17:40 +0200, Imre Deak wrote:
> Most of the AUX_CH_CTL flags are concerned with DP AUX transfer
> parameters. As opposed to this the flag specifying the thunderbolt
> vs.
> non-thunderbolt mode of the port is not related to AUX transfers at
> all
> (rather it's repurposed to e
On Wed, 2018-10-31 at 01:12 +0200, Imre Deak wrote:
> On Wed, Oct 31, 2018 at 01:07:04AM +0200, Souza, Jose wrote:
> > On Tue, 2018-10-30 at 17:40 +0200, Imre Deak wrote:
> > > For DDI/TypeC ports the AUX power domain needs to be enabled
> > > before
> > > the
> > > port's PLL is enabled, so move t
== Series Details ==
Series: series starting with [1/5] drm/i915: Remove CNL from WA 827 (rev4)
URL : https://patchwork.freedesktop.org/series/51713/
State : failure
== Summary ==
Applying: drm/i915: Remove CNL from WA 827
Applying: drm/i915/cnl: Remove useless CNL A-stepping workarounds.
Appl
On Wed, Oct 31, 2018 at 01:07:04AM +0200, Souza, Jose wrote:
> On Tue, 2018-10-30 at 17:40 +0200, Imre Deak wrote:
> > For DDI/TypeC ports the AUX power domain needs to be enabled before
> > the
> > port's PLL is enabled, so move the enabling earlier accordingly.
>
> Could you just pointed out whe
== Series Details ==
Series: series starting with [v2,1/5] drm/i915/debugfs: Do not print cached
information of a disconnected sink
URL : https://patchwork.freedesktop.org/series/51782/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5057 -> Patchwork_10654 =
== Summary - SU
On Tue, 2018-10-30 at 17:40 +0200, Imre Deak wrote:
> DDI/TypeC ports need the AUX power domain for main link functionality
> even when they operate in HDMI static mode, so enable the power
> domain
> for these ports too.
>
Reviewed-by: José Roberto de Souza
> Cc: Paulo Zanoni
> Cc: Ville Syrj
On Tue, 2018-10-30 at 17:40 +0200, Imre Deak wrote:
> For DDI/TypeC ports the AUX power domain needs to be enabled before
> the
> port's PLL is enabled, so move the enabling earlier accordingly.
Could you just pointed out where did you got this information? I
checked in this Bspec pages 20845, 205
On Wed, Oct 31, 2018 at 12:32:35AM +0200, Souza, Jose wrote:
> On Tue, 2018-10-30 at 17:40 +0200, Imre Deak wrote:
> > From ICL onwards DDI/TypeC ports - even in HDMI static mode - need to
> > know
> > which AUX CH belongs to them, so initialize aux_ch for those ports
> > too.
> > For consistency d
On Tue, 2018-10-30 at 17:40 +0200, Imre Deak wrote:
> From ICL onwards all the DDI/TypeC ports - even working in HDMI mode
> -
> need to know their corresponding AUX channel, so move the
> corresponding
> helper to a common place.
>
> No functional change.
>
Reviewed-by: José Roberto de Souza
On Tue, 2018-10-30 at 17:40 +0200, Imre Deak wrote:
> From ICL onwards all DDI/TypeC ports - even working in HDMI mode -
> need
> to know their corresponding AUX CH, so move the field to a common
> struct.
>
> No functional change.
>
> Cc: Paulo Zanoni
> Cc: Ville Syrjälä
> Signed-off-by: Imre
On Tue, Oct 30, 2018 at 05:30:25PM +0800, kbuild test robot wrote:
> Hi Radhakrishna,
>
> Thank you for the patch! Perhaps something to improve:
>
> [auto build test WARNING on drm-intel/for-linux-next]
> [also build test WARNING on v4.19 next-20181030]
> [if your patch is
On Tue, 2018-10-30 at 17:40 +0200, Imre Deak wrote:
> From ICL onwards DDI/TypeC ports - even in HDMI static mode - need to
> know
> which AUX CH belongs to them, so initialize aux_ch for those ports
> too.
> For consistency do this for all HDMI ports, not only for DDI/TypeC
> ones.
>
> Cc: Paulo
On Tue, Oct 30, 2018 at 01:45:02AM -0700, Radhakrishna Sripada wrote:
> Display WA_1405510057 asks to not enable YUV 420 HDMI
> 10bpc when horizontal blank size mod 8 reminder is 2.
>
> V2: Rebase(r-b: Anusha)
> V3: crtc_state->s/ycbcr420/output_format/
>
> Cc: Anusha Srivatsa
> Cc: Paulo Zanoni
Let's introduce the WA number that is the
cause of having NV12 disabled on both SLK and BXT.
According to Spec:
WA 0870: "Display flickers with NV12 video playback in
Y tiling mode.
WA: Use YUV422 surface format instead of NV12."
v2: remove the useless dead code and consequently
avoiding dev
On Tue, Oct 30, 2018 at 02:55:00PM -0700, Manasi Navare wrote:
> On Tue, Oct 30, 2018 at 09:05:57PM +0200, Imre Deak wrote:
> > For DDI/TypeC ports the AUX power domain needs to be enabled before the
> > port's PLL is enabled, so move the enabling earlier accordingly.
> >
> > v2:
> > - Preserve th
Otherwise it would be in a inconsistent state as port is disconnected
but with a valid tc type.
Cc: Paulo Zanoni
Reviewed-by: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_dp.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/driver
Otherwise it would be in a inconsistent state as port is disconnected
but with a valid tc type.
Also setting it to unknown will earlier return
icl_tc_phy_disconnect() for any future calls to
intel_digital_port_connected(), this way we don't need to check if
port is marked as safe everytime.
Cc: P
Besides of give the expected output of i915_display_info it will also
avoid some aux ch transactions that would timeout by obvious reasons.
Reviewed-by: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 +++--
1 file changed, 11 inse
On Tue, Oct 30, 2018 at 05:40:50PM +0200, Imre Deak wrote:
> Most of the AUX_CH_CTL flags are concerned with DP AUX transfer
> parameters. As opposed to this the flag specifying the thunderbolt vs.
> non-thunderbolt mode of the port is not related to AUX transfers at all
> (rather it's repurposed t
enc_to_dig_port() returns NULL for encoders of type
INTEL_OUTPUT_DP_MST causing the crash bellow:
[ 2832.836101] BUG: unable to handle kernel paging request at 12b8
[ 2832.843062] PGD 0 P4D 0
[ 2832.845610] Oops: [#1] SMP
[ 2832.848764] CPU: 2 PID: 3577 Comm: kworker/2:0 Tainted:
It is only used by eDP ports so no need to initialize it for each DP
port.
Reviewed-by: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_dp.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/d
On Tue, Oct 30, 2018 at 09:05:57PM +0200, Imre Deak wrote:
> For DDI/TypeC ports the AUX power domain needs to be enabled before the
> port's PLL is enabled, so move the enabling earlier accordingly.
>
> v2:
> - Preserve the pre_pll hook for GEN9_LP. (Ville)
>
> Cc: Paulo Zanoni
> Cc: Ville Syrj
On Tue, Oct 30, 2018 at 02:16:08PM -0700, Lucas De Marchi wrote:
> On Tue, Oct 30, 2018 at 05:40:47PM +0200, Imre Deak wrote:
> > From ICL onwards the AUX power domain may change dynamically based on
> > whether a DDI/TypeC port is in thunderbolt or non-thunderbolt mode, so
> > use a helper functio
On Tue, Oct 30, 2018 at 05:40:47PM +0200, Imre Deak wrote:
> From ICL onwards the AUX power domain may change dynamically based on
> whether a DDI/TypeC port is in thunderbolt or non-thunderbolt mode, so
> use a helper function instead of a static field to get the current
> domain.
>
> Cc: Paulo Z
On Tue, 2018-10-30 at 19:51 +0200, Ville Syrjälä wrote:
> On Wed, Oct 10, 2018 at 02:35:05PM -0700, José Roberto de Souza
> wrote:
> > Otherwise it would be in a inconsistent state as port is
> > disconnected
> > but with a valid tc type.
> >
> > Cc: Paulo Zanoni
> > Signed-off-by: José Roberto d
== Series Details ==
Series: drm/i915/icl: Fix HDMI on TypeC static ports (rev2)
URL : https://patchwork.freedesktop.org/series/51765/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5057 -> Patchwork_10653 =
== Summary - SUCCESS ==
No regressions found.
External URL:
On Tue, Oct 30, 2018 at 08:57:12PM +0200, Ville Syrjälä wrote:
> On Thu, Oct 25, 2018 at 09:49:40PM -0700, Anusha Srivatsa wrote:
> > Add a crtc state for FEC. Currently, the state
> > is determined by platform, DP and DSC being
> > enabled. Moving forward we can use the state
> > to have error cor
== Series Details ==
Series: drm/i915/icl: Fix HDMI on TypeC static ports (rev2)
URL : https://patchwork.freedesktop.org/series/51765/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Move intel_aux_ch() to intel_bios.c
-drivers/gpu/drm/i915/se
== Series Details ==
Series: drm/i915/icl: Fix HDMI on TypeC static ports (rev2)
URL : https://patchwork.freedesktop.org/series/51765/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e4ad990a6870 drm/i915: Move intel_aux_ch() to intel_bios.c
-:47: CHECK:SPACING: No space is neces
For DDI/TypeC ports the AUX power domain needs to be enabled before the
port's PLL is enabled, so move the enabling earlier accordingly.
v2:
- Preserve the pre_pll hook for GEN9_LP. (Ville)
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c |
On Thu, Oct 25, 2018 at 09:49:40PM -0700, Anusha Srivatsa wrote:
> Add a crtc state for FEC. Currently, the state
> is determined by platform, DP and DSC being
> enabled. Moving forward we can use the state
> to have error correction on other scenarios too
> if needed.
>
> Suggested-by: Ville Syrj
Quoting hang.y...@linux.intel.com (2018-10-30 07:08:01)
> From: Hang Yuan
>
> This reverts commit c9e666880de5a1fed04dc412b046916d542b72dd.
>
> Checked GVT codes that guest PPGTT PTE flag bits are propagated
> to shadow PTE. Read/write bit is not changed. Further tested by
> i915 self-test case
On Mon, Oct 29, 2018 at 04:00:44PM -0700, Rodrigo Vivi wrote:
> According to BSpec this is not needed anymore:
>
> "This workaround is no longer needed since NV12
> support is dropped for the affected projects.
> "
>
> Cc: Maarten Lankhorst
> Cc: Ville Syrjälä
> Signed-off-by: Rodrigo Vivi
Ma
On Mon, Oct 29, 2018 at 04:00:43PM -0700, Rodrigo Vivi wrote:
> First of all I believe this WA as written here was wrong.
>
> Because it is listed on BSpec only for SKL and BXT, exactly
> the only 2 platforms skipped here.
>
> But also it is written there that we don't need this WA
> anymore:
> "
On Tue, Oct 30, 2018 at 11:52:30AM +0200, Jani Nikula wrote:
> On Mon, 29 Oct 2018, Rodrigo Vivi wrote:
> > Introduce Display Gen. The goal is to use this to minimize
> > the amount of platform codename checks we have nowdays on
> > display code.
> >
> > The introduction of a new platform should b
On Mon, Oct 29, 2018 at 04:00:42PM -0700, Rodrigo Vivi wrote:
> Let's introduce HAS_NV12 to check for feature itself
> than spread the platform checks everywhere.
>
> Also let's introduce the WA number that is the
> cause of having NV12 disabled on both SLK and BXT.
>
> According to Spec:
>
> WA
On Tue, Oct 30, 2018 at 05:30:46PM +, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-10-30 13:32:39)
> > On Mon, Oct 29, 2018 at 08:49:58PM +, Chris Wilson wrote:
> > > Older platforms require fence registers to perform blits, and so
> > > userspace is expected to mark up the objects to
On Mon, Oct 29, 2018 at 03:14:10PM -0700, Anusha Srivatsa wrote:
> From: Animesh Manna
>
> ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
> DC5/6 when appropriate.
>
> v2: (James Ausmus)
> - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
>i915_drm_suspend_
On Wed, Oct 10, 2018 at 02:35:08PM -0700, José Roberto de Souza wrote:
> enc_to_dig_port() returns NULL for encoders of type
> INTEL_OUTPUT_DP_MST causing the crash bellow:
>
> [ 2832.836101] BUG: unable to handle kernel paging request at 12b8
> [ 2832.843062] PGD 0 P4D 0
> [ 2832.8456
On Wed, Oct 10, 2018 at 02:35:07PM -0700, José Roberto de Souza wrote:
> Some USB type-C dongles requires some time to power on before being
> able to process aux channel transactions.
> It was not a problem for older gens because there was a bridge
> between DP port and USB-C controller adding som
On Wed, Oct 10, 2018 at 02:35:06PM -0700, José Roberto de Souza wrote:
> It is only used by eDP ports so no need to initialize it for each DP
> port.
>
> Signed-off-by: José Roberto de Souza
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_dp.c | 5 ++---
> 1 file changed, 2 inse
On Wed, Oct 10, 2018 at 02:35:05PM -0700, José Roberto de Souza wrote:
> Otherwise it would be in a inconsistent state as port is disconnected
> but with a valid tc type.
>
> Cc: Paulo Zanoni
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_dp.c | 7 ---
> 1 file ch
+cc Ville
On Tue, Oct 30, 2018 at 11:52:30AM +0200, Jani Nikula wrote:
> On Mon, 29 Oct 2018, Rodrigo Vivi wrote:
> > Introduce Display Gen. The goal is to use this to minimize
> > the amount of platform codename checks we have nowdays on
> > display code.
> >
> > The introduction of a new platfo
Quoting Ville Syrjälä (2018-10-30 13:32:39)
> On Mon, Oct 29, 2018 at 08:49:58PM +, Chris Wilson wrote:
> > Older platforms require fence registers to perform blits, and so
> > userspace is expected to mark up the objects to request fences be
> > assigned.
> >
> > Fixes: ff2db94acb53 ("igt/gem
== Series Details ==
Series: drm/i915/icl: Fix HDMI on TypeC static ports
URL : https://patchwork.freedesktop.org/series/51765/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5055 -> Patchwork_10652 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_1
== Series Details ==
Series: drm/i915/icl: Fix HDMI on TypeC static ports
URL : https://patchwork.freedesktop.org/series/51765/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Move intel_aux_ch() to intel_bios.c
-drivers/gpu/drm/i915/selftests
== Series Details ==
Series: drm/i915/icl: Fix HDMI on TypeC static ports
URL : https://patchwork.freedesktop.org/series/51765/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
83eb4def4751 drm/i915: Move intel_aux_ch() to intel_bios.c
-:47: CHECK:SPACING: No space is necessary af
== Series Details ==
Series: drm/i915/icl: dsi enabling (rev3)
URL : https://patchwork.freedesktop.org/series/51011/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5055 -> Patchwork_10651 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10651 absolu
== Series Details ==
Series: drm/i915: Stop calling intel_opregion unregister/register in
suspend/resume (rev2)
URL : https://patchwork.freedesktop.org/series/50630/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5054_full -> Patchwork_10649_full =
== Summary - SUCCESS ==
Most of the AUX_CH_CTL flags are concerned with DP AUX transfer
parameters. As opposed to this the flag specifying the thunderbolt vs.
non-thunderbolt mode of the port is not related to AUX transfers at all
(rather it's repurposed to enable either TBT or non-TBT PHY HW blocks).
The programming has
From ICL onwards the AUX power domain may change dynamically based on
whether a DDI/TypeC port is in thunderbolt or non-thunderbolt mode, so
use a helper function instead of a static field to get the current
domain.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/dr
BIOS can leave the PLL to port mapping enabled, even if the
corresponding encoder is disabled. Disable the port mapping in this
case.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 23 +++
drivers/gpu/drm/i915/intel_di
From ICL onwards DDI/TypeC ports - even in HDMI static mode - need to know
which AUX CH belongs to them, so initialize aux_ch for those ports too.
For consistency do this for all HDMI ports, not only for DDI/TypeC ones.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gp
For DDI/TypeC ports the AUX power domain needs to be enabled before the
port's PLL is enabled, so move the enabling earlier accordingly.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 46 +---
drivers/gpu/d
DDI/TypeC ports need the AUX power domain for main link functionality
even when they operate in HDMI static mode, so enable the power domain
for these ports too.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 15 +++
1 file change
From ICL onwards all the DDI/TypeC ports - even working in HDMI mode -
need to know their corresponding AUX channel, so move the corresponding
helper to a common place.
No functional change.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_drv.h | 1
ICL has repurposed some of the AUX HW signals/flags, so that we have to
program these for HDMI too. In practice this means enabling the AUX
power well for HDMI mode too.
The last patch fixes an issue where BIOS leaves the PLL->port mapping
enabled even though the corresponding encoder is disabled.
From ICL onwards all DDI/TypeC ports - even working in HDMI mode - need
to know their corresponding AUX CH, so move the field to a common
struct.
No functional change.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 4 +++-
drivers/gpu/drm/i
On Tue, Oct 30, 2018 at 04:18:28PM +0200, Ville Syrjälä wrote:
> On Tue, Oct 30, 2018 at 10:35:07AM +0100, Daniel Vetter wrote:
> > On Mon, Oct 29, 2018 at 04:00:04PM -0700, Eric Anholt wrote:
> > > Ville Syrjala writes:
> > >
> > > > From: Ville Syrjälä
> > > >
> > > > Add a function to check w
On Tue, Oct 30, 2018 at 6:56 AM Jani Nikula wrote:
>
> On Mon, 29 Oct 2018, Anusha Srivatsa wrote:
> > The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
> > from the base - which is the FLexi IO Adaptor. Lets follow the
> > offset calculation while accessing these registers.
>
> Why
On Tue, Oct 30, 2018 at 10:35:07AM +0100, Daniel Vetter wrote:
> On Mon, Oct 29, 2018 at 04:00:04PM -0700, Eric Anholt wrote:
> > Ville Syrjala writes:
> >
> > > From: Ville Syrjälä
> > >
> > > Add a function to check whether there is at least one plane that
> > > supports a specific format and
On Tue, 30 Oct 2018, Ville Syrjälä wrote:
> On Tue, Oct 30, 2018 at 01:56:40PM +0200, Jani Nikula wrote:
>> From: Madhav Chauhan
>>
>> For ICELAKE DSI, Display Pins are the only GPIOs
>> that need to be programmed. So DSI driver should have
>> its own implementation to toggle these pins based on
On Tue, Oct 30, 2018 at 01:56:43PM +0200, Jani Nikula wrote:
> From: Madhav Chauhan
>
> For Gen11 DSI, we use similar registers like for eDP
> to find if DSI encoder is connected or not to a pipe.
> This patch refactors existing hsw_get_transcoder_state()
> to handle this.
>
> Signed-off-by: Mad
On Tue, Oct 30, 2018 at 01:56:40PM +0200, Jani Nikula wrote:
> From: Madhav Chauhan
>
> For ICELAKE DSI, Display Pins are the only GPIOs
> that need to be programmed. So DSI driver should have
> its own implementation to toggle these pins based on
> GPIO info coming from VBT sequences instead of
On Mon, 29 Oct 2018, Anusha Srivatsa wrote:
> The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
> from the base - which is the FLexi IO Adaptor. Lets follow the
> offset calculation while accessing these registers.
Why?
If I search the specs or i915_reg.h for, say, 0x1638c0 I'll fi
On Mon, Oct 29, 2018 at 08:49:58PM +, Chris Wilson wrote:
> Older platforms require fence registers to perform blits, and so
> userspace is expected to mark up the objects to request fences be
> assigned.
>
> Fixes: ff2db94acb53 ("igt/gem_tiled_fence_blits: Remove libdrm_intel
> dependence")
== Series Details ==
Series: drm/i915/gtt: Revert "Disable read-only support under GVT"
URL : https://patchwork.freedesktop.org/series/51730/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5053_full -> Patchwork_10644_full =
== Summary - WARNING ==
Minor unknown changes c
Hi Matthew,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.19 next-20181030]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https
On Tue, 30 Oct 2018, Jani Nikula wrote:
> Jani Nikula (3):
> drm/i915/icl: Allocate DSI encoder/connector
> drm/i915/icl: Allocate hosts for DSI ports
> drm/i915/icl: Load DSI packet payload to queue
These are by Madhav, I accidentally took authorship while
rebasing. Fixed locally.
BR,
Jan
== Series Details ==
Series: drm/i915/icl: dsi enabling (rev3)
URL : https://patchwork.freedesktop.org/series/51011/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5054 -> Patchwork_10650 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10650 absolu
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