On 10/15/2018 7:57 PM, Jani Nikula wrote:
Encoders are not alike, make enable and disable hooks optional like
other hooks. Utilize this in DSI code, and remove the silly nop hook.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 6 --
drivers/gpu/drm/i915/vlv_dsi.c
== Series Details ==
Series: Refactor and Add helper function for combophy/tc ports (rev5)
URL : https://patchwork.freedesktop.org/series/50484/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4984_full -> Patchwork_10467_full =
== Summary - WARNING ==
Minor unknown change
== Series Details ==
Series: Refactor and Add helper function for combophy/tc ports (rev5)
URL : https://patchwork.freedesktop.org/series/50484/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4984 -> Patchwork_10467 =
== Summary - SUCCESS ==
No regressions found.
Exter
== Series Details ==
Series: drm/atomic_helper: Stop modesets on unregistered connectors harder
URL : https://patchwork.freedesktop.org/series/51041/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4984 -> Patchwork_10466 =
== Summary - FAILURE ==
Serious unknown changes c
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix power domain reference balance
when DMC firmware is not present
URL : https://patchwork.freedesktop.org/series/51039/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4984_full -> Patchwork_10465_full =
==
== Series Details ==
Series: Refactor and Add helper function for combophy/tc ports (rev5)
URL : https://patchwork.freedesktop.org/series/50484/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7a0475e44ad4 drm/i915/icl: create function to identify combophy port
99f69dd6d4e8 drm/i
Regards
Shashank
On 10/13/2018 12:58 AM, Ville Syrjälä wrote:
On Fri, Oct 12, 2018 at 10:17:57PM +0300, Ville Syrjälä wrote:
On Sat, Oct 13, 2018 at 12:26:57AM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 10/13/2018 12:08 AM, Ville Syrjala wrote:
From: Ville Syrjälä
The Parade LS
Regards
Shashank
On 10/13/2018 12:47 AM, Ville Syrjälä wrote:
On Sat, Oct 13, 2018 at 12:26:57AM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 10/13/2018 12:08 AM, Ville Syrjala wrote:
From: Ville Syrjälä
The Parade LSPCON on KBL NUCs forgets to turn off scrambling/bit clock
rate w
From: Mahesh Kumar
DDI/TC clock-off bits are not equally distanced. TC1-3 bits are
from offset 12 & TC4 is at offset 21.
Create a function to choose correct clk-off bit.
v2: Add fixes tag (Lucas)
Fixes: c27e917e2bda ("drm/i915/icl: add basic support for the ICL clocks")
Signed-off-by: Mahesh Ku
combo-phy register instances are at same offset from base for each
combo-phy port, i.e.
Port A base offset: 0x16200
Port B base offset: 0x6C000
All the other addresses for both ports can be derived by calculating
offset to these base addresses.
PORT_CL_DW_OFFSET 0x0
PORT_CL_DW 0
Unfortunately, it appears our fix in:
commit b5d29843d8ef ("drm/atomic_helper: Allow DPMS On<->Off changes
for unregistered connectors")
Which attempted to work around the problems introduced by:
commit 4d80273976bf ("drm/atomic_helper: Disallow new modesets on
unregistered connectors")
Is still
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix power domain reference balance
when DMC firmware is not present
URL : https://patchwork.freedesktop.org/series/51039/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4984 -> Patchwork_10465 =
== Summary -
On Mon, 2018-10-15 at 13:58 +0300, Imre Deak wrote:
> On Fri, Oct 12, 2018 at 02:52:15PM -0700, José Roberto de Souza
> wrote:
> > When DMC firmware is not loaded, it return earlier in
> > gen9_dc_off_power_well_disable() as it will have no effect without
> > DMC firmware loaded. But it will cause
When DMC firmware is not loaded, it return earlier in
gen9_dc_off_power_well_disable() as it will have no effect without
DMC firmware loaded. But it will cause a mismatch state error when
running intel_power_domains_verify_state(), so skipping this error
in this case.
Cc: Imre Deak
Signed-off-by:
intel_csr_ucode_init() gets a POWER_DOMAIN_INIT reference but it is
only released in csr_load_work_fn() if DMC firmware is present in
filesystem, keeping a reference to POWER_DOMAIN_INIT and every power
well enabled all the times.
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
---
drivers/g
Ville/Jani,
Could you please look at the logistics of the patch and ACK this?
This has been validated and tested on the DSC panel.
Regards
Manasi
On Fri, Oct 05, 2018 at 04:22:54PM -0700, Manasi Navare wrote:
> From: Gaurav K Singh
>
> This patches does the following:
>
> 1. This patch define
Hi Jani,
This patch has a verbal ACK from you when we went over the patch together,
This is rebased on top of edp fast/narrow optimized config like we discussed.
could you please review this?
Regards
Manasi
On Fri, Oct 05, 2018 at 04:22:51PM -0700, Manasi Navare wrote:
> DSC params like the enab
== Series Details ==
Series: drm/i915: Silence build error with UBSAN
URL : https://patchwork.freedesktop.org/series/51025/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4983_full -> Patchwork_10462_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwo
Hi Jani,
This patch adds the cpu_to_be16 macro and removes the bitfields and
uses macros instead for packing the infoframe as per your feedback
on the previous version of the patch.
Could you please review this patch?
Regards
Manasi
On Fri, Oct 05, 2018 at 04:22:49PM -0700, Manasi Navare wrote:
Hi Ville,
This adds a helper function to get the power well as per
the transcoder as per your suggestion.
Could you please review this one?
Regards
Manasi
On Fri, Oct 05, 2018 at 04:23:04PM -0700, Manasi Navare wrote:
> A separate power well 2 (PG2) is required for VDSC on eDP transcoder
> where
Hi Imre/Ville,
This patch adds the power domain as per our discussion and feedback
on previous patch set.
Could you please take a look at this?
Manasi
On Fri, Oct 05, 2018 at 04:22:57PM -0700, Manasi Navare wrote:
> On Icelake, a separate power well PG2 is created for
> VDSC engine used for eDP
On Mon, 2018-10-15 at 14:06 +0300, Imre Deak wrote:
> On Fri, Oct 12, 2018 at 02:52:17PM -0700, José Roberto de Souza
> wrote:
> > Just not enable power wells is not enough as BIOS/firmware can turn
> > on some power wells during boot, so is needed disable those to save
> > power and to avoid misma
== Series Details ==
Series: drm/i915/gen11: Preempt-to-idle support in execlists. (rev7)
URL : https://patchwork.freedesktop.org/series/40747/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4982_full -> Patchwork_10461_full =
== Summary - FAILURE ==
Serious unknown chang
On Mon, 2018-10-15 at 12:14 +0100, Chris Wilson wrote:
> Quoting José Roberto de Souza (2018-10-12 22:52:04)
> > i915_load_modeset_init() and intel_modeset_cleanup() was
> > initializing
> > and cleaning up things that is not related to display or modeset.
> > This changes will make easy initialize
On 15/10/18 15:47, Patchwork wrote:
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: fix GuC suspend/resume
URL : https://patchwork.freedesktop.org/series/51033/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4984 -> Patchwork_10464 =
== Summary - FA
== Series Details ==
Series: drm/i915/perf: Add OA buffer size uAPI parameter (rev3)
URL : https://patchwork.freedesktop.org/series/50810/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4982_full -> Patchwork_10460_full =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: fix GuC suspend/resume
URL : https://patchwork.freedesktop.org/series/51033/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4984 -> Patchwork_10464 =
== Summary - FAILURE ==
Serious unknown changes comi
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: fix GuC suspend/resume
URL : https://patchwork.freedesktop.org/series/51033/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4454d4d05ce3 drm/i915/guc: fix GuC suspend/resume
c88fb110ee82 HAX enable GuC for CI
== Series Details ==
Series: Forward Error Correction (rev2)
URL : https://patchwork.freedesktop.org/series/47848/
State : failure
== Summary ==
Applying: i915/dp/fec: Cache the FEC_CAPABLE DPCD register
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_dp.c).
error: co
The ENTER/EXIT_S_STATE actions queue the save/restore operation in GuC
FW and then return, so waiting on the H2H is not enough to guarantee
GuC is done.
When all the processing is done, GuC writes 0 to scratch register 14,
so we can poll on that. Note that GuC does not ensure that the value
in the
From: Michal Wajdeczko
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 7e56c516c815..c681537bcb92 100644
--- a/drivers/gpu/dr
On Mon, Oct 15, 2018 at 02:50:32PM -0700, Anusha Srivatsa wrote:
> Similar to DSC DPCD registers, let us cache
> FEC_CAPABLE register to avoid using stale
> values. With this we can avoid aux reads
> everytime and instead read the cached values.
>
> Suggested-by: Jani Nikula
> Cc: Jani Nikula
>
If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.
The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is already active while enabling
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/
With Display Compression, the bit error in the pixel
stream can turn into a significant corruption on
the screen. The DP1.4 adds FEC - Forward Error Correction
scheme which uses Reed-Solomon parity/correction check
generated by the source and used by the sink to detect
and correct small numbers of
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
Check if the sink supports FEC using the helper.
v2: Mention External DP where ever FEC is mentioned
in the code.Check return status of dpcd reads. (Gaurav)
- Do regular mode check ev
DP 1.4 has Forward Error Correction Support(FEC).
Add helper function to check if the sink device
supports FEC.
v2: Separate the helper and the code that uses the helper into
two separate patches. (Manasi)
v3:
- Move the code to drm_dp_helper.c (Manasi)
- change the return type, code style change
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased.
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc
Similar to DSC DPCD registers, let us cache
FEC_CAPABLE register to avoid using stale
values. With this we can avoid aux reads
everytime and instead read the cached values.
Suggested-by: Jani Nikula
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
driver
On Wed, Oct 03, 2018 at 12:51:56PM +0530, Mahesh Kumar wrote:
> This patch creates a function/wrapper to check if port is combophy port
> instead of explicitly comparing ports.
>
> Signed-off-by: Mahesh Kumar
> Cc: Madhav Chauhan
> Cc: Manasi Navare
Looks good to me.
Reviewed-by: Manasi Navar
On Fri, 2018-10-05 at 09:05 +0100, Chris Wilson wrote:
> If KMS is not available, we cannot simply turn on an output and
> expect
> that to wake the device up. As such we have to ignore that part of
> the
> basic subtest and simply proclaim victory if the device is able to
> sleep!
We could replac
On 15/10/18 12:23, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2018-10-15 19:33:26)
On 14/10/18 10:02, Chris Wilson wrote:
Seems like there's a missing ack before the guc is ready for commands.
I'm assuming you're running without HuC since the HuC auth H2G comes
before this one.
On Mon, 2018-10-15 at 14:20 -0700, Rodrigo Vivi wrote:
> On Mon, Oct 15, 2018 at 03:59:36PM -0400, Lyude Paul wrote:
> > Poke: still wondering what we should do about the patch in these fixes
> > that
> > came up a little later which got Cc'd to stable, despite it apparently not
> > being a patch w
On Mon, Oct 15, 2018 at 03:59:36PM -0400, Lyude Paul wrote:
> Poke: still wondering what we should do about the patch in these fixes that
> came up a little later which got Cc'd to stable, despite it apparently not
> being a patch we want in stable (mentioned this over IRC):
>
> https://patchwork.
== Series Details ==
Series: drm/i915: Silence build error with UBSAN
URL : https://patchwork.freedesktop.org/series/51025/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4983 -> Patchwork_10462 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://pat
When I enable UBSAN and compile this driver with clang I get the
following build error:
drivers/gpu/drm/i915/intel_engine_cs.o: In function
`intel_engine_init_execlist':
drivers/gpu/drm/i915/intel_engine_cs.c:411: undefined reference to
`__compiletime_assert_411'
from what I can figure out, the
Poke: still wondering what we should do about the patch in these fixes that
came up a little later which got Cc'd to stable, despite it apparently not
being a patch we want in stable (mentioned this over IRC):
https://patchwork.freedesktop.org/patch/255428/ and
https://patchwork.freedesktop.org/se
Quoting Daniele Ceraolo Spurio (2018-10-15 19:33:26)
>
>
> On 14/10/18 10:02, Chris Wilson wrote:
> > Seems like there's a missing ack before the guc is ready for commands.
> >
>
> I'm assuming you're running without HuC since the HuC auth H2G comes
> before this one.
https://intel-gfx-ci.01.
On Mon, Oct 15, 2018 at 11:40:23AM +0200, Maarten Lankhorst wrote:
> has_drrs is a flag we can't read out. We set it when seamless DRRS is
> enabled in pipe_config, so intel_dump_pipe_config() and
> intel_pipe_config_compare() will continue to do the right thing when
> has_drrs is set on the real s
On Mon, Oct 15, 2018 at 04:59:57PM +0100, Lionel Landwerlin wrote:
> We initialize the OA buffer everytime we enable the OA unit (first call in
> gen[78]_oa_enable), so we don't need to initialize when preparing the metric
> set.
>
> Signed-off-by: Lionel Landwerlin
> Reviewed-by: Matthew Auld
On Mon, Oct 15, 2018 at 04:59:56PM +0100, Lionel Landwerlin wrote:
> Lucas submitted a patch to generator script, so just reflecting the
> change here.
>
> Signed-off-by: Lionel Landwerlin
Reviewed-by: Lucas De Marchi
thanks
Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_oa_bdw.c| 27
On 14/10/18 10:02, Chris Wilson wrote:
Seems like there's a missing ack before the guc is ready for commands.
I'm assuming you're running without HuC since the HuC auth H2G comes
before this one.
What we're polling to indicate load completion (GS_UKERNEL_READY) is
definitely what the firmw
== Series Details ==
Series: drm/i915/gen11: Preempt-to-idle support in execlists. (rev7)
URL : https://patchwork.freedesktop.org/series/40747/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4982 -> Patchwork_10461 =
== Summary - SUCCESS ==
No regressions found.
Extern
== Series Details ==
Series: series starting with [1/3] drm/i915/gen8: Disable master intr before
reading
URL : https://patchwork.freedesktop.org/series/51009/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4981_full -> Patchwork_10458_full =
== Summary - WARNING ==
Mino
== Series Details ==
Series: drm/i915/gen11: Preempt-to-idle support in execlists. (rev7)
URL : https://patchwork.freedesktop.org/series/40747/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Preempt-to-idle support in execlists.
-drivers/
== Series Details ==
Series: drm/i915/gen11: Preempt-to-idle support in execlists. (rev7)
URL : https://patchwork.freedesktop.org/series/40747/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
40f273c57c71 drm/i915/icl: Preempt-to-idle support in execlists.
-:129: CHECK:COMPARISON
On 15/10/18 07:14, Mika Kuoppala wrote:
Disable master interrupt before reading level indications.
This will close a race where we get a level indication between
reading and disabling, generating an extra interrupt where we
could have avoided one.
Further, as the reading acts also as a post, r
== Series Details ==
Series: drm/i915/perf: Add OA buffer size uAPI parameter (rev3)
URL : https://patchwork.freedesktop.org/series/50810/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4982 -> Patchwork_10460 =
== Summary - SUCCESS ==
No regressions found.
External UR
The patch adds support of preempt-to-idle requesting by setting a proper
bit within Execlist Control Register, and receiving preemption result from
Context Status Buffer.
Preemption in previous gens required a special batch buffer to be executed,
so the Command Streamer never preempted to idle dir
== Series Details ==
Series: drm/i915/perf: Add OA buffer size uAPI parameter (rev3)
URL : https://patchwork.freedesktop.org/series/50810/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/perf: update generated files headers
Okay!
Commit: drm/i
== Series Details ==
Series: drm/i915/perf: Add OA buffer size uAPI parameter (rev3)
URL : https://patchwork.freedesktop.org/series/50810/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
766560106b0d drm/i915/perf: update generated files headers
88da93631a80 drm/i915/perf: remove
== Series Details ==
Series: drm/i915: Hold rpm wakeref for debugfs/i915_drop_caches_set
URL : https://patchwork.freedesktop.org/series/51001/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4980_full -> Patchwork_10457_full =
== Summary - WARNING ==
Minor unknown changes
On Fri, Oct 12, 2018 at 03:58:52PM -0700, Lucas De Marchi wrote:
> On Fri, Oct 12, 2018 at 03:25:37PM -0700, Rodrigo Vivi wrote:
> > On Wed, Oct 03, 2018 at 12:52:02PM +0530, Mahesh Kumar wrote:
> > > From: Lucas De Marchi
> > >
> > > combo-phy register instances are at same offset from base for
On 10/15/2018 06:41 AM, Ville Syrjälä wrote:
On Fri, Oct 12, 2018 at 01:14:45PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Initialize SCDC Source Version and TDMS_Config_0 registers to nominal
values during intel_hdmi_detect(). The i915 driver currently doesn't
implement fea
On Tue, Jun 12, 2018 at 06:20:35PM +0200, Mario Kleiner wrote:
> The various clut handling functions like a setup
> consistent with the x-screen color depth. Otherwise
> we observe improper sampling in the gamma tables
> at depth 30.
>
> Therefore replace hard-coded bitsPerRGB = 8 by actual
> bits
> On Wed, Oct 10, 2018 at 05:16:43PM -0700, Deepak Rawat wrote:
> > Selftest for drm damage helper iterator functions.
> >
> > Cc: ville.syrj...@linux.intel.com
> > Cc: Daniel Vetter
> > Cc: Pekka Paalanen
> > Cc: Daniel Stone
> > Cc: intel-gfx@lists.freedesktop.org
> > Cc: igt-...@lists.freedes
Lucas submitted a patch to generator script, so just reflecting the
change here.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_oa_bdw.c| 27 ---
drivers/gpu/drm/i915/i915_oa_bdw.h| 27 ---
drivers/gpu/drm/i915/i915_oa_bxt.c
We initialize the OA buffer everytime we enable the OA unit (first call in
gen[78]_oa_enable), so we don't need to initialize when preparing the metric
set.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 17 -
drivers/gpu/drm/i9
The way our hardware is designed doesn't seem to let us use the
MI_RECORD_PERF_COUNT command without setting up a circular buffer.
In the case where the user didn't request OA reports to be available
through the i915 perf stream, we can set the OA buffer to the minimum
size to avoid consuming memo
We want to use some of the properties of the perf stream to program
the hardware in a later commit.
v2: Pass only perf stream as argument (Matthew)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++---
drivers/gpu/drm/i915/i915_perf.c | 43
Hi all,
Chris recommended we stick on what the HW can do with regard to the
buffer size parameter. This is reflected in the update of patch 4.
Added patch 1 which was requested for newer test config files by
Lucas. I figured we could update the existing files too.
Cheers,
Lionel Landwerlin (4):
== Series Details ==
Series: drm/i915/icl: dsi enabling
URL : https://patchwork.freedesktop.org/series/51011/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4981 -> Patchwork_10459 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10459 absolutely ne
== Series Details ==
Series: drm/i915/icl: dsi enabling
URL : https://patchwork.freedesktop.org/series/51011/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: make encoder enable and disable hooks optional
Okay!
Commit: drm/i915/dsi: refactor
== Series Details ==
Series: drm/i915/icl: dsi enabling
URL : https://patchwork.freedesktop.org/series/51011/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b12abf6e31c4 drm/i915: make encoder enable and disable hooks optional
1a879a6d5120 drm/i915/dsi: refactor bitrate calculat
== Series Details ==
Series: series starting with [1/3] drm/i915/gen8: Disable master intr before
reading
URL : https://patchwork.freedesktop.org/series/51009/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4981 -> Patchwork_10458 =
== Summary - SUCCESS ==
No regressions
Regards
Shashank
On 10/15/2018 4:39 PM, Jani Nikula wrote:
On Mon, 15 Oct 2018, Jani Nikula wrote:
On Fri, 05 Oct 2018, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
HDMI Forum VSDB YCBCR420 deep color capability bits are 2:0. Correct
definitions in the header for the mask to work
From: Madhav Chauhan
This patch execute poweron, deassert reset, display on
VBT sequences and send TURN_ON DSI command to panel for
powering it up.
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 7 +++
1 file changed, 7 insertions(+)
diff --
From: Madhav Chauhan
This patch defines DSI_CMD_RXCTL, DSI_CMD_TXCTL registers,
bitfields, masks and macros used for configuring DSI panel.
v2: Define remaining bitfields
v3 by Jani:
- Alignment fix
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.
From: Madhav Chauhan
Driver needs payload/header credits for sending any command
and data over DSI link. These credits are released once command
or data sent to link. This patch adds functions to wait for releasing
of payload and header credits.
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani
From: Madhav Chauhan
As per BSPEC, driver needs to ensure that all of commands/data
has been dispatched to panel before the transcoder is enabled.
This patch implement those steps i.e. sending NOP DCS command,
wait for header/payload credit to be released etc.
Signed-off-by: Madhav Chauhan
Sign
From: Madhav Chauhan
This patch enables backlight of DSI panel by using VBT
BACKLIGHT_ON sequence and panel specific functions.
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm
From: Madhav Chauhan
This patch programs maximum size of the payload transmitted
from peripheral back to the host processor using short packet
as a part of panel programming.
v2: Rebase
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
FIXME: Looks like this is storing sw state i
From: Madhav Chauhan
This patch enables DSI transcoders by writing to
TRANS_CONF registers and wait for its state to be enabled.
v2 by Jani:
- Rebase
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 25 +
1 file changed, 2
From: Madhav Chauhan
This patch defines TRANS_CONF registers for DSI ports
0 and 1. Bitfields of these registers used for enabling
and reading the current state of transcoder.
v2: Add blank line before comment
v3 by Jani:
- Move DSI specific .pipe_offsets to GEN11_FEATURES
- Macro placement a
From: Madhav Chauhan
This patch select input PIPE for DSI, data lanes width,
enable port sync mode and wait for DSI link to become ready.
v2 by Jani:
- Use MISSING_CASE with fallthrough instead of DRM_ERROR
- minor stylistic changes
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
-
From: Madhav Chauhan
As part of DSI enable sequence, transcoder timings
(horizontal & vertical) need to be set so that transcoder
will generate the stream output as per those timings.
This patch set required transcoder timings as per BSPEC.
v2: Remove TRANS_TIMING_SHIFT usage
v3 by Jani:
- Reb
From: Madhav Chauhan
This patch defines registers and bitfields used for
programming DSI transcoder's horizontal and vertical
timings.
v2: Remove TRANS_TIMING_SHIFT definition
v3 by Jani:
- Group macros by transcoder
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/
From: Madhav Chauhan
This patch defines TRANS_DDI_FUNC_CTL and TRANS_DDI_FUNC_CTL2
registers and their bitfields for DSI. These registers are used
for enabling port sync mode, input pipe select, data lane width
configuration etc.
v2: Changes:
- Remove redundant extra line
- Correct some
Regards
Shashank
On 10/15/2018 6:42 PM, Jani Nikula wrote:
On Fri, 12 Oct 2018, Ville Syrjälä wrote:
On Sat, Oct 13, 2018 at 12:02:25AM +0530, Sharma, Shashank wrote:
+void lspcon_ycbcr420_config(struct drm_connector *connector,
+ struct intel_crtc_state *crtc_stat
From: Madhav Chauhan
This patch defines transcoder function configuration
registers and its bitfields for both DSI ports.
Used while programming/enabling DSI transcoder.
v2: Changes (Jani N)
- Define _SHIFT and _MASK for bitfields
- Define values for fields already shifted in place
v3 b
From: Madhav Chauhan
This patch programs DSI operation mode, pixel format,
BGR info, link calibration etc for the DSI transcoder.
This patch also extract BGR info of the DSI panel from
VBT and save it inside struct intel_dsi which used for
configuring DSI transcoder.
v2: Rebase
v3: Use newly def
From: Madhav Chauhan
This patch adds _MMIO_DSI macros for accessing DSI
transcoder registers.
v2: Use _MMIO_TRANS() (Ville)
Credits-to: Jani N
Cc: Jani Nikula
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 4
1
From: Madhav Chauhan
This patch adds a helper function to retrieve DSI
transcoder for a given DSI port using newly defined
enum names for DSI transcoders.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 8
intel_dsi_vbt_init() has grown too unwieldy, and it's about to be
modified due to ICL DSI. Abstract out the VLV specific dphy param
init. No functional changes. Intentionally no stylistic changes during
code movement.
Cc: Madhav Chauhan
Cc: Ville Syrjala
Signed-off-by: Jani Nikula
---
drivers/
From: Madhav Chauhan
This patch programs D-PHY timing parameters for the
bus turn around flow(in escape clocks) only if dsi link
frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
identical register DSI_TA_TIMING_PARAM (inside DSI
Controller within the Display Core).
v2: Changes
- Don't
From: Madhav Chauhan
This patch moves couple of legacy DSI functions to header and common DSI
files so that they can be re-used by Gen11 DSI. No functional change.
v2 by Jani:
- Move intel_dsi_msleep() to intel_dsi_vbt.c
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/g
Abstract bitrate calculation to a newly resurrected intel_dsi.c file
that will contain common code for VLV and ICL DSI.
No functional changes.
Cc: Madhav Chauhan
Cc: Ville Syrjala
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/intel_dsi.c
The v7 is a bit misleading, but it's essentially the next version of
[1], embedding my review into the commits directly. This is the first
batch from me, and there's more to come.
The new patches that I've added naturally need review.
The patches I've changed need approval from Madhav. I think tw
From: Madhav Chauhan
This patch programs D-PHY timing parameters for the
clock and data lane (in escape clocks) of DSI
controller (DSI port 0 and 1).
These programmed timings would be used by DSI Controller
to calculate link transition latencies of the data and
clock lanes.
v2: Use newly defined
Will be needed in the future. No functional changes.
Cc: Madhav Chauhan
Cc: Ville Syrjala
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 13 +
drivers/gpu/drm/i915/intel_dsi.h | 1 +
drivers/gpu/drm/i915/intel_dsi_vbt.c | 16 +---
3 files cha
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