Similar to DSC DPCD registers, let us cache
FEC_CAPABLE register to avoid using stale
values. With this we can avoid aux reads
everytime and instead read the cached values.

Suggested-by: Jani Nikula <jani.nik...@linux.intel.com>
Cc: Jani Nikula <jani.nik...@linux.intel.com>
Cc: Ville Syrjala <ville.syrj...@linux.intel.com>
Cc: Manasi Navare <manasi.d.nav...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 8 ++++++++
 drivers/gpu/drm/i915/intel_drv.h | 1 +
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dcc5a207fcbd..8a0e0a0b26f6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4163,8 +4163,10 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp 
*intel_dp)
        /*
         *Clear the cached register set to avoid using stale values
         * for the sinks that do not support DSC.
+        * Similarly, clear the cached FEC register.
         */
        memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
+       memset(intel_dp->fec_dpcd, 0, sizeof(intel_dp->fec_dpcd));
 
        /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
        if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
@@ -4179,6 +4181,12 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp 
*intel_dp)
                              (int)sizeof(intel_dp->dsc_dpcd),
                              intel_dp->dsc_dpcd);
        }
+       /* FEC is supported only on DP 1.4 */
+       if (!intel_dp_is_edp(intel_dp) && intel_dp->dpcd[DP_DPCD_REV] >= 0x14) {
+               if (drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
+                                     intel_dp->fec_dpcd) < 0)
+                       DRM_ERROR("Failed to read FEC DPCD register\n");
+       }
 }
 
 static bool
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7b4af8cba279..b87ea052c9ca 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1086,6 +1086,7 @@ struct intel_dp {
        uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
        uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
        u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
+       u8 fec_dpcd[1];
        /* source rates */
        int num_source_rates;
        const int *source_rates;
-- 
2.17.1

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