== Series Details ==
Series: series starting with [01/16] drm/i915: Properly set PCH as NOP when
display is disabled
URL : https://patchwork.freedesktop.org/series/50962/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4978_full -> Patchwork_10450_full =
== Summary - WARNING
== Series Details ==
Series: drm/i915/hdmi: Initialize SCDC registers according to spec
URL : https://patchwork.freedesktop.org/series/50955/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4978_full -> Patchwork_10449_full =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: Refactor and Add helper function for combophy/tc ports (rev3)
URL : https://patchwork.freedesktop.org/series/50484/
State : failure
== Summary ==
Applying: drm/i915/icl: create function to identify combophy port
Using index info to reconstruct a base tree...
M
From: Mahesh Kumar
This patch combines CNL/ICL specific port/combophy macros together
at one location. This is prework for patches later in series where
new macros to find port/combophy register will be introduced.
v2: remove wrong empty line
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De
== Series Details ==
Series: /drm/i915/hdmi: SCDC Scrambling enable without CTS mode (rev2)
URL : https://patchwork.freedesktop.org/series/50648/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4978_full -> Patchwork_10448_full =
== Summary - FAILURE ==
Serious unknown cha
On Fri, Oct 12, 2018 at 03:25:37PM -0700, Rodrigo Vivi wrote:
> On Wed, Oct 03, 2018 at 12:52:02PM +0530, Mahesh Kumar wrote:
> > From: Lucas De Marchi
> >
> > combo-phy register instances are at same offset from base for each
> > combo-phy port, i.e.
> >
> > Port A base offset: 0x16200
> > Port
== Series Details ==
Series: drm/i915/icl: apply Display WA #1178 to fix type C dongles (rev2)
URL : https://patchwork.freedesktop.org/series/50102/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4978 -> Patchwork_10451 =
== Summary - SUCCESS ==
No regressions found.
E
== Series Details ==
Series: drm/i915/lspcon: Fix Parade LSPCON scrambling fail (rev2)
URL : https://patchwork.freedesktop.org/series/50950/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4978_full -> Patchwork_10447_full =
== Summary - WARNING ==
Minor unknown changes co
On Fri, Oct 12, 2018 at 02:57:58PM -0700, Lucas De Marchi wrote:
> Display WA #1178 is meant to fix Aux channel voltage swing too low with
> some type C dongles. It applies to external ports on combo phy. On
> Icelake this is port A and B when those are not eDP.
>
> v2: follow the spec to the lett
== Series Details ==
Series: series starting with [01/16] drm/i915: Properly set PCH as NOP when
display is disabled
URL : https://patchwork.freedesktop.org/series/50962/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4978 -> Patchwork_10450 =
== Summary - WARNING ==
Min
On Wed, Oct 03, 2018 at 12:52:02PM +0530, Mahesh Kumar wrote:
> From: Lucas De Marchi
>
> combo-phy register instances are at same offset from base for each
> combo-phy port, i.e.
>
> Port A base offset: 0x16200
> Port B base offset: 0x6C000
>
> All the other addresses for both ports can be der
On Wed, Oct 03, 2018 at 12:52:01PM +0530, Mahesh Kumar wrote:
> This patch combines CNL/ICL specific port/combophy macros together
> at one location. This is prework for patches later in series where
> new macros to find port/combophy register will be introduced.
>
> Signed-off-by: Mahesh Kumar
>
== Series Details ==
Series: series starting with [01/16] drm/i915: Properly set PCH as NOP when
display is disabled
URL : https://patchwork.freedesktop.org/series/50962/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Properly set PCH as NOP
== Series Details ==
Series: series starting with [01/16] drm/i915: Properly set PCH as NOP when
display is disabled
URL : https://patchwork.freedesktop.org/series/50962/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
06503ffcb9ca drm/i915: Properly set PCH as NOP when display
Display WA #1178 is meant to fix Aux channel voltage swing too low with
some type C dongles. It applies to external ports on combo phy. On
Icelake this is port A and B when those are not eDP.
v2: follow the spec to the letter: include Aux A and just check if it's
not eDP instead of checking on
== Series Details ==
Series: series starting with [v14,1/2] drm: Add connector property to limit max
bpc
URL : https://patchwork.freedesktop.org/series/50951/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4978_full -> Patchwork_10446_full =
== Summary - SUCCESS ==
No re
This 'if's will always be false because of previous changes so let's
drop then.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 12 +++-
drivers/gpu/drm/i915/intel_bios.c| 5 -
drivers/gpu/drm/i915/intel_display.c | 3 ---
drivers/gpu/drm/i915/in
Display is always disabled and enabled when reseting any engine,
but if display is disabled it should not do anything with display
and only reset the needed engines.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_irq.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(
All other overlay functions(almost all other functions in i915)
follow intel_overlay_verb, so renaming overlay ones that do not match
that.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/inte
Just not enable power wells is not enough as BIOS/firmware can turn
on some power wells during boot, so is needed disable those to save
power and to avoid mismatch state errors in
intel_power_domains_verify_state().
So here disabling every non-real power well first as it could have
some dependency
With display disabled, driver don't need to enable any power well
or load the DMC firmware.
The only thing that *_display_core_init will do when display is
disabled is call intel_pch_reset_handshake(), so PCH handshake
will be unset and in counterpart *_display_core_uninit() will
only disable DC.
When DMC firmware is not loaded, it return earlier in
gen9_dc_off_power_well_disable() as it will have no effect without
DMC firmware loaded. But it will cause a mismatch state error when
running intel_power_domains_verify_state(), so skipping this error
in this case.
Signed-off-by: José Roberto d
i915_load_modeset_init() and intel_modeset_cleanup() was initializing
and cleaning up things that is not related to display or modeset.
This changes will make easy initialize driver without display block.
Also moving VLV/CHV/BYT czclk as it is a core clock used as base by
several other GPU blocks
There is just two power wells calls left after the previous changes:
- POWER_DOMAIN_INIT: used in load, unload, resume and suspend driver
paths
- POWER_DOMAIN_GT_IRQ: used by GEM to reduce interrupt latencies when
DMC is loaded
Instead of adding several more 'if (INTEL_INFO(dev_priv)->num_pipes)'
i915_load_modeset_init() is a more suitable place than
i915_driver_load() as vblank is part of modeset.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv
Without this checks in this debugfs, it would try access memory and
resorces from display causing the driver to crash.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_debugfs.c | 64 +
1 file changed, 64 insertions(+)
diff --git a/drivers/gpu/drm/i
IPC is a display feature, so i915_load_modeset_init() is the right
place to initialize it.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_
Although FBC helps save power it do not belongs to power management
also the cleanup was placed in i915_driver_unload() also not a good
place. intel_modeset_init()/intel_modeset_cleanup() are better places
also this will help make easy disable features that depends in
display being enabled in drive
cdclk and rawclk are the 2 display clocks that can now be completed
not initialized when display is disabled.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 9 ++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 27 +
2 files changed,
num_pipes is set to 0 if disable_display is set inside
intel_device_info_runtime_init() but when that happen PCH will
already be set in intel_detect_pch().
i915_driver_load()
i915_driver_init_early()
...
intel_detect_pch()
...
...
Display features should not be initialized or deinitialized when
display is disabled.
With this changes no plane, CRTC, encoder or connector
is being registered in drm when display is disabled so it was also
necessary unset DRIVER_MODESET and DRIVER_ATOMIC features from driver
otherwise it will cr
With previous changes none of those warnings will be printed but lets
add then so CI can caught regressions.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_irq.c | 18 ++
drivers/gpu/drm/i915/intel_hotplug.c | 2 ++
2 files changed, 20 insertions(+)
dif
On Fri, Oct 12, 2018 at 02:33:26PM -0700, Jeff McGee wrote:
> On Fri, Oct 12, 2018 at 01:51:46PM -0700, Rodrigo Vivi wrote:
> > On Fri, Oct 12, 2018 at 01:24:30PM -0700, Jeff McGee wrote:
> > > The GuC firmware team is proposing a change to the firmware versioning
> > > scheme.
> > > The goal is t
Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.19-rc7 next-20181012]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com
On Fri, Oct 12, 2018 at 01:51:46PM -0700, Rodrigo Vivi wrote:
> On Fri, Oct 12, 2018 at 01:24:30PM -0700, Jeff McGee wrote:
> > The GuC firmware team is proposing a change to the firmware versioning
> > scheme.
> > The goal is to more accurately track the firmware interface to help users
> > manag
On Fri, Oct 12, 2018 at 01:24:30PM -0700, Jeff McGee wrote:
> The GuC firmware team is proposing a change to the firmware versioning scheme.
> The goal is to more accurately track the firmware interface to help users
> manage dependencies on that interface. The proposed scheme is based on
> semver.
Forgot to add some people on CC.
On Fri, Oct 12, 2018 at 01:24:30PM -0700, Jeff McGee wrote:
> The GuC firmware team is proposing a change to the firmware versioning scheme.
> The goal is to more accurately track the firmware interface to help users
> manage dependencies on that interface. The pro
== Series Details ==
Series: drm/i915/hdmi: Initialize SCDC registers according to spec
URL : https://patchwork.freedesktop.org/series/50955/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4978 -> Patchwork_10449 =
== Summary - SUCCESS ==
No regressions found.
External
The GuC firmware team is proposing a change to the firmware versioning scheme.
The goal is to more accurately track the firmware interface to help users
manage dependencies on that interface. The proposed scheme is based on
semver.org with some additions to handle branching.
The proposed version n
From: Clint Taylor
Initialize SCDC Source Version and TDMS_Config_0 registers to nominal
values during intel_hdmi_detect(). The i915 driver currently doesn't
implement features that require polling of the status update bits. Once
FRL, DSC, or Source Test is enabled in the driver the status flags
== Series Details ==
Series: /drm/i915/hdmi: SCDC Scrambling enable without CTS mode (rev2)
URL : https://patchwork.freedesktop.org/series/50648/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4978 -> Patchwork_10448 =
== Summary - SUCCESS ==
No regressions found.
Exte
== Series Details ==
Series: drm/i915/lspcon: Fix Parade LSPCON scrambling fail (rev2)
URL : https://patchwork.freedesktop.org/series/50950/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4978 -> Patchwork_10447 =
== Summary - SUCCESS ==
No regressions found.
External
On Fri, Oct 12, 2018 at 10:17:57PM +0300, Ville Syrjälä wrote:
> On Sat, Oct 13, 2018 at 12:26:57AM +0530, Sharma, Shashank wrote:
> > Regards
> >
> > Shashank
> >
> >
> > On 10/13/2018 12:08 AM, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > The Parade LSPCON on KBL NUCs forgets to
On Sat, Oct 13, 2018 at 12:26:57AM +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 10/13/2018 12:08 AM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The Parade LSPCON on KBL NUCs forgets to turn off scrambling/bit clock
> > rate when switching from a mode that needs them
== Series Details ==
Series: series starting with [v14,1/2] drm: Add connector property to limit max
bpc
URL : https://patchwork.freedesktop.org/series/50951/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4978 -> Patchwork_10446 =
== Summary - SUCCESS ==
No regressions
From: Clint Taylor
Setting the SCDC scrambling CTS mode causes HDMI Link Layer protocol tests
HF1-12 and HF1-13 to fail.
V2: Removed "Source Shall" entries to a new patch
Cc: Ville Syrjälä
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107895
Bugzilla: https://bugs.freedesktop.org/show_
== Series Details ==
Series: drm/i915: Assert intel_wait and its rb_node are complimentary
URL : https://patchwork.freedesktop.org/series/50934/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4978_full -> Patchwork_10441_full =
== Summary - WARNING ==
Minor unknown change
On Thu, Oct 04, 2018 at 11:29:36AM -0700, Radhakrishna Sripada wrote:
> From: Oscar Mateo
>
> Required to dinamically set 'Trilinear Filter Quality Mode'
>
> Cc: Mika Kuoppala
> Signed-off-by: Oscar Mateo
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/intel_workarounds.c
Regards
Shashank
On 10/13/2018 12:08 AM, Ville Syrjala wrote:
From: Ville Syrjälä
The Parade LSPCON on KBL NUCs forgets to turn off scrambling/bit clock
rate when switching from a mode that needs them to a mode that does
not. This manifests as a "no signal" on my TV when I try to go from
4k
On Thu, Oct 04, 2018 at 11:29:37AM -0700, Radhakrishna Sripada wrote:
> From: Oscar Mateo
>
> Required for Bindless samplers.
>
> Cc: Mika Kuoppala
> Signed-off-by: Oscar Mateo
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i9
From: Ville Syrjälä
The Parade LSPCON on KBL NUCs forgets to turn off scrambling/bit clock
rate when switching from a mode that needs them to a mode that does
not. This manifests as a "no signal" on my TV when I try to go from
4k to 1080p for example. Resetting the SCDC register bits with
i2cset
== Series Details ==
Series: series starting with [v14,1/2] drm: Add connector property to limit max
bpc
URL : https://patchwork.freedesktop.org/series/50951/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm: Add connector property to limit max bpc
== Series Details ==
Series: drm/i915/lspcon: Fix Parade LSPCON scrambling fail
URL : https://patchwork.freedesktop.org/series/50950/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/intel_hdm
Use the newly added "max bpc" connector property to limit pipe bpp.
V3: Use drm_connector_state to access the "max bpc" property
V4: Initialize the drm property, add suuport to DP(Ville)
V5: Use the property in the connector and fix CI failure(Ville)
V6: Use the core function to attach max_bpc pro
At times 12bpc HDMI cannot be driven due to faulty cables, dongles
level shifters etc. To workaround them we may need to drive the output
at a lower bpc. Currently the user space does not have a way to limit
the bpc. The default bpc to be programmed is decided by the driver and
is run against conne
From: Ville Syrjälä
The Parade LSPCON on KBL NUCs forgets to turn off scrambling/bit clock
rate when switching from a mode that needs them to a mode that does
not. This manifests as a "no signal" on my TV when I try to go from
4k to 1080p for example. Resetting the SCDC register bits with
i2cset
On Sat, Oct 13, 2018 at 12:02:25AM +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 10/12/2018 11:39 PM, Ville Syrjälä wrote:
> > On Fri, Oct 12, 2018 at 11:21:56PM +0530, Sharma, Shashank wrote:
> >> Regards
> >>
> >> Shashank
> >>
> >>
> >> On 10/12/2018 7:28 PM, Ville Syrjälä wr
Regards
Shashank
On 10/12/2018 11:39 PM, Ville Syrjälä wrote:
On Fri, Oct 12, 2018 at 11:21:56PM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 10/12/2018 7:28 PM, Ville Syrjälä wrote:
On Fri, Oct 12, 2018 at 11:53:14AM +0530, Shashank Sharma wrote:
From: Shashank Sharma
LSPCON chi
== Series Details ==
Series: drm/i915: Add Exec param to control data port coherency. (rev8)
URL : https://patchwork.freedesktop.org/series/40181/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4978_full -> Patchwork_10440_full =
== Summary - FAILURE ==
Serious unknown ch
With the new interface, GuC now requires every lrc to be registered in
one of the stage descriptors, which have been re-designed so that each
descriptor can store up to 64 lrc per class (i.e. equal to the possible
SW counter values).
Similarly to what happened with the previous legacy design, it is
On Fri, Oct 12, 2018 at 11:21:56PM +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 10/12/2018 7:28 PM, Ville Syrjälä wrote:
> > On Fri, Oct 12, 2018 at 11:53:14AM +0530, Shashank Sharma wrote:
> >> From: Shashank Sharma
> >>
> >> LSPCON chips can generate YCBCR outputs, if asked
Regards
Shashank
On 10/12/2018 7:28 PM, Ville Syrjälä wrote:
On Fri, Oct 12, 2018 at 11:53:14AM +0530, Shashank Sharma wrote:
From: Shashank Sharma
LSPCON chips can generate YCBCR outputs, if asked nicely :).
In order to generate YCBCR 4:2:0 outputs, a source must:
- send YCBCR 4:4:4 signa
On 12/10/18 06:50, Chris Wilson wrote:
Quoting Michal Wajdeczko (2018-10-12 14:26:09)
In function i915_gem_init_hw we are initializing some uC code that
i915_gem_init_hw really shouldn't be called such, at least it doesn't
fit in with the global init_hw phase. Suggestions for a clearer name
== Series Details ==
Series: drm/i915/guc: Clear preempt status before use (rev3)
URL : https://patchwork.freedesktop.org/series/50936/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4978 -> Patchwork_10444 =
== Summary - FAILURE ==
Serious unknown changes coming with Pat
== Series Details ==
Series: drm/i915/guc: Clear preempt status before use (rev3)
URL : https://patchwork.freedesktop.org/series/50936/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
769878ff15d5 drm/i915/guc: Clear preempt status before use
-:8: WARNING:COMMIT_MESSAGE: Missing
---
drivers/gpu/drm/i915/intel_guc_submission.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index eae668442ebe..e1d5463a04e6 100644
--- a/drivers/gpu/drm/i915/intel_guc_
== Series Details ==
Series: drm/i915/guc: Clear preempt status before use (rev2)
URL : https://patchwork.freedesktop.org/series/50936/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4978 -> Patchwork_10443 =
== Summary - SUCCESS ==
No regressions found.
External URL:
== Series Details ==
Series: drm/i915/guc: Clear preempt status before use (rev2)
URL : https://patchwork.freedesktop.org/series/50936/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9aca37eb0037 drm/i915/guc: Clear preempt status before use
-:8: WARNING:COMMIT_MESSAGE: Missing
---
drivers/gpu/drm/i915/intel_guc_submission.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index eae668442ebe..c257eceef862 100644
--- a/drivers/gpu/drm/i915/intel_guc_
== Series Details ==
Series: drm/i915/guc: Clear preempt status before use
URL : https://patchwork.freedesktop.org/series/50936/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4978 -> Patchwork_10442 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https:
== Series Details ==
Series: drm/i915: Large page offsets for pread/pwrite
URL : https://patchwork.freedesktop.org/series/50929/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4976_full -> Patchwork_10439_full =
== Summary - WARNING ==
Minor unknown changes coming with Pa
== Series Details ==
Series: drm/i915/guc: Clear preempt status before use
URL : https://patchwork.freedesktop.org/series/50936/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
61c98e4e5b38 drm/i915/guc: Clear preempt status before use
-:8: WARNING:COMMIT_MESSAGE: Missing commit
== Series Details ==
Series: drm/i915: Assert intel_wait and its rb_node are complimentary
URL : https://patchwork.freedesktop.org/series/50934/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4978 -> Patchwork_10441 =
== Summary - SUCCESS ==
No regressions found.
Exter
== Series Details ==
Series: drm/i915: Add Exec param to control data port coherency. (rev8)
URL : https://patchwork.freedesktop.org/series/40181/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4978 -> Patchwork_10440 =
== Summary - SUCCESS ==
No regressions found.
Ext
---
drivers/gpu/drm/i915/intel_guc_submission.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index eae668442ebe..4c45da01ea1c 100644
--- a/drivers/gpu/drm/i915/intel_guc_su
For convenience, we want to interchange intel_wait/rb_node and treat a
NULL rb_node as a NULL intel_wait and vice versa. Assert that the
rb_node is at offset 0 in the intel_wait to ensure this.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 1 +
1
== Series Details ==
Series: drm/i915: Add Exec param to control data port coherency. (rev8)
URL : https://patchwork.freedesktop.org/series/40181/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Add IOCTL Param to control data port coherency.
== Series Details ==
Series: drm/i915: Add Exec param to control data port coherency. (rev8)
URL : https://patchwork.freedesktop.org/series/40181/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2c32b051c0f7 drm/i915: Add IOCTL Param to control data port coherency.
-:15: WARNING:
== Series Details ==
Series: drm/i915: Introduce i915_gem_fini_hw for symmetry with i915_gem_init_hw
URL : https://patchwork.freedesktop.org/series/50928/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4976_full -> Patchwork_10438_full =
== Summary - WARNING ==
Minor unkn
On Fri, Oct 12, 2018 at 06:00:23PM +0300, Stanislav Lisovskiy wrote:
> v2: Renamed DRM_FORMAT_XYUV to DRM_FORMAT_XYUV.
> Added comment about AYUV byte ordering in Gstreamer.
>
> v3: Removed sna_composite_op flags related change to the separate patch.
>
> v4: Fixed review comments, done co
The patch adds a parameter to control the data port coherency functionality
on a per-context level. When the IOCTL is called, a command to switch data
port coherency state is added to the ordered list. All prior requests are
executed on old coherency settings, and all exec requests after the IOCTL
With the extra video kernels we already ran out of bits in
the flags. To tackle that let's just split out the
wm_kernel to its own thing.
Signed-off-by: Stanislav Lisovskiy
---
src/sna/gen9_render.c | 35 ++-
src/sna/sna_render.h | 1 +
2 files changed, 23 inser
sna/gen9+: Added AYUV format support for textured and sprite video adapters.
Split out wm_kernel from the sna_composite_op flags
Stanislav Lisovskiy (2):
sna/gen9+: Split out wm_kernel from the sna_composite_op flags
sna: Added AYUV format support for textured and sprite video adapters.
src/
v2: Renamed DRM_FORMAT_XYUV to DRM_FORMAT_XYUV.
Added comment about AYUV byte ordering in Gstreamer.
v3: Removed sna_composite_op flags related change to the separate patch.
v4: Fixed review comments, done code refactoring
Signed-off-by: Stanislav Lisovskiy
---
src/render_program/Makef
On 12/10/2018 15:02, Chris Wilson wrote:
Handle integer overflow when computing the sub-page length for shmem
backed pread/pwrite.
Reported-by: Tvrtko Ursulin
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/i915/i915_gem.c | 12 ++--
1
== Series Details ==
Series: drm/i915: Large page offsets for pread/pwrite
URL : https://patchwork.freedesktop.org/series/50929/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4976 -> Patchwork_10439 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https:
== Series Details ==
Series: drm/i915: Large page offsets for pread/pwrite
URL : https://patchwork.freedesktop.org/series/50929/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Large page offsets for pread/pwrite
+drivers/gpu/drm/i915/i915_gem
== Series Details ==
Series: drm/i915: Introduce i915_gem_fini_hw for symmetry with i915_gem_init_hw
URL : https://patchwork.freedesktop.org/series/50928/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4976 -> Patchwork_10438 =
== Summary - SUCCESS ==
No regressions found
Handle integer overflow when computing the sub-page length for shmem
backed pread/pwrite.
Reported-by: Tvrtko Ursulin
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/i915/i915_gem.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-
On Fri, Oct 12, 2018 at 11:53:14AM +0530, Shashank Sharma wrote:
> From: Shashank Sharma
>
> LSPCON chips can generate YCBCR outputs, if asked nicely :).
>
> In order to generate YCBCR 4:2:0 outputs, a source must:
> - send YCBCR 4:4:4 signals to LSPCON
> - program color space as 4:2:0 in AVI in
On Thu, 2018-10-11 at 15:57 -0700, Paulo Zanoni wrote:
> From: Mahesh Kumar
>
> Enable SAGV for ICL platform.
>
> Cc: Gwan-gyeong Mun
> Reviewed-by: James Ausmus
> Reviewed-by: Paulo Zanoni
> Signed-off-by: Mahesh Kumar
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_pm.c
Quoting Michal Wajdeczko (2018-10-12 14:26:09)
> In function i915_gem_init_hw we are initializing some uC code that
i915_gem_init_hw really shouldn't be called such, at least it doesn't
fit in with the global init_hw phase. Suggestions for a clearer name
welcome.
> requires some cleanup. Then dur
== Series Details ==
Series: drm/i915: Introduce i915_gem_fini_hw for symmetry with i915_gem_init_hw
URL : https://patchwork.freedesktop.org/series/50928/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Introduce i915_gem_fini_hw for symmetry
In function i915_gem_init_hw we are initializing some uC code that
requires some cleanup. Then during unwind we call this uC cleanup
function directly which breaks symmetry and layering. Fix that by
adding i915_gem_fini_hw for symmetry with i915_gem_init_hw.
Signed-off-by: Michal Wajdeczko
Cc: Ch
== Series Details ==
Series: drm/i915/selftests: Check for hangs mid context execution tests (rev2)
URL : https://patchwork.freedesktop.org/series/50801/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4976 -> Patchwork_10437 =
== Summary - FAILURE ==
Serious unknown chang
Quoting Chris Wilson (2018-07-23 13:15:49)
> Quoting Chris Wilson (2018-07-23 12:29:47)
> > Modernise the test to use igt's ioctl library as opposed to the
> > antiquated libdrm_intel.
>
> There is no value in this test, as it is simply a derivative of
> gem_tiled_blits.c.
Nevertheless, something
== Series Details ==
Series: drm/i915: Remove partial attempt to swizzle on pread/pwrite (rev2)
URL : https://patchwork.freedesktop.org/series/47043/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4976 -> Patchwork_10436 =
== Summary - FAILURE ==
Serious unknown changes c
On Thu, Oct 11, 2018 at 05:40:45PM -0700, Paulo Zanoni wrote:
> These are the new recommended values provided by our spec (18 -> 19
> and 23 -> 24). It seems this should help fixing GMBUS issues. Since
> we're doing pretty much the same thing for both CNP and ICP now, unify
> the functions using th
Use the live_test struct to record the reset count before and compare it
at the end of the test to assert that no mystery hang occurred during the
test.
v2: Check per-engine resets as well
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
.../gpu/drm/i915/selftests/i915_gem_context.c | 51
On 12/10/2018 12:56, Chris Wilson wrote:
Our attempt to account for bit17 swizzling of pread/pwrite onto tiled
objects was flawed due to the simple fact that we do not always know the
swizzling for a particular page (due to the swizzling varying based on
location in certain unbalanced configurat
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