cdclk and rawclk are the 2 display clocks that can now be completed
not initialized when display is disabled.
Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 9 ++++++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 27 +++++++++++++++++--------
2 files changed, 25 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 22cebe4871c9..4ec598b0a737 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -900,7 +900,8 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv)
goto err_uc;
intel_irq_init(dev_priv);
intel_hangcheck_init(dev_priv);
- intel_init_display_hooks(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_init_display_hooks(dev_priv);
intel_init_clock_gating_hooks(dev_priv);
if (INTEL_INFO(dev_priv)->num_pipes) {
intel_init_audio_hooks(dev_priv);
@@ -1709,7 +1710,8 @@ int i915_driver_load(struct pci_dev *pdev, const struct
pci_device_id *ent)
goto out_cleanup_mmio;
/* must happen before intel_power_domains_init_hw() on VLV/CHV */
- intel_update_rawclk(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_update_rawclk(dev_priv);
/* i915_gem_init() call chain will call
* intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ);
@@ -2103,7 +2105,8 @@ static int i915_drm_resume(struct drm_device *dev)
i915_gem_resume(dev_priv);
- intel_modeset_init_hw(dev);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_modeset_init_hw(dev);
intel_init_clock_gating(dev_priv);
spin_lock_irq(&dev_priv->irq_lock);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 15fd88bb35f7..3b2588a377a9 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -801,6 +801,9 @@ static void gen9_dc_off_power_well_enable(struct
drm_i915_private *dev_priv,
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
@@ -3293,7 +3296,8 @@ static void skl_display_core_init(struct drm_i915_private
*dev_priv,
mutex_unlock(&power_domains->lock);
- skl_init_cdclk(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ skl_init_cdclk(dev_priv);
gen9_dbuf_enable(dev_priv);
@@ -3310,7 +3314,8 @@ static void skl_display_core_uninit(struct
drm_i915_private *dev_priv)
gen9_dbuf_disable(dev_priv);
- skl_uninit_cdclk(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ skl_uninit_cdclk(dev_priv);
/* The spec doesn't call for removing the reset handshake flag */
/* disable PG1 and Misc I/O */
@@ -3355,7 +3360,8 @@ void bxt_display_core_init(struct drm_i915_private
*dev_priv,
mutex_unlock(&power_domains->lock);
- bxt_init_cdclk(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ bxt_init_cdclk(dev_priv);
gen9_dbuf_enable(dev_priv);
@@ -3372,7 +3378,8 @@ void bxt_display_core_uninit(struct drm_i915_private
*dev_priv)
gen9_dbuf_disable(dev_priv);
- bxt_uninit_cdclk(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ bxt_uninit_cdclk(dev_priv);
/* The spec doesn't call for removing the reset handshake flag */
@@ -3495,7 +3502,8 @@ static void cnl_display_core_init(struct drm_i915_private
*dev_priv, bool resume
mutex_unlock(&power_domains->lock);
/* 5. Enable CD clock */
- cnl_init_cdclk(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ cnl_init_cdclk(dev_priv);
/* 6. Enable DBUF */
gen9_dbuf_enable(dev_priv);
@@ -3518,7 +3526,8 @@ static void cnl_display_core_uninit(struct
drm_i915_private *dev_priv)
gen9_dbuf_disable(dev_priv);
/* 3. Disable CD clock */
- cnl_uninit_cdclk(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ cnl_uninit_cdclk(dev_priv);
/*
* 4. Disable Power Well 1 (PG1).
@@ -3579,7 +3588,8 @@ static void icl_display_core_init(struct drm_i915_private
*dev_priv,
mutex_unlock(&power_domains->lock);
/* 5. Enable CDCLK. */
- icl_init_cdclk(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ icl_init_cdclk(dev_priv);
/* 6. Enable DBUF. */
icl_dbuf_enable(dev_priv);
@@ -3606,7 +3616,8 @@ static void icl_display_core_uninit(struct
drm_i915_private *dev_priv)
icl_dbuf_disable(dev_priv);
/* 3. Disable CD clock */
- icl_uninit_cdclk(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ icl_uninit_cdclk(dev_priv);
/*
* 4. Disable Power Well 1 (PG1).
--
2.19.1
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