== Series Details ==
Series: /drm/i915/hdmi: SCDC Scrambling enable without CTS mode
URL : https://patchwork.freedesktop.org/series/50648/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4944_full -> Patchwork_10383_full =
== Summary - WARNING ==
Minor unknown changes comi
== Series Details ==
Series: drm/i915/aml: Add new Amber Lake PCI ID (rev2)
URL : https://patchwork.freedesktop.org/series/50037/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4944_full -> Patchwork_10382_full =
== Summary - WARNING ==
Minor unknown changes coming with P
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix VIDEO_DIP_CTL bit shifts
URL : https://patchwork.freedesktop.org/series/50636/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4941_full -> Patchwork_10381_full =
== Summary - WARNING ==
Minor unknown ch
== Series Details ==
Series: drm/i915: Refactor PSR status debugfs
URL : https://patchwork.freedesktop.org/series/50655/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4945 -> Patchwork_10387 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10387 need
== Series Details ==
Series: drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs
entry. (rev5)
URL : https://patchwork.freedesktop.org/series/49800/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4941_full -> Patchwork_10380_full =
== Summary - WARNING ==
== Series Details ==
Series: drm/i915: Refactor PSR status debugfs
URL : https://patchwork.freedesktop.org/series/50655/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e429da2ca190 drm/i915: Refactor PSR status debugfs
-:22: WARNING:BAD_SIGN_OFF: Use a single space after To:
#22
== Series Details ==
Series: series starting with [1/4] drm/i915/psr: Always wait for idle state
when disabling PSR
URL : https://patchwork.freedesktop.org/series/50654/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4945 -> Patchwork_10386 =
== Summary - SUCCESS ==
No r
== Series Details ==
Series: series starting with [1/4] drm/i915/psr: Always wait for idle state
when disabling PSR
URL : https://patchwork.freedesktop.org/series/50654/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/psr: Always wait for idle
== Series Details ==
Series: Display Stream Compression enabling on eDP/DP (rev5)
URL : https://patchwork.freedesktop.org/series/47514/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4945 -> Patchwork_10385 =
== Summary - FAILURE ==
Serious unknown changes coming with Pat
== Series Details ==
Series: Display Stream Compression enabling on eDP/DP (rev5)
URL : https://patchwork.freedesktop.org/series/47514/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
Okay!
C
== Series Details ==
Series: Display Stream Compression enabling on eDP/DP (rev5)
URL : https://patchwork.freedesktop.org/series/47514/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f0a2fb715544 drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
f58388d95d62 drm/dp: A
== Series Details ==
Series: drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values
URL : https://patchwork.freedesktop.org/series/50649/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4945 -> Patchwork_10384 =
== Summary - SUCCESS ==
No regressions found.
External
== Series Details ==
Series: drm/i915: Stop calling intel_opregion unregister/register in
suspend/resume
URL : https://patchwork.freedesktop.org/series/50630/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4940_full -> Patchwork_10379_full =
== Summary - WARNING ==
Minor
The old debugfs fields was not following a naming partern and it was
a bit confusing.
So it went from:
~$ sudo more /sys/kernel/debug/dri/0/i915_edp_psr_status
Sink_Support: yes
PSR mode: PSR1
Enabled: yes
Busy frontbuffer bits: 0x000
Main link in standby mode: no
HW Enabled & Active bit: yes
Sour
While PSR is active hardware will do aux transactions by it self to
wakeup sink to receive a new frame when necessary. If that
transaction is not acked by sink, hardware will trigger this
interruption.
So let's disable PSR as it is a hint that there is problem with this
sink.
The removed FIXME wa
When a PSR error happens sink also update the link status values
while source do not retrain link as required in the PSR exit
sequence.
So in the short pulse handling it was returning earlier and doing a
full detection and attempting to retrain but it fails because for
most sinks the main link is d
It should always wait for idle state when disabling PSR because PSR
could be inactive due a call to intel_psr_exit() and while PSR is
still being disabled asynchronously userspace could change the
modeset causing a call to psr_disable() that will not wait for PSR
idle and then PSR will be enabled a
For eDP panels all the DPCD and EDID data is cached when initializing
the eDP connector so in futher detection it do not call
intel_dp_detect_dpcd() for eDP.
The problem is on the first short pulse interruption it calls
intel_dp_get_dpcd() for eDP and DP and it will read and set the sink
count, cau
On Fri, 2018-10-05 at 16:23 -0700, Manasi Navare wrote:
> DSC can be supported per DP connector. This patch adds a per connector
> debugfs node to expose DSC support capability by the kernel.
> The same node can be used from userspace to force DSC enable.
>
> Cc: Rodrigo Vivi
> Cc: Ville Syrjala
== Series Details ==
Series: /drm/i915/hdmi: SCDC Scrambling enable without CTS mode
URL : https://patchwork.freedesktop.org/series/50648/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4944 -> Patchwork_10383 =
== Summary - SUCCESS ==
No regressions found.
External UR
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v2:
* Fix the power well mismatch CI error (Ville)
* Rename as VDSC_PIPE_A (Imre)
* Fix a whitespace (Anusha)
* Fix Comments (Imre)
Cc: Ville Syrjal
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v3:
* Rebase
v2:
* Add warning for DSC and PSR2 enabled together (DK)
Cc: Rodrigo Vivi
C
A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
VDS
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc params
* Add a condition to disable only if
dsc state co
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the
This patch adds inline functions and helpers for obtaining
DP sink's supported DSC parameters like DSC sink support,
eDP compressed BPP supported, maximum slice count supported
by the sink devices, DSC line buffer bit depth supported on DP sink,
DSC sink maximum color depth by parsing corresponding
This patch adds helpers for calculating the maximum compressed BPP
supported with small joiner.
This also adds a helper for calculating the slice count in case
of small joiner.
These are inside intel_dp since they take into account hardware
limitations.
v6:
* Take mode_clock and mode_hdisplay as i
Currently the driver will only enable DSC if a certain mode
does not fit the available link BW. However IGT/userspace
can force DSC enable through dsc support debugfs node to
test the DSC functionality if supported by the panel.
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-b
DSC can be supported per DP connector. This patch adds a per connector
debugfs node to expose DSC support capability by the kernel.
The same node can be used from userspace to force DSC enable.
Cc: Rodrigo Vivi
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Lyude Paul
Signed-off-by: Manasi Navare
From: "Srivatsa, Anusha"
Add defines for DSS_CTL registers.
These registers specify the big joiner, splitter,
overlap pixels and info regarding display stream
compression enabled on left or right branch.
v3 (From Manasi):
- Change the hex values to lower case (Madhav)
- Use BIT macro (Manasi)
v2
DP 1.4 spec defines DP secondary data packet for DSC
picture parameter set. This patch defines its payload size
according to the DP 1.4 specification.
Signed-off-by: Manasi Navare
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Revi
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason we
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
C
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v2:
* Rebase (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v5 (From Manasi):
* Fix dim checkpatch warnings/checks
v4(From Gaurav):
* No change.Rebase on drm-tip
v3
DSC params like the enable, compressed bpp, slice ocunt and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining
DSC is supported on eDP starting GEN 10 display (on GLK) and on DP starting
GEN 11.
This patch implements the discovery phase of DSC. On hotplug,
source reads the DSC DPCD register set (0x00060 - 0x0006F) to
read the decompression capabilities of the sink device.
This entire block of registers is c
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
From: Anusha Srivatsa
Add the newly added slice_row_per_frame parameter
in the Picture Parameter Set registers.
This defines the number of vertically stacked slices
in a frame.
Credits to Manasi for noticing bSpec change.
Suggested-by: Manasi Navare
Cc: Manasi Navare
Signed-off-by: Anusha Sri
This patch defines the DP DSC receiver capability size that gives
total number of DP DSC DPCD registers.
This also adds a missing #defines for DP DSC support missed in the
commit id (ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature")
v3:
* MIN_SLICE_WIDTH = 2560 (Anusha)
* Define DP_DSC
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of intel_dp as an argument (Manasi)
* Use the compression_enable flag
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
v2:
* Rebase ond drm-tip
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Man
When DSC is supported we need to validate the modes based on the
maximum supported compressed BPP and maximum supported slice count.
This allows us to allow the modes with pixel clock greater than the
available link BW as long as it meets the compressed BPP
and slice count requirements.
v3:
* Use
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewe
VESA has developed an industry standard Display Stream Compression(DSC)
for interoperable, visually lossless compression over display links to
address the needs for higher resolution displays.
This patch series enables DSC on Gen 10 eDP and Gen 11 eDP/DP panels.
This implementation is based on VES
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-de...@lists.freedesktop.org
Cc: Manasi Na
From: Gaurav K Singh
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the DSC_MUX_WO
== Series Details ==
Series: drm/i915/aml: Add new Amber Lake PCI ID (rev2)
URL : https://patchwork.freedesktop.org/series/50037/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4944 -> Patchwork_10382 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https
On Fri, 2018-10-05 at 12:53 -0700, Souza, Jose wrote:
> On Fri, 2018-10-05 at 10:51 -0700, Dhinakaran Pandiyan wrote:
> > On Fri, 2018-10-05 at 10:38 -0700, Rodrigo Vivi wrote:
> > > On Thu, Oct 04, 2018 at 08:01:30PM -0700, Dhinakaran Pandiyan
> > > wrote:
> > > > PSR2 sinks that require Y coordin
From: Clint Taylor
HDMI 2.0 594Mhz modes were incorrectly selecting 25.200Mhz Automatic N
value mode instead of HDMI specification values.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_audio.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i9
From: Clint Taylor
Setting the SCDC scrambling CTS mode causes HDMI Link Layer protocol tests
HF1-12 and HF1-13 to fail. Added "Source Shall" entries from SCDC
section before enabling scrambling.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107895
Bugzilla: https://bugs.freedesktop.org
On Thu, Oct 04, 2018 at 04:23:45PM -0700, Paulo Zanoni wrote:
> Em Qui, 2018-10-04 às 15:36 -0700, Rodrigo Vivi escreveu:
> > From: Anusha Srivatsa
> >
> > Add missing MODULE_FIRMWARE while loading DMC ICL.
> >
> > v2: Add Fixes tag. (Rodrigo)
> > v3: Rebase by Rodrigo after commit 7fe78985cd08
On Fri, 2018-10-05 at 13:00 -0700, Souza, Jose wrote:
> On Thu, 2018-10-04 at 20:01 -0700, Dhinakaran Pandiyan wrote:
> > The hardware can start selective update following capture of a full
> > frame
> > in the remote frame buffer, there is no need to wait any longer.
> > Set
> > "Frames Before SU
On Fri, Oct 05, 2018 at 02:40:01PM +0530, Kumar, Mahesh wrote:
> Hi,
>
> LGTM
>
> Reviewed-by: Mahesh Kumar
pushed to dinq adding also the rv-b from lucas
I got offline...
>
> On 10/4/2018 8:48 PM, Rodrigo Vivi wrote:
> > No functional change. But just a minor change to keep
> > up with Spec
On Thu, Sep 27, 2018 at 05:35:00PM +, Souza, Jose wrote:
> On Thu, 2018-09-27 at 00:48 -0700, Lee, Shawn C wrote:
> > Amber Lake used the same gen graphics as Kaby Lake. Kernel driver
> > should configure KBL's DDI buffer setting for AML ULX as well.
> >
> > So far, driver would load DDI trans
On Tue, Sep 25, 2018 at 08:08:59PM +, Souza, Jose wrote:
> On Mon, 2018-09-24 at 16:43 -0700, Rodrigo Vivi wrote:
> > commit 'b9be78531d27 ("drm/i915/whl: Introducing
> > Whiskey Lake platform")' introduced WHL by moving some
> > of CFL IDs here and using the Spec information of "U43" for
> > m
On Fri, Oct 05, 2018 at 11:04:35PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 05, 2018 at 02:08:46PM -0400, Jyoti Yadav wrote:
> > DC5 and DC6 counter register tells about residency of DC5 and DC6.
> > Added the same in debugfs file.
> >
> > v2 : Remove csr_version check.
> > Added generic che
== Series Details ==
Series: drm/i915: Some plane init cleanups
URL : https://patchwork.freedesktop.org/series/50615/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4938_full -> Patchwork_10378_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_103
On Fri, 2018-10-05 at 12:54 -0700, Rodrigo Vivi wrote:
> On Fri, Oct 05, 2018 at 10:51:28AM -0700, Dhinakaran Pandiyan wrote:
> > On Fri, 2018-10-05 at 10:38 -0700, Rodrigo Vivi wrote:
> > > On Thu, Oct 04, 2018 at 08:01:30PM -0700, Dhinakaran Pandiyan
> > > wrote:
> > > > PSR2 sinks that require Y
On Fri, Oct 05, 2018 at 02:08:46PM -0400, Jyoti Yadav wrote:
> DC5 and DC6 counter register tells about residency of DC5 and DC6.
> Added the same in debugfs file.
>
> v2 : Remove csr_version check.
> Added generic check regarding DC counters for Gen9 onwards. (Rodrigo)
> v3 : Simplified gen
On Thu, 2018-10-04 at 20:01 -0700, Dhinakaran Pandiyan wrote:
> The hardware can start selective update following capture of a full
> frame
> in the remote frame buffer, there is no need to wait any longer. Set
> "Frames Before SU Entry" bitfield to the default value of 1.
>
> Signed-off-by: Dhina
On Fri, Oct 05, 2018 at 10:51:28AM -0700, Dhinakaran Pandiyan wrote:
> On Fri, 2018-10-05 at 10:38 -0700, Rodrigo Vivi wrote:
> > On Thu, Oct 04, 2018 at 08:01:30PM -0700, Dhinakaran Pandiyan wrote:
> > > PSR2 sinks that require Y coordinates for selective update also
> > > need the
> > > Y coordin
On Fri, 2018-10-05 at 10:51 -0700, Dhinakaran Pandiyan wrote:
> On Fri, 2018-10-05 at 10:38 -0700, Rodrigo Vivi wrote:
> > On Thu, Oct 04, 2018 at 08:01:30PM -0700, Dhinakaran Pandiyan
> > wrote:
> > > PSR2 sinks that require Y coordinates for selective update also
> > > need the
> > > Y coordinate
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix VIDEO_DIP_CTL bit shifts
URL : https://patchwork.freedesktop.org/series/50636/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4941 -> Patchwork_10381 =
== Summary - SUCCESS ==
No regressions found.
E
== Series Details ==
Series: drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs
entry. (rev5)
URL : https://patchwork.freedesktop.org/series/49800/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4941 -> Patchwork_10380 =
== Summary - SUCCESS ==
No regress
On Fri, Oct 05, 2018 at 11:56:43AM -0700, Dhinakaran Pandiyan wrote:
> The bits weren't defined in descending order.
> v2: Move definitions in a separate patch (Manasi)
>
> Cc: Manasi Navare
> Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: Manasi Navare
Manasi
> ---
> drivers/gpu/drm/i915/
On Fri, Oct 05, 2018 at 11:43:58AM -0700, Lucas De Marchi wrote:
> On Thu, Oct 4, 2018 at 4:00 AM Daniel Vetter wrote:
> >
> > range-diff is awesome, but the interface is a bit silly. Add a bunch
> > of shortcuts, inspired by what git diff does.
> >
> > v2: Add it to the developer commmands list.
The bits weren't defined in descending order.
v2: Move definitions in a separate patch (Manasi)
Cc: Manasi Navare
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_reg.h | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/
The shifts for VSC_SELECT bits are wrong, fix it. Good thing is the
definitions are unused.
v2: Moves definitions in another patch (Manasi)
Cc: Manasi Navare
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Fixes: 7af2be6d54d4 ("drm/i915/icl: Add VIDEO_DIP registers")
Signed-off-by: Dhinakaran Pandiyan
Re
On Thu, Oct 4, 2018 at 4:00 AM Daniel Vetter wrote:
>
> range-diff is awesome, but the interface is a bit silly. Add a bunch
> of shortcuts, inspired by what git diff does.
>
> v2: Add it to the developer commmands list. With this dim range-diff
> is useable on any git repo, not just a dim managed
On Mon, Oct 01, 2018 at 04:48:21PM +0100, Tvrtko Ursulin wrote:
>
> On 01/10/2018 16:37, Chris Wilson wrote:
> > Quoting Ville Syrjälä (2018-10-01 16:27:43)
> >> On Mon, Oct 01, 2018 at 04:12:09PM +0100, Chris Wilson wrote:
> >>> Quoting Ville Syrjälä (2018-10-01 16:03:30)
> On Wed, Sep 26, 2
== Series Details ==
Series: drm/i915: Stop calling intel_opregion unregister/register in
suspend/resume
URL : https://patchwork.freedesktop.org/series/50630/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4940 -> Patchwork_10379 =
== Summary - WARNING ==
Minor unknown c
On Fri, 2018-10-05 at 11:10 -0700, Manasi Navare wrote:
> On Thu, Oct 04, 2018 at 07:56:37PM -0700, Dhinakaran Pandiyan wrote:
> > On Thu, 2018-10-04 at 17:27 -0700, Manasi Navare wrote:
> > > On Thu, Oct 04, 2018 at 05:00:06PM -0700, Dhinakaran Pandiyan
> > > wrote:
> > > > On Thu, 2018-10-04 at 1
Op 04-10-18 om 17:24 schreef Ville Syrjälä:
> On Thu, Oct 04, 2018 at 03:25:42PM +0200, Maarten Lankhorst wrote:
>> Op 04-10-18 om 14:57 schreef Ville Syrjälä:
>>> On Thu, Oct 04, 2018 at 11:45:59AM +0200, Maarten Lankhorst wrote:
Do not rely on crtc->config any more. Remove the assertion from
== Series Details ==
Series: drm/i915: Stop calling intel_opregion unregister/register in
suspend/resume
URL : https://patchwork.freedesktop.org/series/50630/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
eca8408fd83c drm/i915: Stop calling intel_opregion unregister/register i
On Thu, Oct 04, 2018 at 07:56:37PM -0700, Dhinakaran Pandiyan wrote:
> On Thu, 2018-10-04 at 17:27 -0700, Manasi Navare wrote:
> > On Thu, Oct 04, 2018 at 05:00:06PM -0700, Dhinakaran Pandiyan wrote:
> > > On Thu, 2018-10-04 at 16:28 -0700, Manasi Navare wrote:
> > > > On Thu, Oct 04, 2018 at 04:13
DC5 and DC6 counter register tells about residency of DC5 and DC6.
Added the same in debugfs file.
v2 : Remove csr_version check.
Added generic check regarding DC counters for Gen9 onwards. (Rodrigo)
v3 : Simplified gen checks. (Chris)
v4 : Simplified "if" ladder for multiple gens.
v5 : Remo
If we reduce the suspend function for intel_opregion to do the minimum
required, the resume function can also do the simple task of notifier
the ACPI bios that we are back. This avoid some nasty restrictions on
the likes of register_acpi_notifier() that are not allowed during the
early phase of res
On Fri, 2018-10-05 at 10:38 -0700, Rodrigo Vivi wrote:
> On Thu, Oct 04, 2018 at 08:01:30PM -0700, Dhinakaran Pandiyan wrote:
> > PSR2 sinks that require Y coordinates for selective update also
> > need the
> > Y coordinate Valid bit in VSC SDP.
> > Spec: eDP 1.4b VSC payload extension for PSR2 ope
On Thu, Oct 04, 2018 at 08:01:30PM -0700, Dhinakaran Pandiyan wrote:
> PSR2 sinks that require Y coordinates for selective update also need the
> Y coordinate Valid bit in VSC SDP.
> Spec: eDP 1.4b VSC payload extension for PSR2 operation (Table 6-12)
I couldn't get any meaningful information abou
On Fri, Oct 05, 2018 at 12:02:26AM -0400, Jyoti Yadav wrote:
> DC5 and DC6 counter register tells about residency of DC5 and DC6.
> These registers are same for SKL and ICL.
>
> v2 : Remove csr_version check.
> Added generic check regarding DC counters for Gen9 onwards. (Rodrigo)
> v3 : Simp
On Fri, Oct 05, 2018 at 03:43:30PM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Fix ILK-IVB sprite enable delays (rev2)
> URL : https://patchwork.freedesktop.org/series/50328/
> State : failure
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_4931_full -> Patchw
== Series Details ==
Series: drm/i915: Fix ILK-IVB sprite enable delays (rev2)
URL : https://patchwork.freedesktop.org/series/50328/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4931_full -> Patchwork_10359_full =
== Summary - FAILURE ==
Serious unknown changes coming w
== Series Details ==
Series: drm/i915: First cleanup pass to get rid of more crtc->config users.
(rev5)
URL : https://patchwork.freedesktop.org/series/50506/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4933_full -> Patchwork_10377_full =
== Summary - WARNING ==
Minor
== Series Details ==
Series: drm/i915: Some plane init cleanups
URL : https://patchwork.freedesktop.org/series/50615/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4938 -> Patchwork_10378 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork
== Series Details ==
Series: drm/i915: Some plane init cleanups
URL : https://patchwork.freedesktop.org/series/50615/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Constify all plane_funcs structs
Okay!
Commit: drm/i915: Populate possible_c
== Series Details ==
Series: drm/i915: Some plane init cleanups
URL : https://patchwork.freedesktop.org/series/50615/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6202a7a99d0e drm/i915: Constify all plane_funcs structs
f9e6b37d7294 drm/i915: Populate possible_crtcs for primary
Chris Wilson writes:
> When RECOVERABLE is set, the kernel will attempt to automatically recover
> a context after a hang. But if it is unset, the kernel will ban the
> guilty context on a hang, preventing subsequent execution.
>
> v2: Create a has_recoverable_param()
>
> Signed-off-by: Chris Wil
From: Ville Syrjälä
enum i9xx_plane_id namespace is not valid for any sprite plane,
so let's not even populate plane->i9xx_plane.
Signed-off-by: Ville Syrjälä
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_sprite.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gp
From: Ville Syrjälä
Plane scaling is not supported with specific pixel formats. Disallow
plane scaling when such a format is used. Currently the only such
pixel format we expose is C8, but in case we add more in the future
let's make it easy to deal with them.
v2: Redo due to plane_check() refac
From: Ville Syrjälä
Use a more familiar naming pattern for our variables in the sprite plane
init function.
v2: Drop the redundant 'plane' from plane_formats and num_planes_formats
too
v3: Rebase due to ->max_stride() and ->check_plane() changes
Signed-off-by: Ville Syrjälä
Reviewed-by: St
From: Ville Syrjälä
Let's try to stick a common naming pattern in all the plane init funcs.
v2: Rebase due to color_encoding/range props
Signed-off-by: Ville Syrjälä
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_display.c | 74 ++--
1 file ch
From: Ville Syrjälä
There's not much point in following the primary vs. sprite split
for the SKL+ universal plane init code. The only difference is
of our own doing in the form of the .check_plane(). Let's make
a small exception for that little detail and otherwise share
the same code to initiali
From: Ville Syrjälä
Pull the common plane+plane_state allocation into a small helper.
Reduces the amount of boilerplate in the plane initialization
functions.
Signed-off-by: Ville Syrjälä
Reviewed-by: Chris Wilson
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_display.c | 44
From: Ville Syrjälä
We're currently not providing the possible_crtcs mask to
drm_universal_plane_init() for primary/cursor planes. While that does
work on account of drm_crtc_init_with_planes() filling those up
for us, it's inconsisten with what we're doing for sprite planes.
Let's just always p
From: Ville Syrjälä
All SKL+ universal planes support the same set of formats (with the
exception of NV12 which we don't expose yet). Make the format lists
for primary and sprites the same.
And make the format list const while at it.
v2: Deal with the "planar" format list as well
Signed-off-by
From: Ville Syrjälä
No point in having each caller of intel_create_plane_state() initialize
the scaler_id to -1. Instead just do it in intel_create_plane_state().
Previously we left scaler_id at 0 for pre-SKL platforms, but I can't
see how initializing it to -1 always would cause any harm.
Sign
From: Ville Syrjälä
All CNL universal planes support horizontal mirroring. Currently
we expose the capability only for the primary plane. Expose it
for the overlay planes as well.
Cc: Joonas Lahtinen
Signed-off-by: Ville Syrjälä
Reviewed-by: Joonas Lahtinen
Reviewed-by: Stanislav Lisovskiy
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