On Thu, Oct 04, 2018 at 08:01:30PM -0700, Dhinakaran Pandiyan wrote: > PSR2 sinks that require Y coordinates for selective update also need the > Y coordinate Valid bit in VSC SDP. > Spec: eDP 1.4b VSC payload extension for PSR2 operation (Table 6-12)
I couldn't get any meaningful information about Y coordinate valid bit looking at this table... what am I missing? > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> > --- > drivers/gpu/drm/i915/intel_psr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > b/drivers/gpu/drm/i915/intel_psr.c > index 105b7ea2cd98..92672954dfef 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -431,7 +431,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > * good enough. */ > val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > - val |= EDP_Y_COORDINATE_ENABLE; > + val |= EDP_Y_COORDINATE_ENABLE | EDP_Y_COORDINATE_VALID; But also, this seems to be doing the opposite what you wrote on the commit message since this bit means: "Do not include Y-coordinate valid eDP 1.4" (Bspec: 7713) > > if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 && > dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50) > -- > 2.14.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
