== Series Details ==
Series: i915: make the probe asynchronous (rev2)
URL : https://patchwork.freedesktop.org/series/44159/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4344 -> Patchwork_9364 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_9364 a
On Thursday 31 May 2018 12:39 PM, Daniel Vetter wrote:
On Mon, May 21, 2018 at 06:23:44PM +0530, Ramalingam C wrote:
Implements the enable and disable functions for HDCP2.2 encryption
of the PORT.
v2:
intel_wait_for_register is used instead of wait_for. [Chris Wilson]
v3:
No Changes.
v4
On Thursday 31 May 2018 12:37 PM, Daniel Vetter wrote:
On Mon, May 21, 2018 at 06:23:41PM +0530, Ramalingam C wrote:
Adds the wrapper for all mei hdcp2.2 service functions.
v2:
Rebased.
v3:
cldev is moved from mei_hdcp_data to hdcp.
v4:
%s/hdcp2_store_paring_info/hdcp2_store_pairing_
Hi Takashi,
On Wed, Jun 20, 2018 at 08:35:05AM +0200, Takashi Iwai wrote:
> On Wed, 20 Jun 2018 08:25:23 +0200,
> Feng Tang wrote:
> >
> > Hi Jani/Chris/Takashi,
> >
> > On Wed, Jun 06, 2018 at 11:21:43AM +0300, Jani Nikula wrote:
> > > >>
> > > >> http://patchwork.freedesktop.org/patch/msgid
== Series Details ==
Series: i915: make the probe asynchronous (rev2)
URL : https://patchwork.freedesktop.org/series/44159/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
23766ec5a70a i915: make the probe asynchronous
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit
On Wed, 20 Jun 2018 08:25:23 +0200,
Feng Tang wrote:
>
> Hi Jani/Chris/Takashi,
>
> On Wed, Jun 06, 2018 at 11:21:43AM +0300, Jani Nikula wrote:
> > >>
> > >> http://patchwork.freedesktop.org/patch/msgid/20180323083048.13327-1-ch...@chris-wilson.co.uk
> > >
> > > IIUC, you are waiting for the H
HI,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Patchwork
> Sent: keskiviikko 20. kesäkuuta 2018 3.30
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] ✗ Fi.CI.IGT: failure for Geminilake GuC(11.
Hi Jani/Chris/Takashi,
On Wed, Jun 06, 2018 at 11:21:43AM +0300, Jani Nikula wrote:
> >>
> >> http://patchwork.freedesktop.org/patch/msgid/20180323083048.13327-1-ch...@chris-wilson.co.uk
> >
> > IIUC, you are waiting for the HDA audio driver to first handle the
> > i915 sync probel case?
>
> I
== Series Details ==
Series: Geminilake GuC(11.98), HuC(3.0.2225); Icelake DMC v1.05 (rev2)
URL : https://patchwork.freedesktop.org/series/45036/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4344_full -> Patchwork_9363_full =
== Summary - FAILURE ==
Serious unknown chan
== Series Details ==
Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
(rev6)
URL : https://patchwork.freedesktop.org/series/42459/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4344_full -> Patchwork_9362_full =
== Summary - WARNING ==
Minor
Hi,
Thanks a lot for your feedback.
I believe that I understood all of your comments. I will start the first
version of the patch.
Best Regards
Rodrigo Siqueira
On 06/18, Petri Latvala wrote:
> On Sat, Jun 16, 2018 at 09:26:31PM -0300, Rodrigo Siqueira wrote:
> > Hi,
> >
> > First of all, than
== Series Details ==
Series: Geminilake GuC(11.98), HuC(3.0.2225); Icelake DMC v1.05 (rev2)
URL : https://patchwork.freedesktop.org/series/45036/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4344 -> Patchwork_9363 =
== Summary - SUCCESS ==
No regressions found.
Exter
On Tue, 2018-06-19 at 14:59 -0700, Tarun Vyas wrote:
> On Tue, Jun 19, 2018 at 02:54:07PM -0700, Dhinakaran Pandiyan wrote:
> >
> > On Tue, 2018-06-19 at 14:27 -0700, Dhinakaran Pandiyan wrote:
> > >
> > > On Mon, 2018-05-14 at 13:49 -0700, Tarun Vyas wrote:
> > > >
> > > >
> > > > The PIPEDSL
== Series Details ==
Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
(rev6)
URL : https://patchwork.freedesktop.org/series/42459/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4344 -> Patchwork_9362 =
== Summary - SUCCESS ==
No regressions
On Mon, May 21, 2018 at 05:25:52PM -0700, Paulo Zanoni wrote:
> Do like the other functions and check for the ISR bits. We have plans
> to add a few more checks in this code in the next patches, that's why
> it's a little more verbose than it could be.
>
> Cc: Animesh Manna
> Signed-off-by: Paulo
Resending Geminilake GuC,HuC to trigger new CI runs.
Adding Icelake DMC Support.
The following changes since commit d1147327232ec4616a66ab898df84f9700c816c1:
Merge branch 'for-upstreaming-v1.7.2-vsw' of
https://github.com/felix-cavium/linux-firmware (2018-06-06 13:23:36 -0400)
are available i
From: John Spotswood
load the v11.98 guC on geminilake.
v2: rebased.
v3: Change subject prefix. (Anusha)
Cc: Tomi Sarvela
Cc: Jani Saarinen
Signed-off-by: Anusha Srivatsa
Signed-off-by: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_fw.c | 10 ++
1 file changed, 10 insertions(+
load the v03.00.2225 huC on geminilake.
v2:
- rebased.
- Load the correct the version. (John Spotswood)
v3:
- rebased.
v4: Change subject subject prefix.(Anusha)
Cc: John Spotswood
Cc: Tomi Sarvela
Cc: Jani Saarinen
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index aebe046..3e4e128 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/g
Add Support to load DMC on Icelake.
Cc: Rodrigo Vivi
Cc: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_csr.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index cf9b600..dfc2b7f 100644
On Fri, Jun 15, 2018 at 08:44:04PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> No point in having this extra indireciton for the cursor max size.
> So drop the defines and just write out the raw numbers. Makes it
> easier to see what's going on.
>
> Signed-off-by: Ville Syrjälä
Revie
== Series Details ==
Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
(rev6)
URL : https://patchwork.freedesktop.org/series/42459/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabl
== Series Details ==
Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
(rev6)
URL : https://patchwork.freedesktop.org/series/42459/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
61069992fd74 drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power
From: Ville Syrjälä
CDCLK has to be at least twice the BLCK regardless of audio. Audio
driver has to probe using this hook and increase the clock even in
absence of any display.
v2: Use atomic refcount for get_power, put_power so that we can
call each once(Abhay).
v3: Reset power well 2 to a
On Tue, Jun 19, 2018 at 02:54:07PM -0700, Dhinakaran Pandiyan wrote:
> On Tue, 2018-06-19 at 14:27 -0700, Dhinakaran Pandiyan wrote:
> > On Mon, 2018-05-14 at 13:49 -0700, Tarun Vyas wrote:
> > >
> > > The PIPEDSL freezes on PSR entry and if PSR hasn't fully exited,
> > > then
> > > the pipe_updat
On Tue, Jun 19, 2018 at 05:00:43PM +0800, Zhenyu Wang wrote:
>
> Hi,
>
> Here is first gvt-next pull for next 4.19 kernel. Mostly on gvt
> optimizations and has added BXT support for GVT-g.
pushed to dinq. Thanks.
>
> Thanks.
> ---
> The following changes since commit 14c3f8425080a1ff97df7b81f
== Series Details ==
Series: drm/i915/intel_dsi: Read back and use pclk set by the GOP
URL : https://patchwork.freedesktop.org/series/45030/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4343_full -> Patchwork_9361_full =
== Summary - SUCCESS ==
No regressions found.
On Tue, 2018-06-19 at 14:27 -0700, Dhinakaran Pandiyan wrote:
> On Mon, 2018-05-14 at 13:49 -0700, Tarun Vyas wrote:
> >
> > The PIPEDSL freezes on PSR entry and if PSR hasn't fully exited,
> > then
> > the pipe_update_start call schedules itself out to check back
> > later.
> >
> > On ChromeOS-4
On Mon, 2018-05-14 at 13:49 -0700, Tarun Vyas wrote:
> The PIPEDSL freezes on PSR entry and if PSR hasn't fully exited, then
> the pipe_update_start call schedules itself out to check back later.
>
> On ChromeOS-4.4 kernel, which is fairly up-to-date w.r.t drm/i915 but
> lags w.r.t core kernel cod
== Series Details ==
Series: drm/i915/intel_dsi: Read back and use pclk set by the GOP
URL : https://patchwork.freedesktop.org/series/45030/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4343 -> Patchwork_9361 =
== Summary - SUCCESS ==
No regressions found.
External U
On Thu, Jun 14, 2018 at 12:23:36PM -0700, Rodrigo Vivi wrote:
> On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> > From: Manasi Navare
> >
> > For ICL, on Combo PHY the allowed max rates are:
> > - HBR3 8.1 eDP (DDIA)
> > - HBR2 5.4 DisplayPort (DDIB)
> > and for MG PHY/TC DDI Po
On BYT and CHT the GOP sometimes initializes the pclk at a (slightly)
different frequency then the pclk which we've calculated.
This commit makes the DSI code read-back the pclk set by the GOP and
if that is within a reasonable margin of the calculated pclk, uses
that instead.
This fixes the firs
Move the initialization of encoder variables a bit higher inside the
intel_dsi_init() function. So that the encoder can safely be passed to
intel_connector_get_hw_state() inside intel_dsi_vbt_init().
This is a preparation patch for reading back the GOP configured pclk
from intel_dsi_vbt_init().
S
Hi All,
This patch-set is the result of the work I've been doing recently to
give people a smooth "flickerfree" boot experience where the display
keeps displaying the logo put there by the firmware until it smoothly
fades into the Linux GUI (e.g. gdm).
While testing this on some BYT/CHT devices I
Make intel_connector_get_hw_state() non static so that it can be called
from the intel_dsi_vbt.c code.
This is a preparation patch for reading back the GOP configured pclk
from intel_dsi_vbt_init().
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/intel_dsi.c | 3 +--
drivers/gpu/drm/i915/
Allow calling intel_dsi_get_pclk without passing in an intel_crtc_state.
This is a preparation patch for reading back the GOP configured DSI
clk during probe.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions
Paulo could you review this patch, I need these defs for the next revision
of MG PHY DDI programming new revision.
Manasi
On Tue, May 15, 2018 at 05:53:01PM -0700, Manasi Navare wrote:
> This patch adds the remaining register definitions and bit fields
> required for MG PHy DDI buffer initializat
On Tue, 2018-06-19 at 08:24 -0700, Lucas De Marchi wrote:
> On Tue, Jun 19, 2018 at 7:06 AM Ville Syrjälä
> wrote:
> >
> >
> > On Fri, Jun 15, 2018 at 02:51:06PM -0700, Lucas De Marchi wrote:
> > >
> > > On Fri, Jun 15, 2018 at 08:58:28PM +0300, Ville Syrjälä wrote:
> > > >
> > > > On Wed, May
On 19/06/18 06:55, Chris Wilson wrote:
When using the pollable spinner, we often want to use it as a means of
ensuring the task is running on the GPU before switching to something
else. In which case we don't want to add extra delay inside the spinner,
but the current 1000 NOPs add on order of
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Fix MG PLL setup when refclk
is 38.4MHz (rev3)
URL : https://patchwork.freedesktop.org/series/44836/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4343 -> Patchwork_9360 =
== Summary - FAILURE ==
Seri
Some MG PLL registers have fields that need to be preserved at their HW
default or BIOS programmed values. So make sure we preserve them.
v2:
- Add comment to icl_mg_pll_write() explaining the need for register
masks. (Vandita)
- Fix patchwork checkpatch warning.
v3:
- Rebase on drm-tip.
Cc: V
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Fix MG PLL setup when refclk
is 38.4MHz (rev2)
URL : https://patchwork.freedesktop.org/series/44836/
State : failure
== Summary ==
Applying: drm/i915/icl: Fix MG PLL setup when refclk is 38.4MHz
Applying: drm/i915/icl: Do r
Some MG PLL registers have fields that need to be preserved at their HW
default or BIOS programmed values. So make sure we preserve them.
v2:
- Add comment to icl_mg_pll_write() explaining the need for register
masks. (Vandita)
- Fix patchwork checkpatch warning.
Cc: Vandita Kulkarni
Cc: Paulo
On Tue, Jun 19, 2018 at 7:06 AM Ville Syrjälä
wrote:
>
> On Fri, Jun 15, 2018 at 02:51:06PM -0700, Lucas De Marchi wrote:
> > On Fri, Jun 15, 2018 at 08:58:28PM +0300, Ville Syrjälä wrote:
> > > On Wed, May 23, 2018 at 11:04:35AM -0700, Lucas De Marchi wrote:
> > > > This became dead code with com
Quoting Joonas Lahtinen (2018-06-18 13:25:16)
> Quoting Chris Wilson (2018-06-15 19:37:33)
> > From: Oscar Mateo
> >
> > Once upon a time, we tried to apply workarounds for registers that lived
> > inside the context image for every new context. That meant emitting LRI
> > commands soon after eac
On Tue, 12 Jun 2018, Dhinakaran Pandiyan wrote:
> On Fri, 2018-05-25 at 11:50 +0530, vathsala nagaraju wrote:
>> From: Vathsala Nagaraju
>>
>> Prints live state of psr1.Extending the existing
>> PSR2 live state function to cover psr1.
>>
>> Tested on KBL with psr2 and psr1 panel.
>>
>> v2: reb
== Series Details ==
Series: drm/i915/audio: constify ELD pointers
URL : https://patchwork.freedesktop.org/series/45014/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4341_full -> Patchwork_9358_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9
On Fri, Jun 15, 2018 at 02:51:06PM -0700, Lucas De Marchi wrote:
> On Fri, Jun 15, 2018 at 08:58:28PM +0300, Ville Syrjälä wrote:
> > On Wed, May 23, 2018 at 11:04:35AM -0700, Lucas De Marchi wrote:
> > > This became dead code with commit 309bd8ed464f ("drm/i915: Reinstate
> > > GMBUS and AUX inter
Distinguish between the latency required to switch away from the
pollable spinner into the target nops from the client wakeup of
synchronisation on the last nop.
Signed-off-by: Chris Wilson
---
tests/gem_sync.c | 33 ++---
1 file changed, 30 insertions(+), 3 deletions
When using the pollable spinner, we often want to use it as a means of
ensuring the task is running on the GPU before switching to something
else. In which case we don't want to add extra delay inside the spinner,
but the current 1000 NOPs add on order of 5us, which is often larger
than the target
Quoting Joonas Lahtinen (2018-06-19 14:36:42)
> Quoting Chris Wilson (2018-06-19 13:49:16)
> > Apply a different sort of stress by timing how long it takes to sync a
> > second nop batch in the pipeline. We first start a spinner on the
> > engine, then when we know the GPU is active, we submit the
Quoting Chris Wilson (2018-06-19 13:49:17)
> To further defeat any contemplated spin-optimisations to avoid the irq
> latency for synchronous wakeups, increase the queue length.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Regards, Joonas
___
Quoting Chris Wilson (2018-06-19 13:49:16)
> Apply a different sort of stress by timing how long it takes to sync a
> second nop batch in the pipeline. We first start a spinner on the
> engine, then when we know the GPU is active, we submit the second nop;
> start timing as we then release the spin
Quoting Joonas Lahtinen (2018-06-19 14:16:08)
> + Chris,
>
> Somehow this message managed to dodge the mailing list?
>
> Regards, Joonas
>
> Quoting Dave Jones (2018-06-19 05:52:23)
> > The new DMA mapping debug option in 4.18-rc1 (CONFIG_DMA_API_DEBUG_SG)
> > seems to dislike something about i
Quoting Chris Wilson (2018-06-19 12:20:55)
> Add any buffers reported by sysinfo to the estimate of available memory.
> We do ask the kernel to purge it's caches before reporting sysinfo, but
> a few remain that may be forced out by our test usage, so include them.
> However, be conservative and on
Op 22-05-18 om 02:25 schreef Paulo Zanoni:
> The Gen11 TypeC PHY DDI Buffer chapter, PHY Clock Gating Programming
> section says that PHY clock gating should be disabled before starting
> voltage swing programming, then enabled after any link training is
> complete.
>
> Cc: Animesh Manna
> Cc: Man
+ Chris,
Somehow this message managed to dodge the mailing list?
Regards, Joonas
Quoting Dave Jones (2018-06-19 05:52:23)
> The new DMA mapping debug option in 4.18-rc1 (CONFIG_DMA_API_DEBUG_SG) seems
> to dislike something about i915..
>
> [1.203923] i915 :00:02.0: DMA-API: mapping sg
== Series Details ==
Series: drm/i915/audio: constify ELD pointers
URL : https://patchwork.freedesktop.org/series/45014/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4341 -> Patchwork_9358 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwo
On Tue, Jun 19, 2018 at 03:44:37PM +0300, Jani Nikula wrote:
> The hooks aren't supposed to modify the ELD, so use const pointer. As a
> drive-by fix, use drm_eld_size() to log ELD size.
>
> Suggested-by: Ville Syrjala
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_audio.c | 16
Op 19-06-18 om 14:59 schreef Maarten Lankhorst:
> Op 22-05-18 om 02:25 schreef Paulo Zanoni:
>> Programming this register is part of the Enable Sequence for
>> DisplayPort on ICL. Do as the spec says.
>>
>> Cc: Animesh Manna
>> Cc: Manasi Navare
>> Cc: Dhinakaran Pandiyan
>> Signed-off-by: Paulo
Op 22-05-18 om 02:25 schreef Paulo Zanoni:
> Programming this register is part of the Enable Sequence for
> DisplayPort on ICL. Do as the spec says.
>
> Cc: Animesh Manna
> Cc: Manasi Navare
> Cc: Dhinakaran Pandiyan
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i915_reg.h | 15 +
== Series Details ==
Series: drm/i915/audio: constify ELD pointers
URL : https://patchwork.freedesktop.org/series/45014/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/audio: constify ELD pointers
-O:drivers/gpu/drm/i915/intel_audio.c:288:15: warning: expression usi
The hooks aren't supposed to modify the ELD, so use const pointer. As a
drive-by fix, use drm_eld_size() to log ELD size.
Suggested-by: Ville Syrjala
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_audio.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --
> -Original Message-
> From: Deak, Imre
> Sent: Tuesday, June 19, 2018 3:43 PM
> To: Kulkarni, Vandita
> Cc: intel-gfx@lists.freedesktop.org; Zanoni, Paulo R
> ; Ausmus, James
> Subject: Re: [PATCH 1/2] drm/i915/icl: Fix MG PLL setup when refclk is
> 38.4MHz
>
> On Tue, Jun 19, 2018 at
On Mon, Jun 18, 2018 at 09:40:38PM +, Shaikh, Azhar wrote:
>
>
> >-Original Message-
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Monday, June 18, 2018 4:57 AM
> >To: Jani Nikula
> >Cc: Shaikh, Azhar ; intel-gfx@lists.freedesktop.org
> >Subject: Re: [Intel-g
Signed-off-by: Chris Wilson
---
tests/gem_exec_latency.c | 50
1 file changed, 50 insertions(+)
diff --git a/tests/gem_exec_latency.c b/tests/gem_exec_latency.c
index d64dd73ab..ea2e4c681 100644
--- a/tests/gem_exec_latency.c
+++ b/tests/gem_exec_latency.
Wait until the previous nop batch is running before submitting the next.
This prevents the kernel from batching up sequential requests into a
a ringfull, more strenuous exercising the "lite-restore" execution path.
Signed-off-by: Chris Wilson
---
tests/gem_exec_nop.c | 146 ++
From: Tvrtko Ursulin
We want to make sure RT tasks which use a lot of CPU times can submit
batch buffers with roughly the same latency (and certainly not worse)
compared to normal tasks.
v2: Add tests to run across all engines simultaneously to encourage
ksoftirqd to kick in even more often.
v3:
Apply a different sort of stress by timing how long it takes to sync a
second nop batch in the pipeline. We first start a spinner on the
engine, then when we know the GPU is active, we submit the second nop;
start timing as we then release the spinner and wait for the nop to
complete.
As with ever
Add any buffers reported by sysinfo to the estimate of available memory.
We do ask the kernel to purge it's caches before reporting sysinfo, but
a few remain that may be forced out by our test usage, so include them.
However, be conservative and only allow them to be swapped out.
References: https
To further defeat any contemplated spin-optimisations to avoid the irq
latency for synchronous wakeups, increase the queue length.
Signed-off-by: Chris Wilson
---
tests/gem_sync.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/tests/gem_sync.c b/tests/gem_sync.
On Tue, Jun 19, 2018 at 09:07:25AM +0300, Kulkarni, Vandita wrote:
> > -Original Message-
> > From: Deak, Imre
> > Sent: Monday, June 18, 2018 2:45 PM
> > To: Kulkarni, Vandita
> > Cc: intel-gfx@lists.freedesktop.org; Zanoni, Paulo R
> > ; Ausmus, James
> > Subject: Re: [PATCH 1/2] drm/i9
Quoting Ville Syrjala (2018-06-18 18:39:43)
> From: Ville Syrjälä
>
> My IVB hits the SYNC_COPY assert in prefer_blt_copy() when I force the
> use of the software cursor and I move the cursor on top of a dri2
> window. Looks like any platform with sna_wait_for_scanline() implemented
> should be c
Add any buffers reported by sysinfo to the estimate of available memory.
We do ask the kernel to purge it's caches before reporting sysinfo, but
a few remain that may be forced out by our test usage, so include them.
However, be conservative and only allow them to be swapped out.
References: https
Hi,
Here is first gvt-next pull for next 4.19 kernel. Mostly on gvt
optimizations and has added BXT support for GVT-g.
Thanks.
---
The following changes since commit 14c3f8425080a1ff97df7b81f7c339bf42c427a3:
drm/i915: Update DRIVER_DATE to 20180606 (2018-06-06 15:10:47 -0700)
are available i
On Mon, 18 Jun 2018, Dhinakaran Pandiyan wrote:
> On Mon, 2018-06-18 at 11:42 +0530, vathsala nagaraju wrote:
>> From: Vathsala Nagaraju
>>
>> Adds new psrwake options defined in the below table.
>> Platform PSR wake options vbt version
>> KBL/CFL/WHL All(205+)
>> BXT Uses old inte
On Wed, Jun 13, 2018 at 11:57 PM Arkadiusz Hiler
wrote:
>
> On Wed, Jun 13, 2018 at 10:16:07AM -0700, Lucas De Marchi wrote:
> > On Wed, Jun 13, 2018 at 10:09 AM Lucas De Marchi
> > wrote:
> > >
> > > On Wed, Jun 13, 2018 at 1:11 AM Arkadiusz Hiler
> > > wrote:
> > > >
> > > > On Wed, Jun 13, 20
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