== Series Details ==
Series: series starting with [1/3] drm/i915: Nuke the cursor size defines
URL : https://patchwork.freedesktop.org/series/44854/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4325_full -> Patchwork_9334_full =
== Summary - FAILURE ==
Serious unknown c
== Series Details ==
Series: drm: Try to fix encoder possible_clones/crtcs
URL : https://patchwork.freedesktop.org/series/44848/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4325_full -> Patchwork_9333_full =
== Summary - FAILURE ==
Serious unknown changes coming with P
On Friday, June 15, 2018 12:06:05 PM PDT Chris Wilson wrote:
> From: Kenneth Graunke
>
> The SF and clipper units mishandle the provoking vertex in some cases,
> which can cause misrendering with shaders that use flat shaded inputs.
>
> There are chicken bits in 3D_CHICKEN3 (for SF) and FF_SLICE
== Series Details ==
Series: drm/i915: Apply context workarounds directly
URL : https://patchwork.freedesktop.org/series/44846/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4325_full -> Patchwork_9331_full =
== Summary - WARNING ==
Minor unknown changes coming with Patc
Hi Dhinakaran,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20180615]
[cannot apply to v4.17]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url
== Series Details ==
Series: series starting with [1/5] drm/i915/gtt: Add read only pages to
gen8_pte_encode (rev3)
URL : https://patchwork.freedesktop.org/series/44776/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4325_full -> Patchwork_9330_full =
== Summary - FAILURE =
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/icl: GSE interrupt moves from
DE_MISC to GU_MISC
URL : https://patchwork.freedesktop.org/series/44874/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4329 -> Patchwork_9341 =
== Summary - WARNING ==
Mino
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Fix MG PLL setup when refclk
is 38.4MHz
URL : https://patchwork.freedesktop.org/series/44836/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4325_full -> Patchwork_9329_full =
== Summary - FAILURE ==
S
From: Dhinakaran Pandiyan
The hotplug interrupts for the ports can be routed to either North
Display or South Display depending on the output mode. DP Alternate or
DP over TBT outputs will have hotplug interrupts routed to the North
Display while interrupts for legacy modes will be routed to the
From: Dhinakaran Pandiyan
This patch enables hotplug interrupts for DP over TBT output on TC
ports. The TBT interrupts are enabled and handled irrespective of the
actual output type which could be DP Alternate, DP over TBT, native DP
or native HDMI.
Cc: Animesh Manna
Cc: Paulo Zanoni
Cc: Anush
From: Dhinakaran Pandiyan
The Graphics System Event(GSE) interrupt bit has a new location in the
GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the only
DE_MISC interrupt that was enabled, with this change we don't enable/handle
any of DE_MISC interrupts for gen11. Credits to Pau
Em Qua, 2018-06-13 às 15:20 -0700, Lucas De Marchi escreveu:
> +Chris
>
> On Mon, May 21, 2018 at 05:25:38PM -0700, Paulo Zanoni wrote:
> > From: Dhinakaran Pandiyan
> >
> > The hotplug interrupts for the ports can be routed to either North
> > Display or South Display depending on the output mo
== Series Details ==
Series: drm/i915/guc: Print CTL params passed to Guc
URL : https://patchwork.freedesktop.org/series/44834/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4325_full -> Patchwork_9327_full =
== Summary - FAILURE ==
Serious unknown changes coming with Pa
== Series Details ==
Series: series starting with [v5,1/5] drm/i915/psr: Remove intel_crtc_state
parameter from disable()
URL : https://patchwork.freedesktop.org/series/44873/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4329 -> Patchwork_9340 =
== Summary - SUCCESS ==
Em Qui, 2018-06-14 às 12:54 -0700, Dhinakaran Pandiyan escreveu:
> The Graphics System Event(GSE) interrupt bit has a new location in
> the
> GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the
> only
> DE_MISC interrupt that was enabled, with this change we don't
> enable/handle
>
== Series Details ==
Series: series starting with [v5,1/5] drm/i915/psr: Remove intel_crtc_state
parameter from disable()
URL : https://patchwork.freedesktop.org/series/44873/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/psr: Remove intel_crtc_state parameter fro
== Series Details ==
Series: series starting with [v5,1/5] drm/i915/psr: Remove intel_crtc_state
parameter from disable()
URL : https://patchwork.freedesktop.org/series/44873/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3a098d93ca2e drm/i915/psr: Remove intel_crtc_state para
eDP spec states that sink device will do a short pulse in HPD
line when there is a PSR/PSR2 error that needs to be handled by
source, this is handling the first and most simples error:
DP_PSR_SINK_INTERNAL_ERROR.
Here taking the safest approach and disabling PSR(at least until
the next modeset), t
Sink can be configured to calculate the CRC over the static frame and
compare with the CRC calculated and transmited in the VSC SDP by
source, if there is a mismatch sink will do a short pulse in HPD
and set DP_PSR_LINK_CRC_ERROR in DP_PSR_ERROR_STATUS.
Spec: 7723
v4:
patch moved to after 'drm/i9
Specification requires that max time should be masked from bdw and
forward but it can be also safely enabled to hsw.
This will make PSR exits more deterministic and only when really
needed. If this was used to fix a issue in some panel than can
only self-refresh for a few seconds, that panel will i
It was only used in VLV/CHV so after the removal of the PSR support
for those platforms it is not necessary any more.
Reviewed-by: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 3 +--
drivers/gpu/drm/i915/intel_psr.c | 5 ++---
Sink will interrupt source when it have any PSR error.
DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR is a PSR2 but already
handling it here and DP_PSR_LINK_CRC_ERROR should never
happen as it needs to be enable in sink and source.
v5:
handling all PSR errors here, so the commit message and
comment have chang
== Series Details ==
Series: drm: Pass crtc to .best_encoder()
URL : https://patchwork.freedesktop.org/series/44864/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4328 -> Patchwork_9339 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.f
== Series Details ==
Series: drm: Pass crtc to .best_encoder()
URL : https://patchwork.freedesktop.org/series/44864/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
30c6fbddb826 drm: Pass crtc to .best_encoder()
-:81: WARNING:LONG_LINE: line over 100 characters
#81: FILE: drivers
On Fri, Jun 15, 2018 at 08:58:28PM +0300, Ville Syrjälä wrote:
> On Wed, May 23, 2018 at 11:04:35AM -0700, Lucas De Marchi wrote:
> > This became dead code with commit 309bd8ed464f ("drm/i915: Reinstate
> > GMBUS and AUX interrupts on gen4/g4x").
> >
> > v2: Move comment about HW behavior to where
== Series Details ==
Series: drm/i915/uc: Fetch GuC/HuC firmwares from guc/huc specific init
URL : https://patchwork.freedesktop.org/series/44861/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4328 -> Patchwork_9338 =
== Summary - FAILURE ==
Serious unknown changes comin
Em Sex, 2018-06-15 às 20:44 +0300, Ville Syrjala escreveu:
> From: Ville Syrjälä
>
> The PCH transcoder registers are only 12 bits wide for the hdisplay
> and hblank_start values. On HSW/BDW the CPU side registers are 13
> bits wide. intel_mode_valid() only checks against the higher limit
> (sinc
Quoting Antonio Argenziano (2018-06-15 21:23:51)
>
>
> On 15/06/18 11:56, Chris Wilson wrote:
> > As we hang ctx0 quite frequently, it needs to be harden against being
> > banned.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Mika Kuoppala
>
> For some reason I thought we had more hang stress t
On Fri, Jun 15, 2018 at 01:30:24PM -0700, Paulo Zanoni wrote:
> Em Sex, 2018-06-15 às 20:44 +0300, Ville Syrjala escreveu:
> > From: Ville Syrjälä
> >
> > Validate that all display timings fit within the number of bits
> > we have in the transcoder timing registers.
> >
> > The limits are:
> > h
On Tue, Jun 12, 2018 at 03:09:36PM -0400, Harry Wentland wrote:
> On 2018-06-11 03:34 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Print out the modeline when we reject a bad user mode. Avoids having to
> > guess why it was rejected.
> >
> > Signed-off-by: Ville Syrjälä
>
> Reviewe
Em Sex, 2018-06-15 às 20:44 +0300, Ville Syrjala escreveu:
> From: Ville Syrjälä
>
> Validate that all display timings fit within the number of bits
> we have in the transcoder timing registers.
>
> The limits are:
> hsw+:
> 4k: vdisplay, vblank_start
> 8k: everything else
> gen3+:
> 4k: h/vd
== Series Details ==
Series: series starting with [01/21] drm/i915/execlists: Pull submit after
dequeue under timeline lock
URL : https://patchwork.freedesktop.org/series/44860/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4326 -> Patchwork_9337 =
== Summary - SUCCESS ==
On 15/06/18 11:56, Chris Wilson wrote:
As we hang ctx0 quite frequently, it needs to be harden against being
banned.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
For some reason I thought we had more hang stress tests.
Reviewed-by: Antonio Argenziano
---
tests/gem_eio.c | 2 +-
1 f
== Series Details ==
Series: series starting with [01/21] drm/i915/execlists: Pull submit after
dequeue under timeline lock
URL : https://patchwork.freedesktop.org/series/44860/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/execlists: Pull submit after dequeue und
On Fri, Jun 15, 2018 at 09:02:52PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-06-15 20:48:49)
> > On Fri, Jun 15, 2018 at 07:44:08PM +0100, Chris Wilson wrote:
> > > Quoting Ville Syrjala (2018-06-15 18:44:05)
> > > > From: Ville Syrjälä
> > > >
> > > > Validate that all display tim
== Series Details ==
Series: series starting with [01/21] drm/i915/execlists: Pull submit after
dequeue under timeline lock
URL : https://patchwork.freedesktop.org/series/44860/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
cf612f0dd64d drm/i915/execlists: Pull submit after de
== Series Details ==
Series: drm/i915: Enable provoking vertex fix on Gen9+ systems. (rev3)
URL : https://patchwork.freedesktop.org/series/44781/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4326 -> Patchwork_9336 =
== Summary - WARNING ==
Minor unknown changes coming w
Quoting Ville Syrjälä (2018-06-15 20:48:49)
> On Fri, Jun 15, 2018 at 07:44:08PM +0100, Chris Wilson wrote:
> > Quoting Ville Syrjala (2018-06-15 18:44:05)
> > > From: Ville Syrjälä
> > >
> > > Validate that all display timings fit within the number of bits
> > > we have in the transcoder timing
Hi,
On 6/15/2018 12:20 PM, Michal Wajdeczko wrote:
We're fetching GuC/HuC firmwares directly from uc level during
init_early stage but this breaks guc/huc struct isolation and
also strict SW-only initialization rule. Move fw fetching to
init phase and do it separately per guc/huc struct.
Can
From: Ville Syrjälä
To pick the correct MST encoder i915 wants to know which crtc is going
to be feeding us. To that end let's pass the crtc to the .best_encoder()
hook. The atomic variant already knows the crtc via the connector state,
but the non-atomic hooks is still being used by the fb_helpe
Em Sex, 2018-06-15 às 20:44 +0300, Ville Syrjala escreveu:
> From: Ville Syrjälä
>
> No point in having this extra indireciton for the cursor max size.
> So drop the defines and just write out the raw numbers. Makes it
> easier to see what's going on.
And the gen2 definition doesn't even say "ma
On Fri, Jun 15, 2018 at 07:44:08PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-06-15 18:44:05)
> > From: Ville Syrjälä
> >
> > Validate that all display timings fit within the number of bits
> > we have in the transcoder timing registers.
> >
> > The limits are:
> > hsw+:
> > 4k: v
We're fetching GuC/HuC firmwares directly from uc level during
init_early stage but this breaks guc/huc struct isolation and
also strict SW-only initialization rule. Move fw fetching to
init phase and do it separately per guc/huc struct.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Currently the async submission backends (guc and execlists) hold a extra
reference to the requests being processed as they are not serialised with
request retirement. If we instead, prevent the request being dropped
from the engine timeline until after submission has finished processing
the request
Currently all callers are responsible for adding the vma to the active
timeline and then exporting its fence. Combine the two operations into
i915_vma_move_to_active() to move all the extra handling from the
callers to the single site.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_ge
Handling such a late error in request construction is tricky, but to
accommodate future patches which may allocate here, we potentially could
err. To handle the error after already adjusting global state to track
the new request, we must finish and submit the request. But we don't
want to use the r
In the next patch, we will want to be able to use more flexible request
timelines that can hop between engines. From the vma pov, we can then
not rely on the binding of this request to an engine and so can not
ensure that different requests are ordered through a per-engine
timeline, and so we must
Taken from an idea used for FQ_CODEL, we give new request flows a
priority boost. These flows are likely to correspond with interactive
tasks and so be more latency sensitive than the long queues. As soon as
the client has more than one request in the queue, further requests are
not boosted and it
Using a VMA on more than one timeline concurrently is the exception
rather than the rule (using it concurrently on multiple engines). As we
expect to only use one active tracker, store the most recently used
tracker inside the i915_vma itself and only fallback to the radixtree if
we need a second o
In order to maximise concurrency between engines, if we queue a request
to a current idle ring, reorder its dependencies to execute that request
as early as possible and ideally improve occupancy of multiple engines
simultaneously.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_reques
Rather than have multiple locked instructions inside the notify_ring()
irq handler, move them inside the spinlock and reduce their intrinsic
locking.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
drivers/gpu/drm/i915/i915_request.c | 4 ++--
drivers/gp
As we are about to allow ourselves to slightly bump the user priority
into a few different sublevels, packthose internal priority lists
into the same i915_priolist to keep the rbtree compact and avoid having
to allocate the default user priority even after the internal bumping.
The downside to havi
In the next few patches, we will want to give a small priority boost to
some requests/queues but not so much that we perturb the user controlled
order. As such we shift the user priority bits higher leaving ourselves
a few low priority bits for our bumping.
Signed-off-by: Chris Wilson
---
driver
Avoid calling dma_fence_signal() from inside the interrupt if we haven't
enabled signaling on the request.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_irq.c | 8 ++--
drivers/gpu/drm/i915/i915_request.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++---
3 fi
The kernel recently gained an augmented rbtree with the purpose of
cacheing the leftmost element of the rbtree, a frequent optimisation to
avoid calls to rb_first() which is also employed by the
execlists->queue. Switch from our open-coded cache to the library.
Signed-off-by: Chris Wilson
---
dr
In the next patch, we will begin processing the CSB from inside the
submission path (underneath an irqsoff section, and even from inside
interrupt handlers). This means that updating the execlists->port[] will
no longer be serialised by the tasklet but needs to be locked by the
engine->timeline.loc
By taking advantage of the RCU protection of the task struct, we can find
the appropriate signaler under the spinlock and then release the spinlock
before waking the task and signaling the fence.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_irq.c | 33 ++-
In the next patch, we will start to defer retiring the request from the
engine list if it is still active on the submission backend. To preserve
the semantics that after wait-for-idle completes the system is idle and
fully retired, we need to therefore wait for the backends to idle before
calling i
Our long standing defense against a single client from flooding the
system with requests (causing mempressure and stalls across the whole
system) is to retire the old request on every allocation. (By retiring
the oldest, we try to keep returning requests back to the system in a
steady flow.) This a
Following the removal of the last workarounds, the only CSB mmio access
is for the old vGPU interface. The mmio registers presented by vGPU do
not require forcewake and can be treated as ordinary volatile memory,
i.e. they behave just like the HWSP access just at a different location.
We can reduce
In the next patch, we will process the CSB events directly from the
submission path, rather than only after a CS interrupt. Hence, we will
no longer have the need for a loop until the has-interrupt bit is clear,
and in the meantime can remove that small optimisation.
Signed-off-by: Chris Wilson
-
In the following patch, we will process the CSB events under the
timeline.lock and not serailiased by the tasklet. This also means that we
will need to protect access to common variables such as
execlists->csb_head with the timeline.lock during reset.
v2: Move sync_irq to avoid deadlocks between t
Back in commit 27af5eea54d1 ("drm/i915: Move execlists irq handler to a
bottom half"), we came to the conclusion that running our CSB processing
and ELSP submission from inside the irq handler was a bad idea. A really
bad idea as we could impose nearly 1s latency on other users of the
system, on av
In the next patch, we will move ownership of the fence reference to the
submission backend and will want to drop its final reference when
retiring it from the submission backend. We will also need a catch up
when parking the engine to cleanup any residual entries in the engine
timeline. In short, m
From: Kenneth Graunke
The SF and clipper units mishandle the provoking vertex in some cases,
which can cause misrendering with shaders that use flat shaded inputs.
There are chicken bits in 3D_CHICKEN3 (for SF) and FF_SLICE_CHICKEN
(for the clipper) that work around the issue. These registers a
As we hang ctx0 quite frequently, it needs to be harden against being
banned.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
tests/gem_eio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/gem_eio.c b/tests/gem_eio.c
index e1aff639d..5faf7502b 100644
--- a/tests/gem
== Series Details ==
Series: drm/i915: Keep the ctx workarounds tightly packed (rev2)
URL : https://patchwork.freedesktop.org/series/44807/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4323_full -> Patchwork_9326_full =
== Summary - WARNING ==
Minor unknown changes comi
On Fri, Jun 15, 2018 at 11:33:01AM -0700, Dhinakaran Pandiyan wrote:
> On Fri, 2018-06-15 at 19:49 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Each fake MST encoder is tied to a specific pipe. Fix the encoder's
> > crtc_mask to reflect that fact.
> >
> > Signed-off-by: Ville Syrj
Quoting Ville Syrjala (2018-06-15 18:44:05)
> From: Ville Syrjälä
>
> Validate that all display timings fit within the number of bits
> we have in the transcoder timing registers.
>
> The limits are:
> hsw+:
> 4k: vdisplay, vblank_start
> 8k: everything else
> gen3+:
> 4k: h/vdisplay, h/vblan
== Series Details ==
Series: drm/i915: Enable provoking vertex fix on Gen9+ systems. (rev2)
URL : https://patchwork.freedesktop.org/series/44781/
State : failure
== Summary ==
Applying: drm/i915: Enable provoking vertex fix on Gen9+ systems.
error: patch failed: drivers/gpu/drm/i915/intel_lrc.
Quoting Kenneth Graunke (2018-06-14 22:53:28)
> The SF and clipper units mishandle the provoking vertex in some cases,
> which can cause misrendering with shaders that use flat shaded inputs.
>
> There are chicken bits in 3D_CHICKEN3 (for SF) and FF_SLICE_CHICKEN
> (for the clipper) that work arou
== Series Details ==
Series: drm/i915: Fix context ban and hang accounting for client (rev2)
URL : https://patchwork.freedesktop.org/series/44820/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4323_full -> Patchwork_9325_full =
== Summary - FAILURE ==
Serious unknown cha
== Series Details ==
Series: ICELAKE DSI DRIVER
URL : https://patchwork.freedesktop.org/series/44823/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4323_full -> Patchwork_9324_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9324_full need to be
== Series Details ==
Series: series starting with [1/3] drm/i915: Nuke the cursor size defines
URL : https://patchwork.freedesktop.org/series/44854/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4325 -> Patchwork_9334 =
== Summary - SUCCESS ==
No regressions found.
Ex
Em Sex, 2018-06-15 às 23:30 +0530, Chauhan, Madhav escreveu:
> > -Original Message-
> > From: Zanoni, Paulo R
> > Sent: Friday, June 15, 2018 11:00 PM
> > To: Chauhan, Madhav ; intel-
> > g...@lists.freedesktop.org
> > Cc: Nikula, Jani ; Shankar, Uma
> > ; Vivi, Rodrigo
> > Subject: Re: [P
On Fri, 2018-06-15 at 19:49 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Each fake MST encoder is tied to a specific pipe. Fix the encoder's
> crtc_mask to reflect that fact.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> 1 file changed, 1 inser
> -Original Message-
> From: Zanoni, Paulo R
> Sent: Friday, June 15, 2018 11:00 PM
> To: Chauhan, Madhav ; intel-
> g...@lists.freedesktop.org
> Cc: Nikula, Jani ; Shankar, Uma
> ; Vivi, Rodrigo
> Subject: Re: [PATCH 02/20] drm/i915/icl: Program DSI Escape clock Divider
>
> Em Sex, 2018-
On Wed, May 23, 2018 at 11:04:35AM -0700, Lucas De Marchi wrote:
> This became dead code with commit 309bd8ed464f ("drm/i915: Reinstate
> GMBUS and AUX interrupts on gen4/g4x").
>
> v2: Move comment about HW behavior to where decision is made to enable
> MSI (Ville).
>
> Cc: Ville Syrjälä
> Sign
== Series Details ==
Series: drm: Try to fix encoder possible_clones/crtcs
URL : https://patchwork.freedesktop.org/series/44848/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4325 -> Patchwork_9333 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https:/
On Fri, 2018-06-15 at 11:10 +0300, Jani Nikula wrote:
> On Thu, 14 Jun 2018, Dhinakaran Pandiyan om> wrote:
> >
> > On Thu, 2018-06-14 at 16:56 +, Nagaraju, Vathsala wrote:
> > >
> > > + Ashutosh(VBT team) + maulik
> > >
> > > 209 is confirmed version on kbl both by vbt team (Maulik) and
From: Ville Syrjälä
Validate that all display timings fit within the number of bits
we have in the transcoder timing registers.
The limits are:
hsw+:
4k: vdisplay, vblank_start
8k: everything else
gen3+:
4k: h/vdisplay, h/vblank_start
8k: everything else
gen2:
2k: h/vdisplay, h/vblank_start
From: Ville Syrjälä
No point in having this extra indireciton for the cursor max size.
So drop the defines and just write out the raw numbers. Makes it
easier to see what's going on.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 8
drivers/gpu/drm/i915/intel_
From: Ville Syrjälä
The PCH transcoder registers are only 12 bits wide for the hdisplay
and hblank_start values. On HSW/BDW the CPU side registers are 13
bits wide. intel_mode_valid() only checks against the higher limit
(since we don't know where the mode is to be used), so an extra
check is req
On 06/15/2018 07:10 AM, Michal Wajdeczko wrote:
While debugging we may want to examine params passed to GuC.
Print them all if config I915_DEBUG_GUC is enabled.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc.c | 5 +
1 f
== Series Details ==
Series: drm: Try to fix encoder possible_clones/crtcs
URL : https://patchwork.freedesktop.org/series/44848/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a211728791ac drm: Add drm_encoder_mask()
bd9b5da2d267 drm: Include the encoder itself in possible_clone
== Series Details ==
Series: series starting with [1/2] drm/i915: Apply context workarounds directly
URL : https://patchwork.freedesktop.org/series/44847/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4325 -> Patchwork_9332 =
== Summary - FAILURE ==
Serious unknown chang
Em Sex, 2018-06-15 às 15:51 +0530, Madhav Chauhan escreveu:
> Escape Clock is used for LP communication across the DSI
> Link. To achieve the constant frequency of the escape clock
> from the variable DPLL frequency output, a variable divider(M)
> is needed. This patch programs the same.
>
> Signe
== Series Details ==
Series: series starting with [1/2] drm/i915: Apply context workarounds directly
URL : https://patchwork.freedesktop.org/series/44847/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c9721f49301c drm/i915: Apply context workarounds directly
2b91c9fa2f2e drm/i9
== Series Details ==
Series: drm/i915: Apply context workarounds directly
URL : https://patchwork.freedesktop.org/series/44846/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4325 -> Patchwork_9331 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9331
From: Ville Syrjälä
WARN if the encoder possible_crtcs is effectively empty or contains
bits for non-existing crtcs.
TODO: Or should we perhapst just filter out any bit for a
non-exisiting crtc?
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_encoder.c | 18 ++
1 file cha
From: Ville Syrjälä
We don't need to special case PCH vs. gen4 when setting up the LVDS
crtc_mask. Just claim pipes A|B|C work and intel_encoder_crtcs() drop
out any crtc that doesn't exist.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_lvds.c | 4 +---
1 file changed, 1 insertio
From: Ville Syrjälä
Each fake MST encoder is tied to a specific pipe. Fix the encoder's
crtc_mask to reflect that fact.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
From: Ville Syrjälä
Use BIT(pipe) for better legibility when populating the crtc_mask
for encoders.
Also remove the redundant possible_crtcs setup for the TV encoder.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_crt.c | 4 ++--
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers
From: Ville Syrjälä
Don't advertize non-exisiting crtcs in the encoder possible_crtcs
bitmask.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/dri
From: Ville Syrjälä
Many drivers are populating encoder->possible_clones wrong. Let's
persuade them to get it right by adding some loud WARNs.
We'll cross check the bits between any two encoders. So either
both encoders can clone with the other, or neither can.
We'll also complain about effecti
From: Ville Syrjälä
There's no point in the cast for accessing the base class. Just
take the address of the struct instead.
Cc: Benjamin Gaignard
Cc: Vincent Abriou
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/sti/sti_tvout.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
d
From: Ville Syrjälä
dw_hdmi_imx_bind() does not call so the possible_clones mask being set
here is entirely bogus, not to mention the bits set for non-existent
encoders. Just clear possible_clones until someone fixes this properly.
Cc: Philipp Zabel
Signed-off-by: Ville Syrjälä
---
drivers/gp
From: Ville Syrjälä
Replace the hand rolled stuff with drm_encoder_mask() when populating
possible_clones.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drive
From: Ville Syrjälä
The current possible_clones setup doesn't look sensible. I'm assuming
the 0 and 1 are supposed to refer to the indexes of the hdmi and hda
encoders? So it kinda looks like we want hda+hdmi cloning, but then
dvo also claims to be cloneable with hdmi, but hdmi won't recipricate.
From: Ville Syrjälä
Replace the hand rolled encoder bitmask thing with drm_encoder_mask()
Cc: Inki Dae
Cc: Joonyoung Shim
Cc: Seung-Woo Kim
Cc: Kyungmin Park
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/exynos/exynos_drm_drv.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
1 - 100 of 205 matches
Mail list logo
