Quoting Sagar Arun Kamble (2018-02-27 06:54:46)
>
>
> On 2/27/2018 2:22 AM, Chris Wilson wrote:
> > Quoting Daniele Ceraolo Spurio (2018-02-26 16:57:11)
> >> As you said we do always reset GuC no matter the value of the modparam,
> >> but that does not reset the doorbell HW. If we're coming out o
On 2/26/2018 10:27 PM, Daniele Ceraolo Spurio wrote:
On 25/02/18 22:17, Sagar Arun Kamble wrote:
On 2/23/2018 10:31 PM, Daniele Ceraolo Spurio wrote:
On 23/02/18 06:04, Michal Wajdeczko wrote:
Right after GPU reset there will be a small window of time during
which
some of GuC/HuC fiel
Hi,
> These documentation improvements are much welcome, here are a few comments
> from me.
Thankyou!
>Quoting kevin.rogo...@intel.com (2018-02-16 16:04:22)
>> +Intel GPU Basics
>> +
>> +
>> +An Intel GPU has multiple engines. There are several engine types.
>> +
>> +- RCS engin
On 2/27/2018 2:22 AM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2018-02-26 16:57:11)
On 25/02/18 22:17, Sagar Arun Kamble wrote:
On 2/23/2018 10:31 PM, Daniele Ceraolo Spurio wrote:
On 23/02/18 06:04, Michal Wajdeczko wrote:
Right after GPU reset there will be a small window of
On 2/27/2018 4:34 AM, Oscar Mateo wrote:
On 2/25/2018 9:22 PM, Sagar Arun Kamble wrote:
On 2/23/2018 4:35 AM, Oscar Mateo wrote:
+ * We might have detected that some engines are fused off after
we initialized
+ * the forcewake domains. Prune them, to make sure they only
reference ex
== Series Details ==
Series: drm/i915/psr: Check for power state control capability.
URL : https://patchwork.freedesktop.org/series/39006/
State : success
== Summary ==
Possible new issues:
Test kms_vblank:
Subgroup pipe-a-query-forked-busy-hang:
dmesg-warn -> PAS
== Series Details ==
Series: drm/i915/dp: Fix the order of platforms for setting DP source rates
URL : https://patchwork.freedesktop.org/series/39004/
State : success
== Summary ==
Possible new issues:
Test kms_vblank:
Subgroup pipe-a-query-forked-busy-hang:
dmesg
== Series Details ==
Series: drm/i915: Enable VBT based BL control for DP (v3) (rev8)
URL : https://patchwork.freedesktop.org/series/38559/
State : success
== Summary ==
Possible new issues:
Test kms_vblank:
Subgroup pipe-a-query-forked-busy-hang:
dmesg-warn -> PA
== Series Details ==
Series: drm/i915/psr: Check for power state control capability.
URL : https://patchwork.freedesktop.org/series/39006/
State : success
== Summary ==
Series 39006v1 drm/i915/psr: Check for power state control capability.
https://patchwork.freedesktop.org/api/1.0/series/39006
== Series Details ==
Series: drm/i915/dp: Fix the order of platforms for setting DP source rates
URL : https://patchwork.freedesktop.org/series/39004/
State : success
== Summary ==
Series 39004v1 drm/i915/dp: Fix the order of platforms for setting DP source
rates
https://patchwork.freedesktop
== Series Details ==
Series: drm/i915: Enable VBT based BL control for DP (v3) (rev8)
URL : https://patchwork.freedesktop.org/series/38559/
State : success
== Summary ==
Series 38559v8 drm/i915: Enable VBT based BL control for DP (v3)
https://patchwork.freedesktop.org/api/1.0/series/38559/revi
On Mon, 2018-02-26 at 14:41 -0800, Rodrigo Vivi wrote:
> On Mon, Feb 26, 2018 at 01:48:37PM -0800, José Roberto de Souza wrote:
> > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> > self, so lets use the mutex register that is available in gen9+ to
> > avoid concurrent acce
== Series Details ==
Series: drm/i915: Add a parameter to disable SAGV
URL : https://patchwork.freedesktop.org/series/38992/
State : success
== Summary ==
Possible new issues:
Test kms_atomic_transition:
Subgroup plane-all-modeset-transition-fencing:
pass ->
eDP spec says - "If PSR/PSR2 is supported, the SET_POWER_CAPABLE bit in the
EDP_GENERAL_CAPABILITY_1 register (DPCD Address 00701h, bit d7) must be set
to 1."
Reject PSR on panels without this cap bit set as such panels cannot be
controlled via SET_POWER & SET_DP_PWR_VOLTAGE register and the DP so
The usual if ladder order should be from newest to oldest
platform. However the CNL conditional statement was misplaced.
This patch sets the DP source for platforms starting from the newest
to oldest.
Suggested-by: Jani Nikula
Cc: Rodrigo Vivi
Cc: Jani Nikula
Signed-off-by: Manasi Navare
---
Currently, BXT_PP is hardcoded with value '0'.
It practically disabled eDP backlight on MRB (BXT) platform.
This patch will tell which BXT_PP registers (there are two set of
PP_CONTROL in the spec) to be used as defined in VBT (Video Bios Timing
table) and this will enabled eDP backlight controlle
== Series Details ==
Series: drm/i915: Enable VBT based BL control for DP (v3) (rev7)
URL : https://patchwork.freedesktop.org/series/38559/
State : failure
== Summary ==
Applying: drm/i915: Enable VBT based BL control for DP
error: corrupt patch at line 40
error: could not build fake ancestor
== Series Details ==
Series: series starting with [v6,1/2] drm/i915: Move a bunch of
workaround-related code to its own file (rev2)
URL : https://patchwork.freedesktop.org/series/38891/
State : success
== Summary ==
Possible new issues:
Test kms_flip:
Subgroup flip-vs-fences:
Currently, BXT_PP is hardcoded with value '0'.
It practically disabled eDP backlight on MRB (BXT) platform.
This patch will tell which BXT_PP registers (there are two set of
PP_CONTROL in the spec) to be used as defined in VBT (Video Bios Timing
table) and this will enabled eDP backlight controlle
> -Original Message-
> From: Runyan, Arthur J
> Sent: Tuesday, January 9, 2018 11:55 AM
> To: Pandiyan, Dhinakaran ; Singh, Gaurav K
>
> Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo
> Subject: RE: [Intel-gfx] [PATCH] drm: i915: Fix audio issue on BXT
>
> Sorry, I've been out. I'm
On Thu, Feb 22, 2018 at 12:05:35PM -0800, Rodrigo Vivi wrote:
> Old Wa added now forever on CNL all steppings.
>
> With CPU P states enabled along with RC6, dispatcher
> hangs can happen.
>
> Cc: Rafael Antognolli
> Signed-off-by: Rodrigo Vivi
Reviewed-by: Radhakrishna Sripada
> ---
> drivers
== Series Details ==
Series: drm/i915: Add and enable DP AUX CH mutex (rev3)
URL : https://patchwork.freedesktop.org/series/38655/
State : success
== Summary ==
Known issues:
Test kms_flip:
Subgroup dpms-vs-vblank-race-interruptible:
fail -> PASS (shar
On Mon, Feb 26, 2018 at 03:45:51PM -0800, Azhar Shaikh wrote:
> SAGV handling is currently broken which can result in system hangs.
> Add a parameter to disable SAGV, till the SAGV handling is fixed.
Not just handling of the limitations we have with SAGV is broken but
also probably some hidden DBU
Hi everyone,
Just a quick word to remind you that the X.Org Foundation got accepted
to the Google Summer of Code 2018!
As a potential mentor, if you have a project falling under the
foundation's (large) umbrella that you would like to kick start or get
help finishing, please add it to the list on
== Series Details ==
Series: drm/i915: Add a parameter to disable SAGV
URL : https://patchwork.freedesktop.org/series/38992/
State : success
== Summary ==
Series 38992v1 drm/i915: Add a parameter to disable SAGV
https://patchwork.freedesktop.org/api/1.0/series/38992/revisions/1/mbox/
Kno
== Series Details ==
Series: series starting with [v6,1/2] drm/i915: Move a bunch of
workaround-related code to its own file (rev2)
URL : https://patchwork.freedesktop.org/series/38891/
State : success
== Summary ==
Series 38891v2 series starting with [v6,1/2] drm/i915: Move a bunch of
worka
SAGV handling is currently broken which can result in system hangs.
Add a parameter to disable SAGV, till the SAGV handling is fixed.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104975
Signed-off-by: Azhar Shaikh
---
drivers/gpu/drm/i915/i915_params.c | 3 +++
drivers/gpu/drm/i915/i91
== Series Details ==
Series: series starting with [v6,1/2] drm/i915: Move a bunch of
workaround-related code to its own file (rev2)
URL : https://patchwork.freedesktop.org/series/38891/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Move a bunch of workaround-rela
On Mon, Feb 26, 2018 at 10:42:34PM +0530, Ramalingam C wrote:
> This series addresses the requriement of below HDCP compliance tests
> DP: 1A-06 and 1B-05
> HDMI: 1A-04 and 1A-07a
>
> One of the patch uses the I915 power infra-structure for checking
> the power state of PW#1. Which en
== Series Details ==
Series: series starting with drm/i915/guc: Fill preempt context once at init
time (rev2)
URL : https://patchwork.freedesktop.org/series/38975/
State : success
== Summary ==
Possible new issues:
Test drv_missed_irq:
pass -> SKIP (shard-apl
On Mon, 2018-02-26 at 15:12 -0800, Rodrigo Vivi wrote:
> On Fri, Feb 23, 2018 at 03:46:09PM -0800, Pandiyan, Dhinakaran wrote:
> > On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> > > It is a fact that scheduled work is now improved.
> > >
> > > But it is also a fact that on core platfo
Quoting Oscar Mateo (2018-02-26 23:01:50)
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index 41dc881..e41678f 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst
> @@ -58,6 +58,12 @@ Intel GVT-g Host Support(vGPU device model)
> .. kernel-doc::
On Mon, 2018-02-26 at 15:08 -0800, Rodrigo Vivi wrote:
> On Fri, Feb 23, 2018 at 04:24:35PM -0800, Pandiyan, Dhinakaran wrote:
> > On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> > > WA 0884:bxt:all,cnl:*:A - "When FBC is enabled with eDP PSR,
> > > the CPU host modify writes may not get u
On Fri, Feb 23, 2018 at 03:46:09PM -0800, Pandiyan, Dhinakaran wrote:
> On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> > It is a fact that scheduled work is now improved.
> >
> > But it is also a fact that on core platforms that shouldn't
> > be needed. We only need to actually wait on V
On Fri, Feb 23, 2018 at 04:24:35PM -0800, Pandiyan, Dhinakaran wrote:
> On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> > WA 0884:bxt:all,cnl:*:A - "When FBC is enabled with eDP PSR,
> > the CPU host modify writes may not get updated on the Display
> > as expected.
> > WA: Write 0x
On Fri, Feb 23, 2018 at 04:40:38PM -0800, Pandiyan, Dhinakaran wrote:
> On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> > Host/Render modifications do not trigger PSR exit
> > or Wireless quick capture exit correctly.
> >
>
> I don't get this workaround either. The wording indicates fron
On 2/25/2018 9:22 PM, Sagar Arun Kamble wrote:
On 2/23/2018 4:35 AM, Oscar Mateo wrote:
+ * We might have detected that some engines are fused off after we
initialized
+ * the forcewake domains. Prune them, to make sure they only
reference existing
+ * engines.
+ */
+void intel_uncore
This has grown to be a sizable amount of code, so move it to
its own file before we try to refactor anything. For the moment,
we are leaving behind the WA BB code and the WAs that get applied
(incorrectly) in init_clock_gating, but we will deal with it later.
v2: Use intel_ prefix for code that de
Quoting Ramalingam C (2018-02-26 17:12:39)
> DP and HDMI HDCP specifications are varying with respect to
> detecting the R0 and ksv_fifo availability.
>
> DP will produce CP_IRQ and set a bit for indicating the R0 and
> FIFO_READY status.
>
> Whereas HDMI will set a bit for FIFO_READY but there i
== Series Details ==
Series: drm/i915: expose RCS topology to userspace (rev2)
URL : https://patchwork.freedesktop.org/series/38981/
State : success
== Summary ==
Possible new issues:
Test pm_sseu:
Subgroup full-enable:
pass -> FAIL (shard-apl)
K
On Mon, Feb 26, 2018 at 01:48:37PM -0800, José Roberto de Souza wrote:
> When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> self, so lets use the mutex register that is available in gen9+ to
> avoid concurrent access by hardware and driver.
> Older gen handling will be done separ
== Series Details ==
Series: drm/i915: Add and enable DP AUX CH mutex (rev3)
URL : https://patchwork.freedesktop.org/series/38655/
State : success
== Summary ==
Series 38655v3 drm/i915: Add and enable DP AUX CH mutex
https://patchwork.freedesktop.org/api/1.0/series/38655/revisions/3/mbox/
---
On Mon, Feb 26, 2018 at 09:00:50PM +, Chris Wilson wrote:
> Quoting Rodrigo Vivi (2018-02-26 20:53:08)
> > -void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
> > -{
> > - struct intel_fbc *fbc = &dev_priv->fbc;
> > -
> > - if (!fbc_supported(dev_priv))
> > -
== Series Details ==
Series: HDCP1.4 fixes
URL : https://patchwork.freedesktop.org/series/38978/
State : success
== Summary ==
Known issues:
Test kms_cursor_legacy:
Subgroup short-flip-after-cursor-atomic-transitions-varying-size:
pass -> SKIP (shard-s
On Mon, Feb 26, 2018 at 09:21:19PM +, Chris Wilson wrote:
> Quoting Rodrigo Vivi (2018-02-26 20:53:07)
> > Now that we are spreading the places we can manipulate
> > sagv status let's protect it.
>
> This needs a lot more information about the protection you need. "sagv
> status" is too simila
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/guc: Fill preempt context once
at init time
URL : https://patchwork.freedesktop.org/series/38975/
State : success
== Summary ==
Possible new issues:
Test drv_missed_irq:
pass -> SKIP (shard-a
v2
- removed the PSR dependency, now getting lock all the times when available
- renamed functions to avoid nested calls
- moved register bits right after the DP_AUX_CH_MUTEX()
- removed 'drm/i915: keep AUX powered while PSR is enabled' Dhinakaran Pandiyan
will sent a better and final version
v3
-
When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
self, so lets use the mutex register that is available in gen9+ to
avoid concurrent access by hardware and driver.
Older gen handling will be done separated.
Reference:
https://01.org/sites/default/files/documentation/intel-gfx-p
Quoting Ville Syrjälä (2018-02-26 21:22:03)
> On Mon, Feb 26, 2018 at 08:54:47PM +, Chris Wilson wrote:
> > Quoting Chris Wilson (2018-02-24 18:54:04)
> > > If the specified object can not fit into the GTT due to overlap with a
> > > neighbouring pinned object (not part of the execobjects[]), w
== Series Details ==
Series: series starting with [1/4] drm/i915: Don't propagate SAGV errnos in
vain.
URL : https://patchwork.freedesktop.org/series/38987/
State : failure
== Summary ==
Applying: drm/i915: Don't propagate SAGV errnos in vain.
error: sha1 information is lacking or useless
(d
On Mon, Feb 26, 2018 at 08:54:47PM +, Chris Wilson wrote:
> Quoting Chris Wilson (2018-02-24 18:54:04)
> > If the specified object can not fit into the GTT due to overlap with a
> > neighbouring pinned object (not part of the execobjects[]), we expect to
> > fail with ENOSPC (as we cannot evict
Quoting Rodrigo Vivi (2018-02-26 20:53:07)
> Now that we are spreading the places we can manipulate
> sagv status let's protect it.
This needs a lot more information about the protection you need. "sagv
status" is too similar to sagv_status, so it seems like you are simply
talking about protecting
Quoting Rodrigo Vivi (2018-02-26 20:53:08)
> -void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
> -{
> - struct intel_fbc *fbc = &dev_priv->fbc;
> -
> - if (!fbc_supported(dev_priv))
> - return;
> -
> - /* There's no guarantee that underrun_d
Quoting Chris Wilson (2018-02-24 18:54:04)
> If the specified object can not fit into the GTT due to overlap with a
> neighbouring pinned object (not part of the execobjects[]), we expect to
> fail with ENOSPC (as we cannot evict, rather than EINVAL for the user
> error in a badly constructed execo
We never used this information on upper level.
So let's just print the error and make the functions void.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_pm.c | 26 +++---
2 files changed, 13 insertions(+), 17 deletions(
This underrun work can be useful to disable more pm
function that can cause trouble on underrun situations,
like SAGV.
Cc: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h| 7 +++-
drivers/gpu/drm/i915/i915_irq.c| 2 ++
drivers/gpu/drm/i915/
On underrun situations and SAGV enabled we can face hard hangs.
So let's reuse the FBC workaround and expand that to SAGV
on the hope that it is not already too late for that.
Cc: Paulo Zanoni
Cc: Ashar Shaikh
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_drv.h | 2 ++
Now that we are spreading the places we can manipulate
sagv status let's protect it.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 15 +--
drivers/gpu/drm/i915/intel_pm.c | 41 ++---
2 files changed, 35 insertions(+), 21 deletio
Quoting Daniele Ceraolo Spurio (2018-02-26 16:57:11)
>
>
> On 25/02/18 22:17, Sagar Arun Kamble wrote:
> >
> >
> > On 2/23/2018 10:31 PM, Daniele Ceraolo Spurio wrote:
> >>
> >>
> >> On 23/02/18 06:04, Michal Wajdeczko wrote:
> >>> Right after GPU reset there will be a small window of time duri
On Mon, 2018-02-26 at 18:31 +, Souza, Jose wrote:
> On Fri, 2018-02-23 at 19:12 -0800, Pandiyan, Dhinakaran wrote:
> > On Fri, 2018-02-23 at 17:51 -0800, José Roberto de Souza wrote:
> > > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> > > self, so lets use the mutex r
== Series Details ==
Series: kernel: Downgrade warning for unsafe parameters (rev2)
URL : https://patchwork.freedesktop.org/series/38614/
State : success
== Summary ==
Possible new issues:
Test kms_vblank:
Subgroup pipe-a-query-busy:
pass -> SKIP (shar
== Series Details ==
Series: series starting with drm/i915/guc: Fill preempt context once at init
time (rev2)
URL : https://patchwork.freedesktop.org/series/38975/
State : success
== Summary ==
Series 38975v2 series starting with drm/i915/guc: Fill preempt context once at
init time
https://p
== Series Details ==
Series: drm/i915: expose RCS topology to userspace (rev2)
URL : https://patchwork.freedesktop.org/series/38981/
State : success
== Summary ==
Series 38981v2 drm/i915: expose RCS topology to userspace
https://patchwork.freedesktop.org/api/1.0/series/38981/revisions/2/mbox/
== Series Details ==
Series: drm/i915: expose RCS topology to userspace (rev2)
URL : https://patchwork.freedesktop.org/series/38981/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: store all subslice masks
Okay!
Commit: drm/i915/debugfs: reuse max slice/subslices a
From: Michał Winiarski
Since we're inhibiting context save of preempt context, we're no longer
tracking the position of HEAD/TAIL. With GuC, we're adding a new
breadcrumb for each preemption, which means that the HW will do more and
more breadcrumb writes. Eventually the ring is filled, and we're
On Fri, Feb 23, 2018 at 05:51:40PM -0800, José Roberto de Souza wrote:
> When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> self, so lets use the mutex register that is available in gen9+ to
> avoid concurrent access by hardware and driver.
> Older gen handling will be done separ
On Fri, 2018-02-23 at 19:12 -0800, Pandiyan, Dhinakaran wrote:
> On Fri, 2018-02-23 at 17:51 -0800, José Roberto de Souza wrote:
> > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> > self, so lets use the mutex register that is available in gen9+ to
> > avoid concurrent access
Up to now, subslice mask was assumed to be uniform across slices. But
starting with Cannonlake, slices can be asymmetric (for example slice0
has different number of subslices as slice1+). This change stores all
subslices masks for all slices rather than having a single mask that
applies to all slic
== Series Details ==
Series: kernel/panic: Repeat the line and caller information at the end of the
OOPS (rev2)
URL : https://patchwork.freedesktop.org/series/38962/
State : success
== Summary ==
Possible new issues:
Test pm_rc6_residency:
Subgroup rc6-accuracy:
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: Fill preempt context once at
init time
URL : https://patchwork.freedesktop.org/series/38964/
State : success
== Summary ==
Possible new issues:
Test drv_missed_irq:
pass -> SKIP (shard-apl)
== Series Details ==
Series: drm/i915: expose RCS topology to userspace
URL : https://patchwork.freedesktop.org/series/38981/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
CHK
On Mon, Feb 26, 2018 at 10:42:39PM +0530, Ramalingam C wrote:
> DP and HDMI HDCP specifications are varying with respect to
> detecting the R0 and ksv_fifo availability.
>
> DP will produce CP_IRQ and set a bit for indicating the R0 and
> FIFO_READY status.
I'm not sure what the benefit is? Keepi
There are a number of information that are readable from hardware
registers and that we would like to make accessible to userspace. One
particular example is the topology of the execution units (how are
execution units grouped in subslices and slices and also which ones
have been fused off for die
Hi all,
Here is another update to fix a couple of bugs in the first patch :
- HSW was reporting the eu masks incorrectly
- debugfs was reporting incorrect subslice numbers (and failing
igt@pm_sseu), the igt has been update to handle kernels before and
after this series.
Cheers,
Lionel
With the introduction of asymmetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam to tell userspace what subslices
are available. Here we introduce a more detailed way of querying the
Gen's GPU topology that doesn't aggregate numbers.
This is essential for monitoring parts o
This might be useful information for developers looking at an error
state.
v2: Place topology towards the end of the error state (Chris)
v3: Reuse common printing code (Michal)
v4: Make this a one-liner (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
Acked-by: Chris Wilso
Up to now, subslice mask was assumed to be uniform across slices. But
starting with Cannonlake, slices can be asymmetric (for example slice0
has different number of subslices as slice1+). This change stores all
subslices masks for all slices rather than having a single mask that
applies to all slic
While the end goal is to make this information available to userspace
through a new ioctl, there is no reason we can't display it in a human
readable fashion through debugfs.
slice0: 3 subslice(s) (0x7):
subslice0: 8 EUs (0xff)
subslice1: 8 EUs (0xff)
subslice2: 8 EUs (0xff
Now that we have that information in topology fields, let's just reuse it.
v2: Style tweaks (Tvrtko)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
Acked-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 27 +++
drivers/gpu/drm/i915/intel_de
On Mon, Feb 26, 2018 at 10:42:38PM +0530, Ramalingam C wrote:
> In a connected state, If a HDMI HDCP sink is responded with NACK for
> HDCP I2C register access, then HDMI HDCP spec mandates the polling
> of any HDCP space registers for accessibility, minimum once in 2Secs
> atleast for 4Secs.
>
I
On Mon, Feb 26, 2018 at 10:42:37PM +0530, Ramalingam C wrote:
> HDCP1.4 key can be loaded, only when Power well #1 is enabled and cdclk
> is enabled. Using the I915 power well infrastruture, above requirement
> is verified.
>
> This patch enables the hdcp initialization for HSW, BDW, and BXT.
>
>
== Series Details ==
Series: HDCP1.4 fixes
URL : https://patchwork.freedesktop.org/series/38978/
State : success
== Summary ==
Series 38978v1 HDCP1.4 fixes
https://patchwork.freedesktop.org/api/1.0/series/38978/revisions/1/mbox/
Known issues:
Test debugfs_test:
Subgroup read_all
On Mon, Feb 26, 2018 at 10:42:36PM +0530, Ramalingam C wrote:
> In case of V prime mismatch, DP HDCP spec mandates the re-read of
> Vprime atleast twice.
>
> DP HDCP CTS Test: 1B-05
>
> Signed-off-by: Ramalingam C
> ---
> drivers/gpu/drm/i915/intel_hdcp.c | 10 +-
> 1 file changed, 9 in
On Mon, Feb 26, 2018 at 10:42:35PM +0530, Ramalingam C wrote:
> As per DP spec when R0 mismatch is detected, HDCP source supported
> re-read the R0 atleast twice.
>
> And For HDMI and DP minimum wait required for the R0 availability is
> 100mSec. So this patch changes the wait time to 100mSec but
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/guc: Fill preempt context once
at init time
URL : https://patchwork.freedesktop.org/series/38975/
State : success
== Summary ==
Series 38975v1 series starting with [v2,1/2] drm/i915/guc: Fill preempt context
once at init tim
DP and HDMI HDCP specifications are varying with respect to
detecting the R0 and ksv_fifo availability.
DP will produce CP_IRQ and set a bit for indicating the R0 and
FIFO_READY status.
Whereas HDMI will set a bit for FIFO_READY but there is no bit
indication for R0 ready. And also polling of REA
In a connected state, If a HDMI HDCP sink is responded with NACK for
HDCP I2C register access, then HDMI HDCP spec mandates the polling
of any HDCP space registers for accessibility, minimum once in 2Secs
atleast for 4Secs.
Just to make it simple, this is generically implemented for both HDMI
and
As per DP spec when R0 mismatch is detected, HDCP source supported
re-read the R0 atleast twice.
And For HDMI and DP minimum wait required for the R0 availability is
100mSec. So this patch changes the wait time to 100mSec but retries
twice with the time interval of 100mSec for each attempt.
DP CT
In case of V prime mismatch, DP HDCP spec mandates the re-read of
Vprime atleast twice.
DP HDCP CTS Test: 1B-05
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/dr
HDCP1.4 key can be loaded, only when Power well #1 is enabled and cdclk
is enabled. Using the I915 power well infrastruture, above requirement
is verified.
This patch enables the hdcp initialization for HSW, BDW, and BXT.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 31 ++
This series addresses the requriement of below HDCP compliance tests
DP: 1A-06 and 1B-05
HDMI: 1A-04 and 1A-07a
One of the patch uses the I915 power infra-structure for checking
the power state of PW#1. Which enables the init path for all legacy
platforms.
And encoder specific msg
On 25/02/18 22:17, Sagar Arun Kamble wrote:
On 2/23/2018 10:31 PM, Daniele Ceraolo Spurio wrote:
On 23/02/18 06:04, Michal Wajdeczko wrote:
Right after GPU reset there will be a small window of time during which
some of GuC/HuC fields will still show state before reset. Let's start
to fix
Since we're inhibiting context save of preempt context, we're no longer
tracking the position of HEAD/TAIL. With GuC, we're adding a new
breadcrumb for each preemption, which means that the HW will do more and
more breadcrumb writes. Eventually the ring is filled, and we're
submitting the preemptio
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c| 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 430f5f9d0ff4..3deae1e22974 100644
--- a/drivers/gpu/drm/i915/i915_p
On Mon, 26 Feb 2018, Chris Wilson wrote:
> Quoting Jani Nikula (2018-02-26 14:00:37)
>> On Thu, 22 Feb 2018, Tvrtko Ursulin wrote:
>> > From: Tvrtko Ursulin
>> >
>> > Introduce subplatform mask to eliminate throughout the code devid checking
>> > sprinkle, mostly courtesy of IS_*_UL[TX] macros.
On Mon, Feb 26, 2018 at 04:41:09PM +0200, Imre Deak wrote:
> On Sun, Feb 25, 2018 at 12:42:30AM +0100, Lukas Wunner wrote:
> > DRM drivers need to tell vga_switcheroo whether they use runtime PM.
> > If they do use it, vga_switcheroo lets them autosuspend at their own
> > discretion. If on the oth
Quoting Jani Nikula (2018-02-26 14:00:37)
> On Thu, 22 Feb 2018, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > Introduce subplatform mask to eliminate throughout the code devid checking
> > sprinkle, mostly courtesy of IS_*_UL[TX] macros.
> >
> > Subplatform mask initialization is moved
== Series Details ==
Series: kernel: Downgrade warning for unsafe parameters (rev2)
URL : https://patchwork.freedesktop.org/series/38614/
State : success
== Summary ==
Series 38614v2 kernel: Downgrade warning for unsafe parameters
https://patchwork.freedesktop.org/api/1.0/series/38614/revision
On Mon, 26 Feb 2018, Chris Wilson wrote:
> As using an unsafe module parameter is, by its very definition, an
> expected user action, emitting a warning is overkill. Nothing has yet
> gone wrong, and we add a taint flag for any future oops should
> something actually go wrong. So instead of having
In investigating the issue with having to force preemption within the
executing ELSP[], we want to trigger preemption between all elements of
that array. To that end, we issue a series of requests with different
priorities to fill the in-flight ELSP[] and then demand preemption into
the middle of t
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