On Thu, Feb 22, 2018 at 12:05:35PM -0800, Rodrigo Vivi wrote:
> Old Wa added now forever on CNL all steppings.
>
> With CPU P states enabled along with RC6, dispatcher
> hangs can happen.
>
> Cc: Rafael Antognolli <rafael.antogno...@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.srip...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 5 +++--
> drivers/gpu/drm/i915/intel_guc.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 3 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 82a106b1bdbc..7bbec5546d12 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2788,9 +2788,10 @@ intel_info(const struct drm_i915_private *dev_priv)
> /* Early gen2 have a totally busted CS tlb and require pinned batches. */
> #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) ||
> IS_I845G(dev_priv))
>
> -/* WaRsDisableCoarsePowerGating:skl,bxt */
> +/* WaRsDisableCoarsePowerGating:skl,cnl */
> #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
> - (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
> + (IS_CANNONLAKE(dev_priv) || \
> + IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
>
> /*
> * dp aux and gmbus irq on gen4 seems to be able to generate legacy
> interrupts
> diff --git a/drivers/gpu/drm/i915/intel_guc.c
> b/drivers/gpu/drm/i915/intel_guc.c
> index 21140ccd7a97..e6512cccef75 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -370,7 +370,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc)
> u32 action[2];
>
> action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
> - /* WaRsDisableCoarsePowerGating:skl,bxt */
> + /* WaRsDisableCoarsePowerGating:skl,cnl */
> if (!HAS_RC6(dev_priv) || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
> action[1] = 0;
> else
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 731b3808a62e..c5e495dfa387 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6695,7 +6695,7 @@ static void gen9_enable_rc6(struct drm_i915_private
> *dev_priv)
>
> /*
> * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> - * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be
> disabled with RC6.
> + * WaRsDisableCoarsePowerGating:skl,cnl - Render/Media PG need to be
> disabled with RC6.
> */
> if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
> I915_WRITE(GEN9_PG_ENABLE, 0);
> --
> 2.13.6
>
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> Intel-gfx@lists.freedesktop.org
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