== Series Details ==
Series: series starting with [1/2] drm/dp: Add defines for latency in sink
URL : https://patchwork.freedesktop.org/series/30797/
State : success
== Summary ==
shard-hswtotal:2429 pass:1329 dwarn:5 dfail:0 fail:12 skip:1083
time:9777s
== Logs ==
For more det
== Series Details ==
Series: series starting with [1/2] drm/dp: Add defines for latency in sink
URL : https://patchwork.freedesktop.org/series/30797/
State : success
== Summary ==
Series 30797v1 series starting with [1/2] drm/dp: Add defines for latency in
sink
https://patchwork.freedesktop.o
Add defines for dpcd register 2009 (synchronization latency
in sink).
Cc: Rodrigo Vivi
CC: Puthikorn Voravootivat
Reviewed-by: Rodrigo Vivi
Signed-off-by: Vathsala Nagaraju
---
include/drm/drm_dp_helper.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/inc
Set frames before SU entry value for max resync frame count of
dpcd register 2009, bit field 0:3.
v2 :
- add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
- remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
- add check ==1 for dpcd_read call (ville)
v3 : (Rodrigo)
- move macro EDP_PSR2_FRAME_BEFORE_SU
On Fri, Sep 22, 2017 at 03:58:36PM +, vathsala nagaraju wrote:
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit field 0:3.
>
> v2 :
> - add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
> - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
> - add check ==1 f
== Series Details ==
Series: huge gtt pages (rev8)
URL : https://patchwork.freedesktop.org/series/25118/
State : failure
== Summary ==
Test perf:
Subgroup blocking:
pass -> FAIL (shard-hsw) fdo#102252
Test kms_flip:
Subgroup plain-flip-ts-check-inter
== Series Details ==
Series: series starting with [1/6] lib/igt_kms: Don't assert on non-existent
plane
URL : https://patchwork.freedesktop.org/series/30706/
State : success
== Summary ==
Test gem_eio:
Subgroup throttle:
pass -> DMESG-WARN (shard-hsw) fdo#102886
== Series Details ==
Series: Add missing BXT/CNL DPLL debugging/checking code
URL : https://patchwork.freedesktop.org/series/30790/
State : failure
== Summary ==
Series 30790v1 Add missing BXT/CNL DPLL debugging/checking code
https://patchwork.freedesktop.org/api/1.0/series/30790/revisions/1/m
These 2 patches just add the missing struct fields to the relevant parts of the
code. Future patches could probably break those structs into per-platform struct
inside an unions or something like that, but let's get this part done first.
Paulo Zanoni (2):
drm/i915: add the BXT and CNL DPLL regis
Looks like we were missing them.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 026fa54..64a4105 100644
--- a/drivers/gpu/drm
Looks like we've been forgetting to add these since a long time ago.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_debugfs.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 13fc259.
== Series Details ==
Series: drm/i915: enable userspace to program slice/subslice programming (rev2)
URL : https://patchwork.freedesktop.org/series/29715/
State : failure
== Summary ==
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-indfb-draw-blt:
skip
Sending to intel-gfx.
>-Original Message-
>From: Ursulin, Tvrtko
>Sent: Thursday, September 21, 2017 8:16 AM
>To: Srivatsa, Anusha ; intel-
>g...@lists.freedektop.org
>Cc: Chris Wilson ; Vetter, Daniel
>; Sundaresan, Sujaritha
>; Mateo Lozano, Oscar
>; Wajdeczko, Michal
>Subject: RE: [PA
== Series Details ==
Series: series starting with [RFC,1/3] drm/i915: Make I915_PARAMS_FOR_EACH
macro more flexible
URL : https://patchwork.freedesktop.org/series/30768/
State : failure
== Summary ==
Test kms_setmode:
Subgroup basic:
pass -> FAIL (shard-hsw
On Fri, 22 Sep 2017, Chris Wilson wrote:
> Quoting Michal Wajdeczko (2017-09-22 15:27:25)
>> By combining default value into helper macro we can initialize
>> modparams struct in the same automatic way as it was declared.
>> This will initialize members in the same order as declared
>> and additio
== Series Details ==
Series: series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu
configs (rev2)
URL : https://patchwork.freedesktop.org/series/30669/
State : success
== Summary ==
Test perf:
Subgroup blocking:
pass -> FAIL (shard-hsw) fdo
On Fri, Sep 22, 2017 at 04:44:38PM +, Oscar Mateo wrote:
>
>
> On 09/22/2017 06:15 AM, Rodrigo Vivi wrote:
> > CNL adds an extra register for slice/subslice information.
> > Although no SKU is planed with an extra slice let's already
> > handle this extra piece of information so we don't have
On 2017.09.22 18:32:50 +0100, Matthew Auld wrote:
> Currently gvt gtt handling doesn't support huge page entries, so disable
> for now.
>
> v2: remove useless 48b PPGTT check
>
> Suggested-by: Zhenyu Wang
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Chris Wilson
> Cc: Zhenyu Wang
== Series Details ==
Series: huge gtt pages (rev8)
URL : https://patchwork.freedesktop.org/series/25118/
State : success
== Summary ==
Series 25118v8 huge gtt pages
https://patchwork.freedesktop.org/api/1.0/series/25118/revisions/8/mbox/
Test chamelium:
Subgroup common-hpd-after-suspe
On Thu, Sep 21, 2017 at 11:54 AM, Dhinakaran Pandiyan
wrote:
> Rewriting this code without the goto, I believe, makes it more readable.
> One functional change that has been included is the handling of failed ESI
> register reads. Instead of disabling MST only for the first failed read, we
> now d
Thanks for the reply. Learned a lot. :)
GEM_BUG_ON is new to me since it wasn't there at the beginning of GVT-g
upstream. It showed up later. So I left a lot of WARN_ON in the code and some
of them should be GEM_BUG_ON now.
Now I can figure out those differences. We can discuss with our QA to s
Before we can enable 64K pages through the IPS bit, we must first enable
it through MMIO, otherwise the page-walker will simply ignore it.
v2: add comment mentioning that 64K is BDW+
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 16
Support inserting 64K pages into the 48b PPGTT.
v2: check for 64K scratch
v3: we should only have to re-adjust maybe_64K at every sg interval
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 30 ++
drivers/
For gen9+ enable platform level support for 64K pages. Also enable for
mock testing.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 ++-
2 files changed, 4 inser
For gen8+ platforms which support the 48b PPGTT, enable platform level
support for 2M pages. Also enable for mock testing.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_pci.c | 6 --
drivers/gpu/drm/i915/selftests/mock_gem_d
v2: mock test page support configurations and add MI_STORE_DWORD test
v3: run all mockable huge page tests on all platforms via the mock_device
v4: add pin_update regression test
various improvements suggested by Chris
v5: fix issues reported by kbuild
test single sg spanning multiple pa
Good to know, mostly for debugging purposes.
v2: some improvements from Chris
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 61 ++---
1 file changed, 57 insertions(+), 4 deletions(-)
diff --git a/dri
Try to mix sg page sizes for 4K, 64K and 2M pages.
v2: s/BIT(x) >> 12/BIT(x) >> PAGE_SHIFT/
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/selftests/scatterlist.c | 15 +++
1 file changed, 15 insertions(+)
dif
Currently gvt gtt handling doesn't support huge page entries, so disable
for now.
v2: remove useless 48b PPGTT check
Suggested-by: Zhenyu Wang
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Zhenyu Wang
---
drivers/gpu/drm/i915/i915_gem.c | 8
1 file changed, 8
When SW enables the use of 2M/1G pages, it must disable the GTT cache.
v2: don't disable for Cherryview which doesn't even support 48b PPGTT!
v3: explicitly check that the system does support 2M/1G pages
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i91
Now that we support multiple page sizes for the ppgtt, it would be
useful to track the real usage for debugging purposes.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c| 11 +++
drivers/gpu/drm/i915/i915_gem_object.h | 10 ++
Before we can fully enable 64K pages, we need to first support a 64K
scratch page if we intend to support the case where we have object sizes
< 2M, since any scratch PTE must also point to a 64K region. Without
this our 64K usage is limited to objects which completely fill the
page-table, and ther
We are planning to use our own tmpfs mnt in i915 in place of the
shm_mnt, such that we can control the mount options, in particular
huge=, which we require to support huge-gtt-pages. So rather than roll
our own version of __shmem_file_setup, it would be preferred if we could
just give shmem our mnt
Support inserting 2M gtt pages into the 48b PPGTT.
v2: sanity check sg->length against page_size
v3: don't recalculate rem on each loop
whitespace breakup
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 78 +++
Bunch of changes all round, mostly in the kselftest department, of note we drop
support for 1G pages for the time being, since testing has proven to be a pita,
and instead focus on getting the 64K and 2M support landed.
Matthew Auld (21):
mm/shmem: introduce shmem_file_setup_with_mnt
drm/i915:
Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so
moves us away from the shmemfs shm_mnt, and gives us the much needed
flexibility to do things like set our own mount options, namely huge=
which should allow us to enable the use of transparent-huge-pages for
our shmem backed o
For the 48b PPGTT try to align the vma start address to the required
page size boundary to guarantee we use said page size in the gtt. If we
are dealing with multiple page sizes, we can't guarantee anything and
just align to the largest. For soft pinning and objects which need to be
tightly packed
Move the setting/clearing of the vma->pages to a vm operation. Doing so
neatens things up a little, but more importantly gives us a sane place
to also set/clear the vma->pages_sizes, which we introduce later in
preparation for supporting huge-pages.
v2: remove redundant vma->pages check
v3: GEM_B
In preparation for huge gtt pages expose page_sizes as part of the
device info, to indicate the page sizes supported by the HW. Currently
only 4K is supported.
v2: s/page_size_mask/page_sizes/
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Chris Wilson
Reviewed-by: Joo
We can't mix 64K and 4K pte's in the same page-table, so for now we
align 64K objects to 2M to avoid any potential mixing. This is
potentially wasteful but in reality shouldn't be too bad since this only
applies to the virtual address space of a 48b PPGTT.
v2: don't separate logically connected op
In preparation for supporting huge gtt pages for the ppgtt, we introduce
page size members for gem objects. We fill in the page sizes by
scanning the sg table.
v2: pass the sg_mask to set_pages
v3: calculate the sg_mask inline with populating the sg_table where
possible, and pass to set_pages al
Each backend is now responsible for calling __i915_gem_object_set_pages
upon successfully gathering its backing storage. This eliminates the
inconsistency between the async and sync paths, which stands out even
more when we start throwing around an sg_mask in a later patch.
Suggested-by: Chris Wil
Enable transparent-huge-pages through gemfs by mounting with
huge=within_size.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gemfs.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gemfs.c
b/drivers
== Series Details ==
Series: drm/i915: Make i915_spin_request() static
URL : https://patchwork.freedesktop.org/series/30757/
State : success
== Summary ==
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
Test kms_flip:
Subgroup fl
On 09/22/2017 06:15 AM, Rodrigo Vivi wrote:
CNL adds an extra register for slice/subslice information.
Although no SKU is planed with an extra slice let's already
handle this extra piece of information so we don't have the
risk in future of getting a part that might have chosen this
part of the
== Series Details ==
Series: tests: add slice power programming test (rev2)
URL : https://patchwork.freedesktop.org/series/29717/
State : failure
== Summary ==
IGT patchset build failed on latest successful build
b94a17d13fb5e03bbc7ef50ce88352b37ad06c85 tests/psr: Don't strcmp CRCs that are
n
== Series Details ==
Series: igt/gem_exec_schedule: Fix up too deep reorder-wide()
URL : https://patchwork.freedesktop.org/series/30765/
State : failure
== Summary ==
Series 30765 revision 1 was fully merged or fully failed: no git log
___
Intel-gfx
== Series Details ==
Series: tests/kms_frontbuffer_tracking: Try harder to collect CRC's
URL : https://patchwork.freedesktop.org/series/30760/
State : warning
== Summary ==
IGT patchset tested on top of latest successful build
b94a17d13fb5e03bbc7ef50ce88352b37ad06c85 tests/psr: Don't strcmp CR
From: Uma Shankar
For certain platforms on certain encoders, timings are driven
from port instead of pipe. Thus, we can't rely on pipe scanline
registers to get the timing information. Some cases scanline
register read will not be functional.
This is causing vblank evasion logic to fail since it
Set frames before SU entry value for max resync frame count of
dpcd register 2009, bit field 0:3.
v2 :
- add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
- remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
- add check ==1 for dpcd_read call (ville)
Cc: Rodrigo Vivi
CC: Puthikorn Voravootivat
Signed-o
== Series Details ==
Series: series starting with [1/6] lib/igt_kms: Don't assert on non-existent
plane
URL : https://patchwork.freedesktop.org/series/30706/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
b94a17d13fb5e03bbc7ef50ce88352b37ad06c85 tests/psr:
On Fri, Sep 22, 2017 at 09:11:30PM +0530, Vidya Srinivas wrote:
> From: Uma Shankar
>
> For certain platforms on certain encoders, timings are driven
> from port instead of pipe. Thus, we can't rely on pipe scanline
> registers to get the timing information. Some cases scanline
> register read wi
On Thu, Sep 21, 2017 at 08:36:33PM +0200, Thomas Richter wrote:
> Hi Daniel, hi Ville,
>
> thanks for integrating my patches of the DVO chip of my old IBM R31.
> With this patch in place, dithering on the laptop works now.
>
> However, I recently upgraded to Debian Stretch, and since then, I'm
>
== Series Details ==
Series: drm/i915: enable userspace to program slice/subslice programming (rev2)
URL : https://patchwork.freedesktop.org/series/29715/
State : success
== Summary ==
Series 29715v2 drm/i915: enable userspace to program slice/subslice programming
https://patchwork.freedesktop
From: Uma Shankar
For certain platforms on certain encoders, timings are driven
from port instead of pipe. Thus, we can't rely on pipe scanline
registers to get the timing information. Some cases scanline
register read will not be functional.
This is causing vblank evasion logic to fail since it
Maybe we are missing a vblank wait somewhere on kernel CRC code?!
Or maybe o kernel we read and discard the first for GLK?! :/
Also this is pipe crc right?! Shouldn't it be independent of the panel at
the end?! Does it only happen with MIPI/DSI ?! Or it just happen on that
particular unity on CI th
Quoting Lionel Landwerlin (2017-09-22 16:11:33)
> Verifies that the kernel programs slices correctly based by reading
> the value of PWR_CLK_STATE register.
>
> v2: Add subslice tests (Lionel)
> Use MI_SET_PREDICATE for further verification when available (Lionel)
Since this is being created
Quoting Michal Wajdeczko (2017-09-22 15:27:26)
> Members should be initialized with values of matching types.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
Reviewed-by: Chris Wilson
Perhaps typecheck(T, value) could sneak in somewhere. Add a
Quoting Michal Wajdeczko (2017-09-22 15:27:25)
> By combining default value into helper macro we can initialize
> modparams struct in the same automatic way as it was declared.
> This will initialize members in the same order as declared
> and additionally will disallow declaring new member without
Quoting Michal Wajdeczko (2017-09-22 15:27:24)
> We should not add trailing ; after each member allow other
> than statements-style uses of this helper macro.
> While here s/func/param for clarity.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
> Cc: Jani Nikula
Ok, looks like the trai
== Series Details ==
Series: series starting with [RFC,1/3] drm/i915: Make I915_PARAMS_FOR_EACH
macro more flexible
URL : https://patchwork.freedesktop.org/series/30768/
State : success
== Summary ==
Series 30768v1 series starting with [RFC,1/3] drm/i915: Make
I915_PARAMS_FOR_EACH macro more
Verifies that the kernel programs slices correctly based by reading
the value of PWR_CLK_STATE register.
v2: Add subslice tests (Lionel)
Use MI_SET_PREDICATE for further verification when available (Lionel)
Signed-off-by: Lionel Landwerlin
---
tests/Makefile.sources | 1 +
tests/ctx_rpcs.
This function will be used later by the per (context,engine) power
programming interface.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h| 3 +++
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 18 +-
2 files changed, 12 insertions(+), 9 deletions(-
From: Chris Wilson
We want to allow userspace to reconfigure the subslice configuration for
its own use case. To do so, we expose a context parameter to allow
adjustment of the RPCS register stored within the context image (and
currently not accessible via LRI). If the context is adjusted before
Hi,
A small update to all userspace to select the engine to which the
slice/subslice configuration applies (as suggested by Chris).
Cheers,
Chris Wilson (4):
drm/i915: Record both min/max eu_per_subslice in sseu_dev_info
drm/i915: Program RPCS for Broadwell
drm/i915: Record the sseu config
From: Chris Wilson
Currently we only configure the power gating for Skylake and above, but
the configuration should equally apply to Broadwell and Braswell. Even
though, there is not as much variation as for later generations, we want
to expose control over the configuration to userspace and may
From: Chris Wilson
When we query the available eu on each subslice, we currently only
report the max. It would also be useful to report the minimum found as
well.
When we set RPCS (power gating over the EU), we can also specify both
the min and max number of eu to configure on each slice; curren
From: Chris Wilson
We want to expose the ability to reconfigure the slices, subslice and
eu per context and per engine. To facilitate that, store the current
configuration on the context for each engine, which is initially set
to the device default upon creation.
v2: record sseu configuration pe
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, September 22, 2017 6:58 PM
>To: Srinivas, Vidya
>Cc: intel-gfx@lists.freedesktop.org; Kahola, Mika ;
>Kamath, Sunil ; Shankar, Uma
>; Konduru, Chandra
>Subject: Re: [PATCH] drm/i915: Enable sc
Prepared intel_auth_huc to separate HuC specific functionality
from GuC send action. Created new header intel_huc.h to group
HuC specific declarations.
v2: Changed argument preparation for AUTHENTICATE_HUC.
s/intel_auth_huc/intel_huc_auth. Deferred creation of intel_huc.h
to later patch.
v3: Reba
On 9/22/2017 5:34 PM, Joonas Lahtinen wrote:
On Fri, 2017-09-22 at 15:37 +0530, Sagar Arun Kamble wrote:
With GuC v9, new type of Default/critical logging in GuC to enable
capturing minimal important logs in production systems efficiently.
This patch enables this logging in GuC by default alwa
== Series Details ==
Series: series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu
configs (rev2)
URL : https://patchwork.freedesktop.org/series/30669/
State : success
== Summary ==
Series 30669v2 series starting with [1/2] drm/i915/cnl: Add support
slice/subslice/eu configs
On 9/22/2017 3:54 PM, Michal Wajdeczko wrote:
On Fri, 22 Sep 2017 12:07:47 +0200, Sagar Arun Kamble
wrote:
With GuC v9, new type of Default/critical logging in GuC to enable
capturing minimal important logs in production systems efficiently.
This patch enables this logging in GuC by default
We should not add trailing ; after each member allow other
than statements-style uses of this helper macro.
While here s/func/param for clarity.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Jani Nikula
---
drivers/gpu/drm/i915/i915_params.h | 84 +++---
Members should be initialized with values of matching types.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Jani Nikula
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_params.h | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915
By combining default value into helper macro we can initialize
modparams struct in the same automatic way as it was declared.
This will initialize members in the same order as declared
and additionally will disallow declaring new member without
proper default value for it.
Signed-off-by: Michal Wa
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Make own struct for execlist
items
URL : https://patchwork.freedesktop.org/series/30761/
State : warning
== Summary ==
Series 30761v1 series starting with [CI,1/5] drm/i915: Make own struct for
execlist items
https://patchw
== Series Details ==
Series: igt/kms_psr_sink_crc: Fix the bug in psr_drrs subtest
URL : https://patchwork.freedesktop.org/series/30727/
State : success
== Summary ==
Test gem_eio:
Subgroup in-flight-contexts:
dmesg-warn -> PASS (shard-hsw) fdo#102886 +3
Test prim
On Fri, Sep 22, 2017 at 6:31 AM Rodrigo Vivi wrote:
> On Thu, Sep 21, 2017 at 11:19:49PM +, Oscar Mateo wrote:
> > The total size of the context has decreased with the removal of the
> > URB_ATOMIC section. BSpec indicates 16750 DWORDs (17 pages), plus
> > one page for PPHWSP, and I'm throwin
Like wide(), reorder-wide() didn't check the ring size before flooding
and so would exhaust its available space and block (causing a GPU hang
to recover), thus failing the test. Also, since we use a new context for
each iteration of the test, the available ring space is reduced (due to
the overhead
== Series Details ==
Series: GuC Fixes, HuC auth. reorg and v9+ logging change (rev2)
URL : https://patchwork.freedesktop.org/series/30715/
State : warning
== Summary ==
Test perf:
Subgroup blocking:
fail -> PASS (shard-hsw) fdo#102252
Test kms_flip:
On Thu, Sep 21, 2017 at 11:19:49PM +, Oscar Mateo wrote:
> The total size of the context has decreased with the removal of the
> URB_ATOMIC section. BSpec indicates 16750 DWORDs (17 pages), plus
> one page for PPHWSP, and I'm throwing an extra page for precaution.
I could never find this info
On Tue, Sep 19, 2017 at 02:50:03PM +0530, Vidya Srinivas wrote:
> From: Uma Shankar
>
> For certain platforms on certain encoders, timings are driven
> from port instead of pipe. Thus, we can't rely on pipe scanline
> registers to get the timing information. Some cases scanline
> register read ma
== Series Details ==
Series: drm/i915: Make i915_spin_request() static
URL : https://patchwork.freedesktop.org/series/30757/
State : success
== Summary ==
Series 30757v1 drm/i915: Make i915_spin_request() static
https://patchwork.freedesktop.org/api/1.0/series/30757/revisions/1/mbox/
Test kms
CNL adds an extra register for slice/subslice information.
Although no SKU is planed with an extra slice let's already
handle this extra piece of information so we don't have the
risk in future of getting a part that might have chosen this
part of the die instead of other slices or anything like th
As we emulate execlists on top of the GuC workqueue, it is not
restricted to just 2 ports and we can increase that number arbitrarily
to trade-off queue depth (i.e. scheduling latency) against pipeline
bubbles.
v2: rebase. better commit msg (Chris)
v3: rebase
Signed-off-by: Mika Kuoppala
Reviewe
When first execlist entry is processed, we move the port (contents).
Introduce function for this as execlist and guc use this common
operation.
v2: rebase. s/GEM_DEBUG_BUG/GEM_BUG (Chris)
v3: rebase
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_guc_submis
On reset and wedged path, we want to release the requests
that are tied to ports and then mark the ports to be unset.
Introduce a function for this.
v2: rebase
v3: drop local, keep GEM_BUG_ON (Michał, Chris)
v4: rebase
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
Reviewed-by: Michał Winiarski
Move execlist init into a common engine setup. As it is
common to both guc and hw execlists.
v2: rebase with csb changes
v3: rebase
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_engine_cs.c | 30 --
drivers/gpu/drm/i915/intel_
== Series Details ==
Series: drm/i915/bios: ignore HDMI on port A (rev2)
URL : https://patchwork.freedesktop.org/series/30700/
State : success
== Summary ==
Test drv_module_reload:
Subgroup basic-no-display:
dmesg-warn -> PASS (shard-hsw) fdo#102707
fdo#102707 ht
On Fri, Sep 22, 2017 at 11:23:34AM +, Jani Nikula wrote:
> On Fri, 22 Sep 2017, Jani Nikula wrote:
> > On Fri, 22 Sep 2017, Rodrigo Vivi wrote:
> >> On Thu, Sep 21, 2017 at 10:03:48PM +, Anuj Phogat wrote:
> >>> On Thu, Sep 21, 2017 at 2:58 PM, Rodrigo Vivi
> >>> wrote:
> >>> > In sync
Engine's execlist related items have been increasing to
a point where a separate struct is warranted. Carve execlist
specific items to a dedicated struct to add clarity.
v2: add kerneldoc and fix whitespace (Joonas, Chris)
v3: csb_mmio changes, rebase
v4: s/\b(el|execlist)\b/execlists/ (Joonas)
S
== Series Details ==
Series: drm/i915/cnl: Add Gen10 LRC size
URL : https://patchwork.freedesktop.org/series/30724/
State : success
== Summary ==
Test perf:
Subgroup polling:
fail -> PASS (shard-hsw) fdo#102252
fdo#102252 https://bugs.freedesktop.org/show_b
It seems that at least with GLK with MIPI/DSI display, the first collected
CRC is bogus. To fix this, try to collect two CRC's instead of one.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101309
Signed-off-by: Mika Kahola
---
tests/kms_frontbuffer_tracking.c | 12 +++-
1 file c
On Fri, Sep 22, 2017 at 03:05:44PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 22, 2017 at 12:52:59PM +0300, Petri Latvala wrote:
> > On Thu, Sep 21, 2017 at 05:39:30PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Raw usage of cairo_image_surface_create_from_png() doesn't work
On Thu, 21 Sep 2017, Michal Wajdeczko wrote:
> If there is an agreement on merging first patch, can someone give it
> r-b and merge ? Note that this patch is prone to rebase conflicts.
Pushed the first patch, thanks.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
__
== Series Details ==
Series: igt/kms_psr_sink_crc: Fix the bug in psr_drrs subtest
URL : https://patchwork.freedesktop.org/series/30727/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
3a01e58858e6068f75356e798fd90c80cccb37d6 tests/gem_flink_basic: Add
docu
On Fri, 2017-09-22 at 13:03 +0100, Chris Wilson wrote:
> No users now outside of i915_wait_request(), so we can make it private to
> i915_gem_request.c, and assume the caller knows the seqno. In the
> process, also remove i915_gem_request_started() as that was only ever
> used by i915_spin_request(
On Fri, Sep 22, 2017 at 12:52:59PM +0300, Petri Latvala wrote:
> On Thu, Sep 21, 2017 at 05:39:30PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Raw usage of cairo_image_surface_create_from_png() doesn't work
> > since it doesn't know about IGT_DATADIR and IGT_SRCDIR. Let's extract
On Wed, 20 Sep 2017, Daniel Drake wrote:
> We are looking at a geminilake board and i915 is trying to load
> glk_dmc_ver1_04.bin. It looks like there isn't any glk firmware in
> linux-firmware, would now be a good time to add it?
Fail. We're working on resolving this.
> ( not sure if it's relate
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