== Series Details ==
Series: Collect command stream based OA reports using i915 perf
URL : https://patchwork.freedesktop.org/series/21351/
State : success
== Summary ==
Series 21351v1 Collect command stream based OA reports using i915 perf
https://patchwork.freedesktop.org/api/1.0/series/21351
From: Sourab Gupta
Currently, we have the ability to only forward the GPU timestamps in the
samples (which are generated via OA reports or PIPE_CONTROL commands
inserted in the ring). This limits the ability to correlate these samples
with the system events. If we scale the GPU timestamps accordi
From: Sourab Gupta
This patch adds support for capturing MMIO register values through
i915 perf interface.
The userspace can request upto 8 MMIO register values to be dumped.
The addresses of these registers can be passed through the corresponding
property 'value' field while opening the stream.
From: Sourab Gupta
For the drivers to be able to use the cross timestamp framework,
they need the information of current clocksource being used by the
kernel timekeeping. This is needed since the callback given by driver
into the get_device_system_crosststamp(), in order to synchronously read
the
From: Sourab Gupta
This patch adds support for opening multiple concurrent perf streams for
different gpu engines, while having the restriction to open only a single
stream open for a particular gpu engine.
This enables userspace client to open multiple streams, one per engine,
at any time to cap
From: Sourab Gupta
The OA reports contain the least significant 32 bits of the gpu timestamp.
This patch enables retrieval of the timestamp field from OA reports, to
forward as 64 bit raw gpu timestamps in the perf samples.
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/i915_drv.h | 1
From: Sourab Gupta
This patch extends the i915 perf framework to handle the perf sample
collection for any given gpu engine. Particularly, the support
for collecting timestamp sample type is added, which can be requested for
any engine.
With this, for RCS, timestamps and OA reports can be collec
From: Sourab Gupta
This series adds framework for collection of gpu performance metrics
associated with the command stream of a particular engine. These metrics
include OA reports for render stream and timestamps, mmio metrics, etc. for
other gpu engine streams. These metrics are are collected ar
From: Sourab Gupta
This adds support for populating the ctx id for the periodic OA reports
when requested through the corresponding property.
For Gen8, the OA reports itself have the ctx ID and it is the one programmed
into HW while submitting workloads. Thus it's retrieved from reports itself.
From: Sourab Gupta
This patch introduces a framework to capture OA counter reports associated
with Render command stream. We can then associate the reports captured
through this mechanism with their corresponding context id's. This can be
further extended to associate any other metadata informati
From: Sourab Gupta
Considering how we don't currently give userspace control over the
OA buffer size and always configure a large 16MB buffer,
then a buffer overflow does anyway likely indicate that something
has gone quite badly wrong.
Here we set a status flag to detect overflow and inform use
From: Sourab Gupta
This patch exposes a new sample source field to userspace. This field can
be populated to specify the origin of the OA report.
Currently, the OA samples are being generated only periodically, and hence
there's only source flag enum definition right now, but there are other
mean
From: Sourab Gupta
When there are no pending CS OA samples, flush the periodic OA samples
collected so far.
We can safely forward the periodic OA samples in the case we
have no pending CS samples, but we can't do so in the case we have
pending CS samples, since we don't know what the ordering be
From: Sourab Gupta
This patch introduces flags and adds support for having pid output with
the OA reports generated through the RCS commands.
When the stream is opened with pid sample type, the pid information is also
captured through the command stream samples and forwarded along with the
OA re
From: Sourab Gupta
This patch enables userspace to specify tags (per workload), provided via
execbuffer ioctl, which could be added to OA reports, to help associate
reports with the corresponding workloads.
There may be multiple stages within a single context, from a userspace
perspective. An ab
From: Sourab Gupta
This patch adds a new ctx getparam ioctl parameter, which can be used to
retrieve ctx unique id by userspace.
This can be used by userspace to map the OA reports received in the
i915 perf samples with their associated ctx's (The OA reports have the
hw ctx ID information embedd
From: Sourab Gupta
This series adds framework for collection of OA reports associated with the
render command stream, which are collected around batchbuffer boundaries.
Refloating the series rebased on Robert's latest patch set for
'Enabling OA unit for Gen 8 and 9 in i915 perf', which can be fo
== Series Details ==
Series: Enchancement to intel_dp_aux_backlight driver
URL : https://patchwork.freedesktop.org/series/21327/
State : success
== Summary ==
Series 21327v1 Enchancement to intel_dp_aux_backlight driver
https://patchwork.freedesktop.org/api/1.0/series/21327/revisions/1/mbox/
intel_dp_aux_enable_backlight() assumed that the register
BACKLIGHT_BRIGHTNESS_CONTROL_MODE can only has value 01
(DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET) when initialize.
This patch fixed that by handling all cases of that register.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/
From: Puthikorn Voravootivat
This patch set contain 6 patches.
- First two patches allow enable DPCD backlight control when panel
can also do that via PWM pin and fix the usage of enable register.
- Next patch adds enable DBC by default
- Next patch makes the driver restore last brightness leve
Currently the intel_dp_aux_backlight driver requires eDP panel
to not also support backlight adjustment via PWM pin to use
this driver.
This force the eDP panel that support both ways of backlight
adjustment to do it via PWM pin.
This patch adds the new prefer DPCD mode in the i915_param
to make
This patch adds the following definition
- Bit mask for EDP_PWMGEN_BIT_COUNT and min/max cap
register which only use bit 0:4
- Base frequency (27 MHz) for backlight PWM frequency
generator.
Signed-off-by: Puthikorn Voravootivat
---
include/drm/drm_dp_helper.h | 2 ++
1 file changed, 2 insert
This patch enables dynamic backlight by default for eDP
panel that supports this feature via DPCD register and
set minimum / maximum brightness to 0% and 100% of the
normal brightness.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 31 ++
From: Puthikorn Voravootivat
This patch set contain 6 patches.
- First two patches allow enable DPCD backlight control when panel
can also do that via PWM pin and fix the usage of enable register.
- Next patch adds enable DBC by default
- Next patch makes the driver restore last brightness leve
Read desired PWM frequency from panel vbt and calculate the
value for divider in DPCD address 0x724 and 0x728 to match
that frequency as close as possible.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 54 +++
1 file changed, 54
Some panel will default to zero brightness when turning the
panel off and on again. This patch stores last brightness level
before turning off and set them back when panel is turning on.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 2 ++
1 file change
Am Dienstag, den 14.03.2017, 13:19 +0200 schrieb Jani Nikula:
>
> That would be
>
> commit f2a0409a08502d64fbe3990354dff5902b08d2fb
> Author: Chris Wilson
> Date: Wed Sep 21 14:51:08 2016 +0100
>
> drm/i915/execlists: Reset RING registers upon resume
>
> commit bafb2f7d4755bf1571
== Series Details ==
Series: drm/i915/breadcrumbs: Tweak commentary
URL : https://patchwork.freedesktop.org/series/21324/
State : success
== Summary ==
Series 21324v1 drm/i915/breadcrumbs: Tweak commentary
https://patchwork.freedesktop.org/api/1.0/series/21324/revisions/1/mbox/
Test gem_exec_
Tvrtko spotted a stale reference to b->lock (now b->rb_lock) so review
the comments and try to improve them in passing.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 25 +
1 file changed, 17 insertions(+)
On Wed, Mar 15, 2017 at 09:38:58PM -, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [CI,1/5] drm/i915/breadcrumbs: Use booleans for
> intel_breadcrumbs_busy()
> URL : https://patchwork.freedesktop.org/series/21320/
> State : success
>
> == Summary ==
>
> Series
On Wed, Mar 15, 2017 at 11:06:32PM +0200, Ville Syrjälä wrote:
> > @@ -1608,6 +1619,21 @@ int drm_wait_vblank(struct drm_device *dev, void
> > *data,
> >
> > vblank = &dev->vblank[pipe];
> >
> > + /* If the counter is currently enabled and accurate, short-circuit
> > queries
> > +*
== Series Details ==
Series: series starting with [CI,1/5] drm/i915/breadcrumbs: Use booleans for
intel_breadcrumbs_busy()
URL : https://patchwork.freedesktop.org/series/21320/
State : success
== Summary ==
Series 21320v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/s
== Series Details ==
Series: series starting with [1/3] drm: Defer disabling the vblank IRQ until
the next interrupt (for instant-off)
URL : https://patchwork.freedesktop.org/series/21318/
State : success
== Summary ==
Series 21318v1 Series without cover letter
https://patchwork.freedesktop.o
Em Qua, 2017-02-15 às 20:18 +0530, Mahesh Kumar escreveu:
> This patch adds support to decode system memory bandwidth
> which will be used for arbitrated display memory percentage
> calculation in GEN9 based system.
>
> Changes from v1:
> - Address comments from Paulo
> - implement decode functi
We need to ensure that we always serialize updates to the bottom-half
using the breadcrumbs.irq_lock so that we don't race with a concurrent
interrupt handler. This is most important just prior to leaving the
waiter (when the intel_wait will be overwritten), so make sure we are
not the current bott
Check that request has not been signaled before acquiring a reference to
the request for signaling later in the interrupt handler.
The loading of the cacheline (for request->fence.flags) should be "free"
when followed by the locked increment of the request->fence.refcount
(which then sets the cach
Since commit 9b6586ae9f6b ("drm/i915: Keep a global seqno per-engine")
converted intel_breadcrumbs_busy() to reporting a single boolean, we
need only compute a boolean internally (and not needlessly compute the
flag).
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Reviewed-by:
When adding a new request to the breadcrumb rbtree, we mark all those
requests inside the rbtree that are already completed as complete. This
wakes those waiters up and allows them to skip the spinlock before
returning to userspace. If one of those is the current bottom-half and
allocated its intel
Before walking the rbtree of waiters (marking them as complete and waking
them), decouple the interrupt handler. This prevents a race between the
missed waiter waking up and removing its intel_wait (which skips
checking the lock) and the interrupt handler dereferencing the
intel_wait. (Though we do
On Wed, Mar 15, 2017 at 08:40:27PM +, Chris Wilson wrote:
> Bypass all the spinlocks and return the last timestamp and counter from
> the last vblank if the driver delcares that it is accurate (and stable
> across on/off), and the vblank is currently enabled.
>
> This is dependent upon the bot
On Wed, Mar 15, 2017 at 08:40:25PM +, Chris Wilson wrote:
> On vblank instant-off systems, we can get into a situation where the cost
> of enabling and disabling the vblank IRQ around a drmWaitVblank query
> dominates. And with the advent of even deeper hardware sleep state,
> touching register
== Series Details ==
Series: series starting with [CI,1/5] drm/i915/breadcrumbs: Use booleans for
intel_breadcrumbs_busy()
URL : https://patchwork.freedesktop.org/series/21317/
State : failure
== Summary ==
Series 21317v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/s
On Wed, Mar 15, 2017 at 08:38:07PM +, Chris Wilson wrote:
> When adding a new request to the breadcrumb rbtree, we mark all those
> requests inside the rbtree that are already completed as complete. This
> wakes those waiters up and allows them to skip the spinlock before
> returning to userspa
On vblank instant-off systems, we can get into a situation where the cost
of enabling and disabling the vblank IRQ around a drmWaitVblank query
dominates. And with the advent of even deeper hardware sleep state,
touching registers becomes ever more expensive. However, we know that if
the user want
Avoid adding to the waitqueue and reprobing the current vblank if the
caller is only querying the current vblank sequence and timestamp, where
we know that the wait would return immediately.
v2: Add CRTC identifier to debug messages
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Daniel Vette
Bypass all the spinlocks and return the last timestamp and counter from
the last vblank if the driver delcares that it is accurate (and stable
across on/off), and the vblank is currently enabled.
This is dependent upon the both the hardware and driver to provide the
proper barriers to facilitate r
Acked-by: Lyude
On Mon, 2017-03-13 at 17:02 +, Chris Wilson wrote:
> In order to prevent accessing the hpd registers outside of the
> display
> power wells, we should refrain from writing to the registers before
> the
> display interrupts are enabled.
>
> [4.740136] WARNING: CPU: 1 PID:
When adding a new request to the breadcrumb rbtree, we mark all those
requests inside the rbtree that are already completed as complete. This
wakes those waiters up and allows them to skip the spinlock before
returning to userspace. If one of those is the current bottom-half and
allocated its intel
Check that request has not been signaled before acquiring a reference to
the request for signaling later in the interrupt handler.
The loading of the cacheline (for request->fence.flags) should be "free"
when followed by the locked increment of the request->fence.refcount
(which then sets the cach
Before walking the rbtree of waiters (marking them as complete and waking
them), decouple the interrupt handler. This prevents a race between the
missed waiter waking up and removing its intel_wait (which skips
checking the lock) and the interrupt handler dereferencing the
intel_wait. (Though we do
We need to ensure that we always serialize updates to the bottom-half
using the breadcrumbs.irq_lock so that we don't race with a concurrent
interrupt handler. This is most important just prior to leaving the
waiter (when the intel_wait will be overwritten), so make sure we are
not the current bott
Since commit 9b6586ae9f6b ("drm/i915: Keep a global seqno per-engine")
converted intel_breadcrumbs_busy() to reporting a single boolean, we
need only compute a boolean internally (and not needlessly compute the
flag).
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Reviewed-by:
Em Qua, 2017-02-01 às 12:14 +0530, Mahesh Kumar escreveu:
> Hi,
>
>
> On Tuesday 31 January 2017 09:26 PM, Ander Conselvan De Oliveira
> wrote:
> >
> > On Tue, 2017-01-31 at 20:27 +0530, Mahesh Kumar wrote:
> > >
> > > This patch adds IPC support for platforms. This patch enables IPC
> > > only
On 15/03/2017 20:05, Chris Wilson wrote:
On Wed, Mar 15, 2017 at 07:47:20PM +, Tvrtko Ursulin wrote:
On 15/03/2017 14:01, Chris Wilson wrote:
Check that signaled bit on the request->fence before acquiring a
"is not set" ^
Or "Check that the request has not been signalled be
On Wed, Mar 15, 2017 at 07:47:20PM +, Tvrtko Ursulin wrote:
>
> On 15/03/2017 14:01, Chris Wilson wrote:
> >Check that signaled bit on the request->fence before acquiring a
>
> "is not set" ^
>
> Or "Check that the request has not been signalled before.." ?
>
> >reference to the
== Series Details ==
Series: drm/i915/uc: Make intel_uc_prepare_fw() static
URL : https://patchwork.freedesktop.org/series/21315/
State : success
== Summary ==
Series 21315v1 drm/i915/uc: Make intel_uc_prepare_fw() static
https://patchwork.freedesktop.org/api/1.0/series/21315/revisions/1/mbox/
On 15/03/2017 14:01, Chris Wilson wrote:
Check that signaled bit on the request->fence before acquiring a
"is not set" ^
Or "Check that the request has not been signalled before.." ?
reference to the request for signaling later in the interrupt handler.
Signed-off-by: Chris Wil
On 15/03/2017 14:01, Chris Wilson wrote:
We need to ensure that we always serialize updates to the bottom-half
using the breadcrumbs.irq_lock so that we don't race with a concurrent
interrupt handler. This is most important just prior to leaving the
waiter (when the intel_wait will be overwritte
There is no need to expose this function as it is called from
one function only. Also move it up to avoid forward declaration.
Signed-off-by: Michal Wajdeczko
Cc: Arkadiusz Hiler
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_uc.c | 269
drivers/gpu
On 15/03/2017 14:01, Chris Wilson wrote:
Before walking the rbtree of waiters (marking them as complete and waking
them), decouple the interrupt handler. This prevents a race between the
missed waiter waking up and removing its intel_wait (which skips
checking the lock) and the interrupt handler
On Wed, Mar 15, 2017 at 03:39:58PM -0300, Paulo Zanoni wrote:
> Em Qua, 2017-03-15 às 20:16 +0200, Ville Syrjälä escreveu:
> > On Wed, Mar 15, 2017 at 06:03:58PM +, Pandiyan, Dhinakaran wrote:
> > >
> > > On Wed, 2017-03-15 at 11:32 +0200, Jani Nikula wrote:
> > > >
> > > > On Tue, 14 Mar 201
On 15/03/2017 19:10, Chris Wilson wrote:
On Wed, Mar 15, 2017 at 06:58:27PM +, Tvrtko Ursulin wrote:
On 15/03/2017 14:01, Chris Wilson wrote:
When adding a new request to the breadcrumb rbtree, we mark all those
requests inside the rbtree that are already completed as complete. This
wakes
On Wed, Mar 15, 2017 at 06:58:27PM +, Tvrtko Ursulin wrote:
>
> On 15/03/2017 14:01, Chris Wilson wrote:
> >When adding a new request to the breadcrumb rbtree, we mark all those
> >requests inside the rbtree that are already completed as complete. This
> >wakes those waiters up and allows them
On 15/03/2017 18:32, Chris Wilson wrote:
On Wed, Mar 15, 2017 at 06:20:16PM +, Tvrtko Ursulin wrote:
On 15/03/2017 14:01, Chris Wilson wrote:
Check that we have disabled irqs before we take the spin_lock around
reassigned the breadcrumbs.irq_wait.
Signed-off-by: Chris Wilson
Cc: Tvrtko
On 15/03/2017 14:01, Chris Wilson wrote:
When adding a new request to the breadcrumb rbtree, we mark all those
requests inside the rbtree that are already completed as complete. This
wakes those waiters up and allows them to skip the spinlock before
returning to userspace. If one of those is the
Em Qua, 2017-03-15 às 20:16 +0200, Ville Syrjälä escreveu:
> On Wed, Mar 15, 2017 at 06:03:58PM +, Pandiyan, Dhinakaran wrote:
> >
> > On Wed, 2017-03-15 at 11:32 +0200, Jani Nikula wrote:
> > >
> > > On Tue, 14 Mar 2017, "Pandiyan, Dhinakaran" > > intel.com> wrote:
> > > >
> > > > On Tue,
On Wed, Mar 15, 2017 at 06:20:16PM +, Tvrtko Ursulin wrote:
>
> On 15/03/2017 14:01, Chris Wilson wrote:
> >Check that we have disabled irqs before we take the spin_lock around
> >reassigned the breadcrumbs.irq_wait.
> >
> >Signed-off-by: Chris Wilson
> >Cc: Tvrtko Ursulin
> >---
> > drivers
On 15/03/2017 14:01, Chris Wilson wrote:
Check that we have disabled irqs before we take the spin_lock around
reassigned the breadcrumbs.irq_wait.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 7 ++-
1 file changed, 6 insertions(+), 1 delet
On Wed, Mar 15, 2017 at 06:03:58PM +, Pandiyan, Dhinakaran wrote:
> On Wed, 2017-03-15 at 11:32 +0200, Jani Nikula wrote:
> > On Tue, 14 Mar 2017, "Pandiyan, Dhinakaran"
> > wrote:
> > > On Tue, 2017-03-14 at 17:47 -0300, Paulo Zanoni wrote:
> > >> Em Ter, 2017-03-07 às 16:12 -0800, Dhinakara
== Series Details ==
Series: drm/i915/gvt: Use offsetofend() rather than offsetof + sizeof
URL : https://patchwork.freedesktop.org/series/21309/
State : success
== Summary ==
Series 21309v1 drm/i915/gvt: Use offsetofend() rather than offsetof + sizeof
https://patchwork.freedesktop.org/api/1.0/
On Wed, 2017-03-15 at 11:32 +0200, Jani Nikula wrote:
> On Tue, 14 Mar 2017, "Pandiyan, Dhinakaran"
> wrote:
> > On Tue, 2017-03-14 at 17:47 -0300, Paulo Zanoni wrote:
> >> Em Ter, 2017-03-07 às 16:12 -0800, Dhinakaran Pandiyan escreveu:
> >> > According to BSpec, "The CD clock frequency must be
On 15/03/2017 14:01, Chris Wilson wrote:
Since commit 9b6586ae9f6b ("drm/i915: Keep a global seqno per-engine")
converted intel_breadcrumbs_busy() to reporting a single boolean, we
need only compute a boolean internally (and not needlessly compute the
flag).
Signed-off-by: Chris Wilson
Cc: Mik
== Series Details ==
Series: series starting with [1/6] drm/i915: Move residency calculation into
intel_pm.c (rev3)
URL : https://patchwork.freedesktop.org/series/21303/
State : success
== Summary ==
Series 21303v3 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/2
Compute the offset of the end of the crc32 field using offsetofend()
rather than open-coding.
Signed-off-by: Chris Wilson
Cc: Zhenyu Wang
Cc: Zhi Wang
---
drivers/gpu/drm/i915/gvt/firmware.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/firmware.c
== Series Details ==
Series: drm/i915: Enable atomic for VLV/CHV
URL : https://patchwork.freedesktop.org/series/20634/
State : failure
== Summary ==
Series 20634v1 drm/i915: Enable atomic for VLV/CHV
https://patchwork.freedesktop.org/api/1.0/series/20634/revisions/1/mbox/
Test gem_exec_flush:
Set byt rc residency counters high level as chv does by
default. We lose some accuracy on byt but we can do the calculation
without extra hw read on both platforms, as now they behave
identically in this respect.
v2: use ktime
v3: keep comparison u32 (Chris)
Cc: Chris Wilson
Cc: Ville Syrjälä
S
Depending on what version of drm_i915.h you have, you may not have
this #define but it's required in order to properly dump aubs from
newer versions of mesa.
---
I have no idea what the back-porting procedure is for IGT. If someone
could provide me with a tagline to ensure it lands in stable, tha
Vlv and chv residency counters are 40 bits in width.
With a control bit, we can choose between upper or lower
32 bit window into this counter.
Lets toggle this bit on and off on and read both parts.
As a result we can push the wrap from 13 seconds to 54
minutes.
v2: commit msg, loop readability,
On Wed, Mar 15, 2017 at 05:42:59PM +0200, Mika Kuoppala wrote:
> Plan is to make generic residency calculation utility
> function for usage outside of sysfs. As a first step
> move residency calculation into intel_pm.c
>
> Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
-Chris
--
Chris
On Wed, Mar 15, 2017 at 05:43:00PM +0200, Mika Kuoppala wrote:
> Change the granularity from milliseconds to microseconds
> when returning rc6 residencies. This is in preparation
> for increased resolution on some platforms.
>
> v2: use 64bit div macro (Chris)
>
> Cc: Chris Wilson
> Signed-off-b
On Wed, Mar 15, 2017 at 05:43:03PM +0200, Mika Kuoppala wrote:
> We have used cz timestamp register to gain a reference time wrt
> to residency calculations. The residency counts are in cz clk ticks
> (333Mhz clock) but for some reason the cz timestamp register gives
> 100us units. Perhaps for some
On Wed, Mar 15, 2017 at 05:43:04PM +0200, Mika Kuoppala wrote:
> Set byt rc residency counters high level as chv does by
> default. We lose some accuracy on byt but we can do the calculation
> without extra hw read on both platforms, as now they behave
> identically in this respect.
>
> v2: use kt
On Wed, Mar 15, 2017 at 05:43:02PM +0200, Mika Kuoppala wrote:
> Use intel_rc6_residency to get benefit for increased resolution
> in byt/chv.
>
> v2: output raw and time (Chris)
>
> Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
-Chris
--
Chris Wilson, Intel Open Source Technology Ce
On Wed, Mar 15, 2017 at 05:43:01PM +0200, Mika Kuoppala wrote:
> Vlv and chv residency counters are 40 bits in width.
> With a control bit, we can choose between upper or lower
> 32 bit window into this counter.
>
> Lets toggle this bit on and off on and read both parts.
> As a result we can push
On Wed, Mar 15, 2017 at 12:46:57PM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/guc: Use formalized struct definition for ads object (rev5)
> URL : https://patchwork.freedesktop.org/series/20826/
> State : success
>
> == Summary ==
>
> Series 20826v5 drm/i915/guc: Use fo
On Tue, Mar 14, 2017 at 10:24:42AM -0700, Michel Thierry wrote:
>
>
> On 3/14/2017 10:18 AM, Chris Wilson wrote:
> >We take the runtime pm wakelock during i915_handle_error() to ensure
> >that all paths that reach the error capture keep the device awake during
> >the hw reads. However, we need to
Vlv and chv residency counters are 40 bits in width.
With a control bit, we can choose between upper or lower
32 bit window into this counter.
Lets toggle this bit on and off on and read both parts.
As a result we can push the wrap from 13 seconds to 54
minutes.
v2: commit msg, loop readability,
Set byt rc residency counters high level as chv does by
default. We lose some accuracy on byt but we can do the calculation
without extra hw read on both platforms, as now they behave
identically in this respect.
v2: use ktime
Cc: Chris Wilson
Cc: Ville Syrjälä
Signed-off-by: Mika Kuoppala
---
Plan is to make generic residency calculation utility
function for usage outside of sysfs. As a first step
move residency calculation into intel_pm.c
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_sysfs.c | 27 +--
dr
We have used cz timestamp register to gain a reference time wrt
to residency calculations. The residency counts are in cz clk ticks
(333Mhz clock) but for some reason the cz timestamp register gives
100us units. Perhaps for some other usage, the base-ten based values
are easier, but in residency ca
Change the granularity from milliseconds to microseconds
when returning rc6 residencies. This is in preparation
for increased resolution on some platforms.
v2: use 64bit div macro (Chris)
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu
Use intel_rc6_residency to get benefit for increased resolution
in byt/chv.
v2: output raw and time (Chris)
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c | 30 ++
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i
== Series Details ==
Series: drm/i915/userptr: Reinvent GGTT self-faulting protection
URL : https://patchwork.freedesktop.org/series/21291/
State : warning
== Summary ==
Series 21291v1 drm/i915/userptr: Reinvent GGTT self-faulting protection
https://patchwork.freedesktop.org/api/1.0/series/212
On Wed, Mar 15, 2017 at 05:09:04PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Add a command for extracting various tags (eg. Reviwed-by:) from
> emails. You can give the comamnd a rangeish to add the tags from
> the same email to multiple already applied patches.
>
> T
== Series Details ==
Series: series starting with [1/4] drm/i915: Split I915_RESET_IN_PROGRESS into
two flags
URL : https://patchwork.freedesktop.org/series/21290/
State : warning
== Summary ==
Series 21290v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/21290/r
From: Ville Syrjälä
Add the "add-link" command so that you can add the Link: tag to
patches that failed to apply directly.
v2: Drop the aliases
Remove the temp file
Clean up locals
Use echoerr for error prints
Cc: Jani Nikula
Signed-off-by: Ville Syrjälä
---
dim | 39
From: Ville Syrjälä
Add a command for extracting various tags (eg. Reviwed-by:) from
emails. You can give the comamnd a rangeish to add the tags from
the same email to multiple already applied patches.
The regexp used to pick up tags is purposefully quite broad. People
tend to typo these things,
== Series Details ==
Series: series starting with [1/6] drm/i915/breadcrumbs: Use booleans for
intel_breadcrumbs_busy()
URL : https://patchwork.freedesktop.org/series/21289/
State : success
== Summary ==
Series 21289v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/seri
== Series Details ==
Series: drm/i915: Make intel_uc_sanitize_options() more robust
URL : https://patchwork.freedesktop.org/series/21286/
State : success
== Summary ==
Series 21286v1 drm/i915: Make intel_uc_sanitize_options() more robust
https://patchwork.freedesktop.org/api/1.0/series/21286/r
From: Ville Syrjälä
Currently ILK-BDW explicitly disable LP1+ watermarks from their
.init_clock_gating() hooks. Unfortunately that hook gets called way too
late since by that time we've already initialized all the watermark
state tracking which then gets out of sync with the hardware state.
We m
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