Re: [Intel-gfx] [PATCH v2 4/5] i2c: designware-baytrail: Force the CPU to C1 state while holding the punit semaphore

Hi, On 26-12-16 12:07, Hans de Goede wrote: Hi, On 25-12-16 19:31, Len Brown wrote: Is there a simple way to run a test to keep deep C-states and instead disable part or all of i2c on this platform, to see how much stability separating the two will buy us? This should do the trick to complet

Re: [Intel-gfx] [Mesa-dev] [PATCH 00/27] Renderbuffer Decompression (and GBM modifiers)

On 16-12-29 17:34:19, Ben Widawsky wrote: On 16-12-06 13:34:02, Paulo Zanoni wrote: 2016-12-01 20:09 GMT-02:00 Ben Widawsky : From: Ben Widawsky This patch series ultimately adds support within the i965 driver for Renderbuffer Decompression with GBM. In short, this feature reduces memory band

Re: [Intel-gfx] [PATCH] drm/i915: Fix not finding the VBT when it overlaps with OPREGION_ASLE_EXT

Hi, On 27-12-16 11:58, Jani Nikula wrote: On Sun, 25 Dec 2016, Hans de Goede wrote: If there is no OPREGION_ASLE_EXT then a VBT stored in mailbox #4 may use the ASLE_EXT parts of the opregion. Adjust the vbt_size calculation for a vbt in mailbox #4 for this. This fixes the driver not finding

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/26] drm/i915: Assert that we do create the deferred context

On Sat, Dec 31, 2016 at 01:23:42PM -, Patchwork wrote: > == Series Details == > > Series: series starting with [01/26] drm/i915: Assert that we do create the > deferred context > URL : https://patchwork.freedesktop.org/series/17337/ > State : failure > > == Summary == > > Series 17337v1 S

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/26] drm/i915: Assert that we do create the deferred context

== Series Details == Series: series starting with [01/26] drm/i915: Assert that we do create the deferred context URL : https://patchwork.freedesktop.org/series/17337/ State : failure == Summary == Series 17337v1 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/173

[Intel-gfx] [PATCH 23/26] drm/i915: Construct a request even if the GPU is currently hung

As we now have the ability to directly reset the GPU from the waiter (and so do not need to drop the lock in order to let the reset proceed) and also do not lose requests over a reset, we can now simply queue the request to occur after the reset rather than roundtripping to userspace (or worse fail

[Intel-gfx] [PATCH 01/26] drm/i915: Assert that we do create the deferred context

In order to convince static analyzers that the allocation function returns an error or sets ce->state, assert that it is set afterwards. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_lrc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers

[Intel-gfx] [PATCH 19/26] drm/i915: Store required fence size/alignment for GGTT vma

Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.h | 7 ++-- drivers/gpu/drm/i915/i915_gem.c | 27 +-- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 16 - drivers/gpu/drm/i915/i915_gem_tiling.c| 40 +++--- drivers/gpu/drm/i91

[Intel-gfx] [PATCH 13/26] drm/i915: Eliminate superfluous i915_ggtt_view_rotated

It is only being used to clear a struct and set the type, after which it is overwritten. Since we no longer check the unset bits of the union, skipping the clear is permissible. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem_gtt.c | 3 --- drivers/gp

[Intel-gfx] [PATCH 10/26] drm/i915: Name the anonymous structs inside i915_ggtt_view

Naming this pair will become useful later... Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_gtt.h | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 9e91d7e6149c..19ea4c9

[Intel-gfx] [PATCH 22/26] drm/i915: Split out i915_gem_object_set_tiling()

Expose an interface for changing the tiling and stride on an object, that includes the complexity of checking for conflicting bindings and fence registers. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_object.h | 3 + drivers/gpu/drm/i915/i915_gem_tiling.c | 238 +++

[Intel-gfx] [PATCH 21/26] drm/i915: Include ioctl in set-tiling and get-tiling function names

Make it clear that these functions are the user entry points for the tiling/fence registers. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.c| 4 ++-- drivers/gpu/drm/i915/i915_drv.h| 8 drivers/gpu/drm/i915/i915_gem_tiling.c | 16 3 fil

[Intel-gfx] [PATCH 04/26] drm/i915: Use range_overflows()

Replace a few more open-coded overflow checks with the macro. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +- drivers/gpu/drm/i915/i915_vma.c| 3 ++- drivers/gpu/drm/i915/intel_bios.c | 7 +-- 3 files changed, 8 insertions(+), 4 deletions(-) diff

[Intel-gfx] [PATCH 14/26] drm/i915: Eliminate superfluous i915_ggtt_view_normal

Since commit 058d88c4330f ("drm/i915: Track pinned VMA"), there is only one user of i915_ggtt_view_normal rodate. Just treat NULL as no special view in pin_to_display() like everywhere else. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem.c | 2 +-

[Intel-gfx] [PATCH 26/26] drm/i915: Use the MRU stack search after evicting

When we evict from the GTT to make room for an object, the hole we create is put onto the MRU stack inside the drm_mm range manager. On the next search pass, we can speed up a PIN_HIGH allocation by referencing that stack for the new hole. v2: Pull together the 3 identical implements (ahem, a coup

[Intel-gfx] [PATCH 08/26] drm/i915: Drain freed objects for mmap space exhaustion

As we now use a deferred free queue for objects, simply retiring the active objects is not enough to immediately free them and recover their mmap space - we must now also drain the freed object list. Fixes: fbbd37b36fa5 ("drm/i915: Move object release to a freelist + worker" Signed-off-by: Chris W

[Intel-gfx] [PATCH 17/26] drm/i915: Align GGTT sizes to a fence tile row

Ensure the view occupies the full tile row so that reads/writes into the VMA do not escape (via fenced detiling) into neighbouring objects - we will pad the object with scratch pages to satisfy the fence. This applies the lazy-tiling we employed on gen2/3 to gen4+. Signed-off-by: Chris Wilson ---

[Intel-gfx] [PATCH 11/26] drm/i915: Pack the partial view size and offset into a single u64

Since the partial offset must be page aligned, we can use those low 12 bits to encode the side of the partial view (which then cannot be larger than 8MiB in pages). Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c | 22 +- drivers/gpu/drm/i915/i915_gem_gtt.

[Intel-gfx] [PATCH 02/26] drm/i915: Move a few utility macros into a separate header

In order to defeat some circular dependencies between headers to allow use of e.g. range_overflows() in a header, move the simple independent macros into their own header. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.h | 13 +--- drivers/gpu/drm/i915/i915_gem.c | 4

[Intel-gfx] [PATCH 24/26] drm/i915: Skip switch to kernel context if already done

Some engines are never user or already sitting idle in the kernel context and for those we can skip flushing the current context for i915_gem_switch_to_kernel_context(). We used to perform this optimisation but that was removed for convenience of converting over to multiple timelines and handling t

[Intel-gfx] [PATCH 16/26] drm/i915: Clip the partial view against the object not vma

The VMA is later clipped against the vm_area_struct before insertion of the faulting PTE so we are free to create the partial view as we desire. If we use the object as the extents rather than the area, this partial can then be used for other areas. Signed-off-by: Chris Wilson --- drivers/gpu/dr

[Intel-gfx] [PATCH 12/26] drm/i915: Convert i915_ggtt_view to use an anonymous union

Save a lot of characters by making the union anonymous, with the side-effect of ignoring unset bits when comparing views. v2: Roll up the memcmps back into one. v3: And split again as Ville points out we can't trust the compiler. Signed-off-by: Chris Wilson Cc: Daniel Vetter --- drivers/gpu/dr

[Intel-gfx] [PATCH 05/26] drm/i915/guc: Exclude the upper end of the Global GTT for the GuC

The GuC uses a special mapping for the upper end of the Global GTT, similar to the way it uses a special mapping for the lower end, so exclude it from our drm_mm to prevent us using it. v2: Rename to reflect that it is unmappable similar to the region at the bottom of the GGTT, and couple it into

[Intel-gfx] [PATCH 09/26] drm/i915: Simplify testing for am-I-the-kernel-context?

The kernel context (dev_priv->kernel_context) is unique in that it is not associated with any user filp - it is the only one with ctx->file_priv == NULL. This is a simpler test than comparing it against dev_priv->kernel_context which involves some pointer dancing. In checking that this is true, we

[Intel-gfx] [PATCH 25/26] drm/i915: Replace 4096 with PAGE_SIZE or I915_GTT_PAGE_SIZE

Start converting over from the byte count to its semantic macro, either we want to allocate the size of a physical page in main memory or we want the size of a virtual page in the GTT. 4096 could mean either, but PAGE_SIZE and I915_GTT_PAGE_SIZE are explicit and should help improve coe comprehensio

[Intel-gfx] [PATCH 07/26] drm/i915: Fix phys pwrite for struct_mutex-less operation

Since commit fe115628d567 ("drm/i915: Implement pwrite without struct-mutex") the lowlevel pwrite calls are now called without the protection of struct_mutex, but pwrite_phys was still asserting that it held the struct_mutex and later tried to drop and relock it. Fixes: fe115628d567 ("drm/i915: Im

[Intel-gfx] [PATCH 15/26] drm/i915: Extact compute_partial_view()

In order to reuse the partial view for selftesting, extract the common function for computing the view. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem.c | 49 + 1 file changed, 30 insertions(+), 19 deletions(-)

[Intel-gfx] Small GEM fixes

Outside of making guc play nicely with high GGTT offsets, a big fix here is the correct implementation of lazy fencing for gen4+. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 03/26] drm/i915: Use fixed-sized types for stolen

Stolen memory is a hardware resource of known size, so use an accurate fixed integer type rather than the ambiguous variable size_t. This was motivated by the next patch spotting inconsistencies in our types. Signed-off-by: Chris Wilson --- drivers/char/agp/intel-gtt.c | 6 -- dri

[Intel-gfx] [PATCH 20/26] drm/i915: Remove the rounding down of the gen4+ fence region

Restricting the fence to the end of the previous tile-row breaks access to the final portion of the object. On gen2/3 we employed lazy fencing to pad out the fence with scratch page to provide access to the tail, and now we also pad out the object on gen4+ we can apply the same fix. Fixes: af1a730

[Intel-gfx] [PATCH 06/26] drm/i915: Purge loose pages if we run out of DMA remap space

If the DMA remap fails, one cause can be that we have too many objects pinned in a small remapping table, such as swiotlb. (DMA remapping does not trigger the shrinker by itself on its normal failure paths.) So try purging all other objects (using i915_gem_shrink_all(), sparing our own pages as we

[Intel-gfx] [PATCH 18/26] drm/i915: Replace WARNs in fence register writes with extensive asserts

All of these conditions are prechecked by i915_tiling_ok() before we allow setting the tiling/stride on the object and so we should never fail asserting those conditions before writing the register. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 50 ++

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915: Move assert of page pin vs bind count into i915_vma_unbind

== Series Details == Series: series starting with [CI,1/4] drm/i915: Move assert of page pin vs bind count into i915_vma_unbind URL : https://patchwork.freedesktop.org/series/17336/ State : success == Summary == Series 17336v1 Series without cover letter https://patchwork.freedesktop.org/api/

[Intel-gfx] [CI 3/4] drm/i915: Complete kerneldoc for struct i915_gem_context

The existing kerneldoc was outdated, so time for a refresh. v2: Use single line kdoc, mention functions for manipulation Signed-off-by: Chris Wilson Reviewed-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h| 99 +-- drivers/gpu/drm/i915/i915_gem.c| 26 +--

[Intel-gfx] [CI 4/4] drm/i915: Drop kerneldoc markup from non-kerneldoc enum drrs_refresh_rate_type

DRRS is not yet kerneldoc despite the allusion prior to enum drrs_refresh_rate_type. Drop the '**' to avoid the warnings from make htmldocs. Signed-off-by: Chris Wilson Reviewed-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --g

[Intel-gfx] [CI 2/4] drm/i915: Fix kerneldoc for i915_gem_object_pin_map()

Parameter - no. Parameter: yes. Signed-off-by: Chris Wilson Reviewed-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 66bd5cf9cd3b..1aa33444115a

[Intel-gfx] [CI 1/4] drm/i915: Move assert of page pin vs bind count into i915_vma_unbind

The read of the page pin count and the bind count are unordered, presenting races in the assert and it firing off incorrectly. Prevent this by restricting the assert to the vma bind/unbind routines where we have local cpu ordering between the two. Signed-off-by: Chris Wilson Cc: Daniel Vetter Re