== Series Details ==
Series: DPCD Backlight Control
URL : https://patchwork.freedesktop.org/series/5333/
State : success
== Summary ==
Series 5333v1 DPCD Backlight Control
http://patchwork.freedesktop.org/api/1.0/series/5333/revisions/1/mbox/
Test gem_sync:
Subgroup basic-all:
dont want to hijack thread but wanted to point out a possible regression
in the
previous patches of this series.
intel_fbc_can_choose: returns true for gen 4/5/6/7. (possible bug)
so intel_crtc_state->enable_fbc = true; will be executed for first crtc
everytime intel_fbc_choose_crtc is called.
When we change the current seqno, we also need to remember to reset the
last_submitted_seqno for the engine.
Testcase: igt/gem_exec_whisper
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
1 file changed, 1 insertion(+)
diff
Having fixed the tracking of the engine's last_submitted_seqno, we can
now rely on it for detecting when the engine is idle (and not have to
touch the requests pointer).
Testcase: igt/gem_exec_whisper
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i9
Since we are setting engine local values that are tied to the hardware,
move it out of i915_gem_init_seqno() into the intel_ring_init_seqno()
backend, next to where the other hw semaphore registers are written.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
---
drivers/gpu/d
It's useful to look at the last seqno submitted on a particular engine
and compare it against the HWS value to check for irregularities.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 --
drivers/gpu/drm/i915/i915_drv.h
After the GPU reset and we discard all of the incomplete requests, mark
the GPU as having advanced to the last_submitted_seqno (as having
completed the requests and ready for fresh work). The impact of this is
negligible, as all the requests will be considered completed by this
point, it just bring
An oversight is that when we wrap the seqno, we need to reset the hw
semaphore counters to 0. We did this for gen6 and gen7 and forgot to do
so for the new implementation required for gen8 (legacy).
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/inte
We only use drm_i915_private within the function, so delete the unneeded
drm_device local.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i9
Hi. Currently I'm working on a bug in the i915 driver where hotplugging seems to
break if we power on the machine without any connectors attached:
https://bugzilla.redhat.com/show_bug.cgi?id=1277863
So the main cause of the issue seems to be that we're not keeping the right
power wells on for HPD
On Tue, Apr 05, 2016 at 02:37:19PM -0700, Matt Roper wrote:
> intel_update_max_cdclk() doesn't have a switch case for Broxton, so
> dev_priv->max_cdclk_freq gets set to whatever clock frequency we're
> currently running at (e.g., 144 MHz) rather than the true maximum. This
> causes our max dotcloc
intel_update_max_cdclk() doesn't have a switch case for Broxton, so
dev_priv->max_cdclk_freq gets set to whatever clock frequency we're
currently running at (e.g., 144 MHz) rather than the true maximum. This
causes our max dotclock to also be set too low and in turn leads mode
verification to reje
While writing a utility that parses information from the debugfs file
i915_dp_mst_info and formats it in a more easily human-readable fashion,
I noticed a few things missing from the debug output that would be nice to
have. Most notably, there was not an easy way to associate a particular
sink dev
In order to include monitor name information in debugfs
output we needed to add a function that would extract the
monitor name from the EDID, and that function needed to
reside in the file where the rest of the EDID helper
functions are implemented.
cc: dri-de...@lists.freedesktop.org
Signed-off-
Add some additional information (input vs. output port, sink associated
with VC, peer device type, max number of VCs supported) and ensure that
any embedded '\0' characters in a branch device's devid string are not
written to debugfs.
cc: dri-de...@lists.freedesktop.org
Signed-off-by: Jim Bride
-
Modify the debugfs output for i915_dp_mst_info to list the source port for
the DP MST topology in question.
Signed-off-by: Jim Bride
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/dr
Use a table similar to vlv to check for accepted gpio indexes. For now,
add all, but this list should be trimmed down. Use managed gpio request,
which will be automatically released when the driver is detached.
Signed-off-by: Jani Nikula
---
I didn't address review comments to this one yet, but
The shorthand is easier. Also change the struct name. No functional
changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
b/drivers/gpu/drm
Prepare for future. No functional changes.
v2: Move earlier in the series. Use bool for gpio value.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 68 +++---
1 file changed, 35 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915
Define and store the pad base offset in the array, and reference the
pconf0 and padval registers through macros. Add VLV prefixes to
macros. Use spec nomenclature for pconf0 and padval.
v2: Address Ville's review comments, squash another patch here.
v3: Use the names Ville dug up in the specs.
S
Add support for CHV gpio programming in DSI gpio elements.
v2: Overhaul macros according to Ville's review.
[Rewritten by Jani, based on earlier work by Yogesh and Deepak.]
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Deepak M
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel
Just put the iosf port in the gpio table. The table might include some
duplication, but this approach keeps the code the cleanest.
v2: pack the struct better (Ville), use designated initializers, add
debug logging for mismatching ports
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_d
Next iteration after [1]. Last patch merely rebased, and review comments
not addressed, but included here for completeness.
BR,
Jani.
[1] http://mid.gmane.org/cover.1458299160.git.jani.nik...@intel.com
Jani Nikula (6):
drm/i915/dsi: clean up vlv gpio table and definitions
drm/i915/dsi: abst
On Wed, Mar 16, 2016 at 07:47:06PM +0200, Ville Syrjälä wrote:
> On Wed, Mar 16, 2016 at 07:17:51PM +0200, Imre Deak wrote:
> > On Fri, 2016-03-04 at 21:43 +0200, ville.syrj...@linux.intel.com wrote:
> > > From: Ville Syrjälä
> > >
> > > Extract the GPLL reference frequency from CCK and use it in
From: Ville Syrjälä
My BSW takes ~12 seconds to go back to idle after high load, so the
current 10s timeouts are too short. Bump them up to 15s.
Signed-off-by: Ville Syrjälä
---
tests/pm_rps.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/pm_rps.c b/tests/pm_rps
Hi Bastien,
On Tue, Apr 05, 2016 at 06:59:40PM +0200, Bastien Nocera wrote:
> I tested the runtime patches for Radeon on top of 4.6.0-rc2, and
> writing DIGD failed. I also saw a number of messages with the
> vga_switcheroo core in the kernel trying to switch GPUs but failed
> because "client 1" w
On Tue, Apr 05, 2016 at 08:34:02PM +0300, Marius Vlad wrote:
> On Tue, Apr 05, 2016 at 06:23:21PM +0100, Chris Wilson wrote:
> > On Tue, Apr 05, 2016 at 08:13:23PM +0300, Marius Vlad wrote:
> > > Signed-off-by: Marius Vlad
> > > ---
> > > tests/gem_concurrent_all.c | 2 +-
> > > 1 file changed, 1
On Tue, Apr 05, 2016 at 06:23:21PM +0100, Chris Wilson wrote:
> On Tue, Apr 05, 2016 at 08:13:23PM +0300, Marius Vlad wrote:
> > Signed-off-by: Marius Vlad
> > ---
> > tests/gem_concurrent_all.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/tests/gem_concurrent_a
On Tue, Apr 05, 2016 at 08:13:23PM +0300, Marius Vlad wrote:
> Signed-off-by: Marius Vlad
> ---
> tests/gem_concurrent_all.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/gem_concurrent_all.c b/tests/gem_concurrent_all.c
> index 10e5357..e84ded3 100644
> --- a/te
Signed-off-by: Marius Vlad
---
tests/gem_concurrent_all.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/gem_concurrent_all.c b/tests/gem_concurrent_all.c
index 10e5357..e84ded3 100644
--- a/tests/gem_concurrent_all.c
+++ b/tests/gem_concurrent_all.c
@@ -650,7 +650,7 @@
On Mon, 2016-03-14 at 13:41 +0100, Lukas Wunner wrote:
>
> > So I'd push DIGD to the switch sysfs entry on boot. But I'm
> > guessing
> > that won't turn off the other output we're not interested in.
> IGD and DIGD switch to the integrated GPU and also turn off the
> discrete
> GPU. However if th
== Series Details ==
Series: series starting with [v2,3/3] drm/i915/userptr: Store i915 backpointer
for i915_mm_struct (rev4)
URL : https://patchwork.freedesktop.org/series/5240/
State : failure
== Summary ==
Series 5240v4 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/s
Hi Peter,
This patch is required for the BXT firmware loading. (Maybe/Probably
something similar for KBL is also required)
Do you have plans to fix this interpretation as Dave pointed and send
a new version?
Thanks,
Rodrigo.
On Wed, Feb 3, 2016 at 7:39 AM, Dave Gordon wrote:
> On 21/01/16 21:4
== Series Details ==
Series: DPCD Backlight Control
URL : https://patchwork.freedesktop.org/series/5330/
State : success
== Summary ==
Series 5330v1 DPCD Backlight Control
http://patchwork.freedesktop.org/api/1.0/series/5330/revisions/1/mbox/
Test kms_flip:
Subgroup basic-flip-vs-wf_v
== Series Details ==
Series: series starting with [1/6] drm/i915/dmabuf: Tighten struct_mutex for
unmap_dma_buf
URL : https://patchwork.freedesktop.org/series/5325/
State : failure
== Summary ==
Series 5325v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/5325/rev
On Tue, Apr 05, 2016 at 03:56:17PM +0300, Mika Kuoppala wrote:
> Experiments with heaven 4.0 benchmark and skylake gt3e (rev 0xa)
> suggest that WaForceContextSaveRestoreNonCoherent is needed for all
> revs. Extending this to all revs cures a gpu hang with rev 0xa when
> running heaven4.0 gpu bench
== Series Details ==
Series: series starting with [1/2] drm/i915/skl: Fix rc6 based gpu/system hang
URL : https://patchwork.freedesktop.org/series/5324/
State : success
== Summary ==
Series 5324v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/5324/revisions/1/mbox
On 05/04/16 14:59, Chris Wilson wrote:
In order to ensure that all invalidations are completed before the
operation returns to userspace (i.e. before the munmap() syscall returns)
we need to wait upon the outstanding operations.
We are allowed to block inside the invalidate_range_start callback
On Tue, Apr 05, 2016 at 02:42:16PM +0100, Tvrtko Ursulin wrote:
> >>@@ -587,9 +587,6 @@ static int execlists_context_queue(struct
> >>drm_i915_gem_request *request)
> >> struct drm_i915_gem_request *cursor;
> >> int num_elements = 0;
> >>
> >>-if (request->ctx != ring->default_context
On Tue, 05 Apr 2016, Mika Kuoppala wrote:
> Experiments with heaven 4.0 benchmark and skylake gt3e (rev 0xa)
> suggest that WaForceContextSaveRestoreNonCoherent is needed for all
> revs. Extending this to all revs cures a gpu hang with rev 0xa when
> running heaven4.0 gpu benchmark.
>
> We have be
(Adding Jani again, who got dropped for some reason)
On 1 April 2016 at 16:50, Ezequiel Garcia wrote:
> On 01 Apr 06:46 PM, Ville Syrjälä wrote:
>> On Fri, Apr 01, 2016 at 12:38:11PM -0300, Ezequiel Garcia wrote:
>> > El abr. 1, 2016 11:47 AM, "Ville Syrjälä"
>> > escribió:
>> > >
>> > > On Thu,
== Series Details ==
Series: HPD support during suspend.
URL : https://patchwork.freedesktop.org/series/5322/
State : failure
== Summary ==
Series 5322v1 HPD support during suspend.
http://patchwork.freedesktop.org/api/1.0/series/5322/revisions/1/mbox/
Test drv_getparams_basic:
Subgro
On Tue, Apr 05, 2016 at 03:27:24PM +0100, Chris Wilson wrote:
> On Tue, Apr 05, 2016 at 03:17:30PM +0100, Tvrtko Ursulin wrote:
> >
> > On 05/04/16 15:09, Chris Wilson wrote:
> > >On Tue, Apr 05, 2016 at 02:42:16PM +0100, Tvrtko Ursulin wrote:
> > @@ -587,9 +587,6 @@ static int execlists_conte
On Tue, Apr 05, 2016 at 02:02:38PM +0100, Daniel Stone wrote:
> Hi,
>
> On 4 April 2016 at 22:17, Matt Roper wrote:
> > i915 does not yet support the atomic modesetting interface by default;
> > at the moment it must be turned on explicitly via an
> > 'i915.nuclear_pageflip' kernel command line o
== Series Details ==
Series: DPCD Backlight Control
URL : https://patchwork.freedesktop.org/series/5323/
State : failure
== Summary ==
LD drivers/pci/built-in.o
CC drivers/usb/storage/option_ms.o
CC drivers/usb/host/ehci-pci.o
LD drivers/usb/gadget/libcomposite.o
Hi Animesh,
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20160405]
[cannot apply to v4.6-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Animesh
On Tue, Apr 05, 2016 at 03:17:30PM +0100, Tvrtko Ursulin wrote:
>
> On 05/04/16 15:09, Chris Wilson wrote:
> >On Tue, Apr 05, 2016 at 02:42:16PM +0100, Tvrtko Ursulin wrote:
> @@ -587,9 +587,6 @@ static int execlists_context_queue(struct
> drm_i915_gem_request *request)
> struct
Add new edp_dpcd variable to intel_dp.
Read and save eDP Display control capability registers to edp_dpcd.
Signed-off-by: Yetunde Adebisi
---
drivers/gpu/drm/i915/intel_dp.c | 15 ++-
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 11 insertions(+), 5 deletions(-)
diff --
This is used when reading Display Control capability Registers on the sink
device.
cc: dri-de...@lists.freedesktop.org
Signed-off-by: Yetunde Adebisi
Reviewed-by: Jani Nikula
---
include/drm/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_dp_helper.h b/includ
On 05/04/16 15:09, Chris Wilson wrote:
On Tue, Apr 05, 2016 at 02:42:16PM +0100, Tvrtko Ursulin wrote:
@@ -587,9 +587,6 @@ static int execlists_context_queue(struct
drm_i915_gem_request *request)
struct drm_i915_gem_request *cursor;
int num_elements = 0;
-if (request->ctx != ri
This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.
It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.
v2: Moved backlight functions from intel_
These patches add support for Backlight Control using DPCD registers on eDP
displays.
- Patch 1 Adds macro for DPCD registers capability size to drm_dp_helper.h
- Patch 2 Reads the eDP DPCD Display Control capability registers.
- Patch 2 Implements functionaly for DPCD Backlight Control
Yetunde
On Tue, Apr 05, 2016 at 02:42:16PM +0100, Tvrtko Ursulin wrote:
> I felt was so close in getting rid of execlist_retired_req_queue,
> using this patch as a starting point, when I realised this patch
> does not play nicely with the GuC. Back to the drawing board. :(
I will also say that we need to
In order to ensure that all invalidations are completed before the
operation returns to userspace (i.e. before the munmap() syscall returns)
we need to wait upon the outstanding operations.
We are allowed to block inside the invalidate_range_start callback, and
as struct_mutex is the inner lock wi
On Tue, 05 Apr 2016, Animesh Manna wrote:
> To support hpd during sleep a new feature flag is
> added in vbt and also in dev_priv for enabling/disabling
> inside deiver. By default this feature will be
> diabled and based on oem request this feature can
> be enabled by changing vbt feature flag.
>
Since we only ever use the drm_i915_private from the stored
i915_mm_struct->dev, save some electrons by storing the right
backpointer.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Michał Winiarski
Reviewed-by: Michał Winiarski
---
drivers/gpu/drm/i915/i915_gem_userptr.c | 10 +-
Holding a reference to the containing task_struct is not sufficient to
prevent the mm_struct from being reaped under memory pressure. If this
happens whilst we are calling get_user_pages(), explosions erupt -
sometimes an immediate GPF, sometimes page flag corruption. To prevent
the target mm from
On Tue, 05 Apr 2016, ville.syrj...@linux.intel.com wrote:
> [ text/plain ]
> From: Ville Syrjälä
>
> Actually use the builtin register spec on gen4. Makes intel_reg dump
> actually do something on gen4.
>
> Signed-off-by: Ville Syrjälä
> ---
> tools/intel_reg_decode.c | 2 +-
> 1 file changed, 1
This is used when reading Display Control capability Registers on the sink
device.
cc: Jani Nikula
cc: dri-de...@lists.freedesktop.org
Signed-off-by: Yetunde Adebisi
---
include/drm/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm
These patches add support for Backlight Control using DPCD registers on eDP
displays.
- Patch 1 Adds macro for DPCD registers capability size to drm_dp_helper.h
- Patch 2 Reads the eDP DPCD Display Control capability registers.
- Patch 2 Implements functionaly for DPCD Backlight Control
Yetunde
This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.
It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.
v2: Moved backlight functions from intel_
Add new edp_dpcd variable to intel_dp.
Read and save eDP Display control capability registers to edp_dpcd.
Signed-off-by: Yetunde Adebisi
---
drivers/gpu/drm/i915/intel_dp.c | 15 ++-
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 11 insertions(+), 5 deletions(-)
diff --
On 08/03/16 13:15, Tvrtko Ursulin wrote:
On 11/01/16 09:16, Chris Wilson wrote:
If we move the release of the GEM request (i.e. decoupling it from the
various lists used for client and context tracking) after it is complete
(either by the GPU retiring the request, or by the caller cancelling t
== Series Details ==
Series: drm/i915: Add a way to test the modeset done during gpu reset.
URL : https://patchwork.freedesktop.org/series/5314/
State : failure
== Summary ==
Series 5314v1 drm/i915: Add a way to test the modeset done during gpu reset.
http://patchwork.freedesktop.org/api/1.0/s
On Tue, Apr 05, 2016 at 02:12:43PM +0100, Lionel Landwerlin wrote:
> On 05/04/16 12:48, Ville Syrjälä wrote:
> > On Tue, Apr 05, 2016 at 12:11:19PM +0100, Lionel Landwerlin wrote:
> >> This fixes potential crashes when the framebuffer is unset from a
> >> given plane.
> >>
> >> Signed-off-by: Lione
Hi Yetunde,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.6-rc2 next-20160405]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Yetunde-Adebisi/DPCD-Backlight
This fixes potential crashes when the framebuffer is unset from a
given plane.
v2: s/with/within/ typo in header
Signed-off-by: Lionel Landwerlin
Cc: Maarten Lankhorst
Cc: Marius Vlad
Cc: Ville Syrjälä
---
lib/igt_fb.h | 4
lib/igt_kms.c | 32
lib/igt_
I use :autocmd FileType gitcommit setlocal spell
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 05/04/16 12:48, Ville Syrjälä wrote:
On Tue, Apr 05, 2016 at 12:11:19PM +0100, Lionel Landwerlin wrote:
This fixes potential crashes when the framebuffer is unset from a
given plane.
Signed-off-by: Lionel Landwerlin
Cc: Maarten Lankhorst
Cc: Marius Vlad
Cc: Ville Syrjälä
---
lib/igt_fb
On Tue, Apr 05, 2016 at 01:57:36PM +0100, Chris Wilson wrote:
> I have instances where I want to use drm_malloc_ab() but with a custom
> gfp mask. And with those, where I want a temporary allocation, I want to
> try a high-order kmalloc() before using a vmalloc().
>
> So refactor my usage into drm
Hi,
On 4 April 2016 at 22:17, Matt Roper wrote:
> i915 does not yet support the atomic modesetting interface by default;
> at the moment it must be turned on explicitly via an
> 'i915.nuclear_pageflip' kernel command line option. We should skip
> (rather than fail) this IGT test when running on
On Tue, Apr 05, 2016 at 01:57:37PM +0100, Chris Wilson wrote:
> If we want a contiguous mapping of a single page sized object, we can
> forgo using vmap() and just use a regular kmap(). Note that this is only
> suitable if the desired pgprot_t is comptabitible.
One day, I will enable :set spell. D
On Tue, Apr 05, 2016 at 12:56:37PM +0200, Maarten Lankhorst wrote:
> Add force_reset_modeset_test as a parameter to force the modeset path during
> gpu reset.
> This allows a IGT test to set the knob and trigger a hang to force the gpu
> reset.
>
> Signed-off-by: Maarten Lankhorst
> Fixes: e2c8
05.04.2016, 15:56, Mika Kuoppala kirjoitti:
> For all gt3 and gt4 skylake variants, extend the usage of
> WaRsDisableCoarsePowerGating for all revisions. Without this
> gt3 and gt4 skylakes up to atleast rev 0xa can gpu hang or
> system hang.
>
> Cc: Abdiel Janulgue
> Cc: Ben Widawsky
> Cc: Timo
On Thu, Mar 31, 2016 at 06:46:36PM -0700, Matt Roper wrote:
> Moving watermark calculation into the check phase will allow us to to
> reject display configurations for which there are no valid watermark
> values before we start trying to program the hardware (although those
> tests will come in a s
We have a couple of pieces of code that wish to take further advantange
of prolonged vmappings: execlists (ringbuffers), the cmdparser and the GuC
(workqueues). This series refactors the whole-object vmapping code and
caches it on the drm_i915_gem_object until it is released along with the
object's
We now have two implementations for vmapping a whole object, one for
dma-buf and one for the ringbuffer. If we couple the vmapping into the
obj->pages lifetime, then we can reuse an obj->vmapping for both and at
the same time couple it into the shrinker.
v2: Mark the failable kmalloc() as __GFP_NO
When called because we have run out of vmap address space, we only need
to recover objects that have vmappings and not all.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem_shrinker.c | 10 +-
2 files changed, 10 insertions(+)
If we want a contiguous mapping of a single page sized object, we can
forgo using vmap() and just use a regular kmap(). Note that this is only
suitable if the desired pgprot_t is comptabitible.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 22 --
1 file ch
I have instances where I want to use drm_malloc_ab() but with a custom
gfp mask. And with those, where I want a temporary allocation, I want to
try a high-order kmalloc() before using a vmalloc().
So refactor my usage into drm_malloc_gfp().
Signed-off-by: Chris Wilson
Cc: dri-de...@lists.freedes
After we pin the ringbuffer into the GGTT, all error paths need to unpin
it again. Move this common step into one block, and make the unable to
iomap error code consistent (i.e. treat it as out of memory to avoid
confusing it with a invalid argument).
Signed-off-by: Chris Wilson
---
drivers/gpu/
We only need the struct_mutex to manipulate the pages_pin_count on the
object, we do not need to hold our BKL when freeing the exported
scatterlist.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_dmabuf.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drive
For all gt3 and gt4 skylake variants, extend the usage of
WaRsDisableCoarsePowerGating for all revisions. Without this
gt3 and gt4 skylakes up to atleast rev 0xa can gpu hang or
system hang.
Cc: Abdiel Janulgue
Cc: Ben Widawsky
Cc: Timo Aaltonen
Cc:
Reported-by: Mikael Djurfeldt
References: h
Experiments with heaven 4.0 benchmark and skylake gt3e (rev 0xa)
suggest that WaForceContextSaveRestoreNonCoherent is needed for all
revs. Extending this to all revs cures a gpu hang with rev 0xa when
running heaven4.0 gpu benchmark.
We have been here before, with problems enabling gt4e and extend
This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.
It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.
v2: Moved backlight functions from intel_
These patches add support for Backlight Control using DPCD registers on eDP
displays.
- Patch 1 Reads the eDP DPCD Display Control capability registers.
- Patch 2 Implements functionaly for DPCD Backlight Control
Yetunde Adebisi (2):
drm/i915: Add edp_dpcd variable
drm/i915: Add Backlight
Add new edp_dpcd variable to intel_dp.
Read and save eDP Display control capability registers to edp_dpcd.
Signed-off-by: Yetunde Adebisi
---
drivers/gpu/drm/i915/intel_dp.c | 15 ++-
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 11 insertions(+), 5 deletions(-)
diff --
For BXT, display engine can not generate interrupt when in D3.
On the othen hand S0ix can be achieved without display in D3. So,
Display should not put into D3 for HPD to work and will not
have any power impact.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.c | 6 ++
1 file
Along with below patches sharing some background details/design.
- On BXT, Display cannot generate an interrupt when in D3.
- Without display in D3, S0ix can be achieved, Power impact
will be zero if d3 is blocked. PMCSR for Graphics/Display
is irrelevant, as the power management for them is taken
Based on vbt entry enabling i915 driver to act on
hpd support during suspend.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_bios.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 9c406b0..8ed084
Guid is changed for bxt platform, so corrected the guid for bxt.
Signed-off-by: Ananth Krishna R
Signed-off-by: Bharath K Veera
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_acpi.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/int
While suspending the device hpd related interrupts are enabled
to get the interrupt when device is in suspend state.
Though display is in DC9 but system can be in S0 or S0i3 state.
Hot plug during S0 state will generate de_port_interrupt but if
system is in S0i3 state then display driver will get
To support hpd during sleep a new feature flag is
added in vbt and also in dev_priv for enabling/disabling
inside deiver. By default this feature will be
diabled and based on oem request this feature can
be enabled by changing vbt feature flag.
Signed-off-by: Animesh Manna
Signed-off-by: A.Sunil
2016-04-02 15:08 GMT+01:00 Oskar Berggren :
> Hi,
>
> After trying two different machines I'm beginning to feel like Skylake is
> completely unusable with multiple monitors connected. Is this a known
> limitation? Am I the only one experiencing this?
>
> First I tested on laptop Dell XPS 15 9550 w
_DSM is added to program HPD_CTL(0x1094) register
of PMC from i915 driver which will be called
based on driver feature flag. PMC hpd control register
programming will enable PMC to get hpd interrupt
during dc9.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_acpi.c | 45 +
On Tue, Apr 05, 2016 at 01:05:05PM +0100, Tvrtko Ursulin wrote:
>
> On 03/04/16 18:14, Chris Wilson wrote:
> >In order to ensure that all invalidations are completed before the
> >operation returns to userspace (i.e. before the mmap() syscall returns)
> >we need to flush the outstanding operations
On 05/04/16 13:03, Dave Gordon wrote:
On 05/04/16 07:56, Patchwork wrote:
== Series Details ==
Series: GuC reset-and-retry patches (resend)
URL : https://patchwork.freedesktop.org/series/5287/
State : failure
== Summary ==
Series 5287v1 GuC reset-and-retry patches (resend)
http://patchwork
On 03/04/16 18:14, Chris Wilson wrote:
Holding a reference to the containing task_struct is not sufficient to
prevent the mm_struct from being reaped under memory pressure. If this
happens whilst we are calling get_user_pages(), explosions errupt -
sometimes an immediate GPF, sometimes page flag
== Series Details ==
Series: drm/i915/bxt: Fix/enable display power well support/runtime PM (rev5)
URL : https://patchwork.freedesktop.org/series/5177/
State : success
== Summary ==
Series 5177v5 drm/i915/bxt: Fix/enable display power well support/runtime PM
http://patchwork.freedesktop.org/ap
Reviewed-by: Matthew Auld
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
1 - 100 of 148 matches
Mail list logo
