On Tue, 05 Apr 2016, Mika Kuoppala <mika.kuopp...@linux.intel.com> wrote:
> Experiments with heaven 4.0 benchmark and skylake gt3e (rev 0xa)
> suggest that WaForceContextSaveRestoreNonCoherent is needed for all
> revs. Extending this to all revs cures a gpu hang with rev 0xa when
> running heaven4.0 gpu benchmark.
>
> We have been here before, with problems enabling gt4e and extending
> up to revision F0 instead of false claims of bspec of E0 only. See
> commit <e238659ddd88> ("drm/i915/skl: Default to noncoherent access
> up to F0"). In retrospect we should have covered this with this big
> blanket back then already, as E0 vs F0 discrepancy was suspicious
> enough.
>
> Previously the WaForceEnableNonCoherent has been tied to
> context non-coherence, atleast in relevant hsds. So keep this tie
> and extended this alongside.
>
> Cc: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
> Cc: Ben Widawsky <benjamin.widaw...@intel.com>
> Cc: Timo Aaltonen <tjaal...@ubuntu.com>
> Cc: sta...@vger.kernel.org
> Reported-by: Mike Lothian <m...@fireburn.co.uk>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=93491
> Signed-off-by: Mika Kuoppala <mika.kuopp...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 45ce45a5e122..7fce1e6afcbc 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -968,7 +968,7 @@ static int gen9_init_workarounds(struct intel_engine_cs
> *ring)
>
> /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
> tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
> - if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) ||
> + if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) ||
Side note only slightly related to this patch: We need to start dropping
support for old steppings, only leaving production steppings in place.
BR,
Jani.
> IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
> tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
> WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
> @@ -1085,7 +1085,8 @@ static int skl_init_workarounds(struct intel_engine_cs
> *ring)
> WA_SET_BIT_MASKED(HIZ_CHICKEN,
> BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
>
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) {
> + /* This is tied to WaForceContextSaveRestoreNonCoherent */
> + if (IS_SKL_REVID(dev, 0, REVID_FOREVER)) {
> /*
> *Use Force Non-Coherent whenever executing a 3D context. This
> * is a workaround for a possible hang in the unlikely event
--
Jani Nikula, Intel Open Source Technology Center
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