On Thu, Mar 31, 2016 at 12:36 PM, Dave Gordon wrote:
> On 24/03/16 12:47, Chris Wilson wrote:
>>
>> On Thu, Mar 24, 2016 at 12:29:32PM +, Dave Gordon wrote:
>>>
>>> On 24/03/16 09:54, Chris Wilson wrote:
On Thu, Mar 24, 2016 at 10:34:58AM +0100, Sedat Dilek wrote:
>
> [ build
Hi Dongwon,
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20160401]
[cannot apply to v4.6-rc1]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Dongwon
With IPC(Isochronous Priority Control) enabled,
display sends requests based on the priority of each
request. To enable it, a i915 param, i915.enable_ipc
should be set to 1.
Signed-off-by: Dongwon Kim
---
drivers/gpu/drm/i915/i915_params.c | 5 +
drivers/gpu/drm/i915/i915_params.h | 1 +
dri
On Mon, Mar 21, 2016 at 02:43:22PM +, Matthew Auld wrote:
> From: Ville Syrjälä
>
> Deal with errors from drm_universal_plane_init() in primary and cursor
> plane init paths (sprites were already covered). Also make the code
> neater by using goto for error handling.
>
> v2: Rebased due to d
On Tue, Mar 22, 2016 at 08:32:50AM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Fix plane init failure paths (rev2)
> URL : https://patchwork.freedesktop.org/series/4708/
> State : warning
>
> == Summary ==
>
> Series 4708v2 drm/i915: Fix plane init failure paths
> http
On Tue, Mar 22, 2016 at 04:08:39PM +0100, Maarten Lankhorst wrote:
> Op 22-03-16 om 15:58 schreef Ville Syrjälä:
> > On Tue, Mar 22, 2016 at 03:42:14PM +0100, Maarten Lankhorst wrote:
> >> __drm_atomic_helper_plane_destroy_state calls
> >> drm_framebuffer_unreference, which means that if drm_frameb
On Wed, Mar 23, 2016 at 10:58:21PM +, Zanoni, Paulo R wrote:
> Em Qua, 2016-03-23 às 23:57 +0200, Ville Syrjälä escreveu:
> > On Wed, Mar 23, 2016 at 09:14:34PM +, Zanoni, Paulo R wrote:
> > >
> > > Em Ter, 2016-03-01 às 16:16 +0200, ville.syrj...@linux.intel.com
> > > escreveu:
> > > >
>
On Wed, Mar 30, 2016 at 04:31:04PM +0300, Jani Nikula wrote:
> On Tue, 15 Mar 2016, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > The VLV and CHV DPLL disable and update are almost identical in
> > how the DPLL/DPLL_MD registers need to be set up. But the code
> > looks more
On Wed, Mar 16, 2016 at 11:05:30AM +0200, Jani Nikula wrote:
> On Tue, 15 Mar 2016, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > VLV DPLL is somewhat sane and doesn't run on luck.
> >
> > Signed-off-by: Ville Syrjälä
>
> Acked-by: Jani Nikula
Pushed to dinq up to this p
On Fri, Apr 01, 2016 at 10:47:13PM +0300, Ville Syrjälä wrote:
> On Fri, Apr 01, 2016 at 08:39:22PM +0100, Chris Wilson wrote:
> > On Fri, Apr 01, 2016 at 10:12:09PM +0300, Ville Syrjälä wrote:
> > > On Tue, Mar 15, 2016 at 03:27:30PM -, Patchwork wrote:
> > > > == Series Details ==
> > > >
>
On 01 Apr 06:46 PM, Ville Syrjälä wrote:
> On Fri, Apr 01, 2016 at 12:38:11PM -0300, Ezequiel Garcia wrote:
> > El abr. 1, 2016 11:47 AM, "Ville Syrjälä"
> > escribió:
> > >
> > > On Thu, Mar 31, 2016 at 05:55:03PM -0300, Ezequiel Garcia wrote:
> > > > Currently, our implementation of drm_connecto
On Fri, Apr 01, 2016 at 08:39:22PM +0100, Chris Wilson wrote:
> On Fri, Apr 01, 2016 at 10:12:09PM +0300, Ville Syrjälä wrote:
> > On Tue, Mar 15, 2016 at 03:27:30PM -, Patchwork wrote:
> > > == Series Details ==
> > >
> > > Series: drm/i915: DSI and DPLL stuff for VLV/CHV mostly
> > > URL :
On Fri, Apr 01, 2016 at 10:12:09PM +0300, Ville Syrjälä wrote:
> On Tue, Mar 15, 2016 at 03:27:30PM -, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915: DSI and DPLL stuff for VLV/CHV mostly
> > URL : https://patchwork.freedesktop.org/series/4472/
> > State : failure
> >
>
On Tue, Mar 15, 2016 at 03:27:30PM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: DSI and DPLL stuff for VLV/CHV mostly
> URL : https://patchwork.freedesktop.org/series/4472/
> State : failure
>
> == Summary ==
>
> Series 4472v1 drm/i915: DSI and DPLL stuff for VLV/CHV mo
From: Ville Syrjälä
The underruns we were seeing when enabling eDP port A on ILK seem to
have been caused by prematurely clearing the LP1+ watermark values when
disabling LP1+ watermarks. Now that the watermarks are handled
properly, we can rip out the underrun suppression around the port A
enabl
From: Ville Syrjälä
Take a bigger hammer to the underrun suppression on ILK. Instead of
trying to suppress them at specific points in the modeset sequence just
silence them across the entire sequence. This gets rid of some underruns
at least on my ILK. Note that this changes SNB and IVB to follow
From: Ville Syrjälä
With this series I seem to have succeeded in eliminating all the underruns
from my ILK. Let's hope it's as effective for others as well.
Ville Syrjälä (3):
drm/i915: Try to shut up more ILK underruns
drm/i915: Make sure LP1+ watermarks levels are preserved when going
From: Ville Syrjälä
Once again ILK is unhappy if we clear out the LP1+ watermark levels
outright, and instead we must disable the levels we don't want while
still leaving the actual programmed watermark levels intact.
Fixes underruns on the already enabled pipe when programming watermarks
while
From: Ville Syrjälä
Eliminate the duplicate code for pipe timing readout in
intel_crtc_mode_get() by using the functions we use for the normal state
readout.
v2: Store dotclock in adjusted_mode instead of the final mode
Cc: dri-de...@lists.freedesktop.org
Cc: Rob Kramer
Cc: Daniel Vetter
Sign
On Fri, 1 Apr 2016 17:03:37 +
Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Read DPCD when connector forced on.
> URL : https://patchwork.freedesktop.org/series/5185/
> State : failure
>
> == Summary ==
>
> Series 5185v1 drm/i915: Read DPCD when connector forced on.
> htt
== Series Details ==
Series: drm/i915: Read DPCD when connector forced on.
URL : https://patchwork.freedesktop.org/series/5185/
State : failure
== Summary ==
Series 5185v1 drm/i915: Read DPCD when connector forced on.
http://patchwork.freedesktop.org/api/1.0/series/5185/revisions/1/mbox/
Test
On Fri, Apr 01, 2016 at 04:44:01PM -, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915: Read timings from the correct
> transcoder in intel_crtc_mode_get()
> URL : https://patchwork.freedesktop.org/series/5183/
> State : warning
>
> == Summary ==
>
>
On 01/04/2016 18:02, Ville Syrjälä wrote:
On Fri, Apr 01, 2016 at 05:43:37PM +0100, Arun Siluvery wrote:
This WA is applied in two different places for SKL GT3, GT4 until
E0. Previously we were applying until F0 at one place.
A macro was introduced in the below commit to replace both usages but
== Series Details ==
Series: series starting with [1/2] drm/i915: Read timings from the correct
transcoder in intel_crtc_mode_get()
URL : https://patchwork.freedesktop.org/series/5183/
State : warning
== Summary ==
Series 5183v1 Series without cover letter
http://patchwork.freedesktop.org/api
On Fri, Apr 01, 2016 at 05:43:37PM +0100, Arun Siluvery wrote:
> This WA is applied in two different places for SKL GT3, GT4 until
> E0. Previously we were applying until F0 at one place.
>
> A macro was introduced in the below commit to replace both usages but now
> we apply this WA until F0 in b
This WA is applied in two different places for SKL GT3, GT4 until
E0. Previously we were applying until F0 at one place.
A macro was introduced in the below commit to replace both usages but now
we apply this WA until F0 in both places, this patch correct this.
commit 06e668ac91c93eb10bd21dfc
When a DP connector is forced on using using the video=:e
kernel command line, we bypass the calls to check if the port is
connected and also bypass the call to intel_dp_detect_dpcd(); The
result is that we don't query for the sink capabilities like the
max link bandwidth. The sink capabilities a
On Fri, Apr 01, 2016 at 12:38:11PM -0300, Ezequiel Garcia wrote:
> El abr. 1, 2016 11:47 AM, "Ville Syrjälä"
> escribió:
> >
> > On Thu, Mar 31, 2016 at 05:55:03PM -0300, Ezequiel Garcia wrote:
> > > Currently, our implementation of drm_connector_funcs.detect is
> > > based on getting a valid EDID
El abr. 1, 2016 11:47 AM, "Ville Syrjälä"
escribió:
>
> On Thu, Mar 31, 2016 at 05:55:03PM -0300, Ezequiel Garcia wrote:
> > Currently, our implementation of drm_connector_funcs.detect is
> > based on getting a valid EDID.
> >
> > This requirement makes the driver fail to detect connected
> > conn
From: Ville Syrjälä
intel_crtc->config->cpu_transcoder isn't yet filled out when
intel_crtc_mode_get() gets called during output probing, so we should
not use it there. Instead intel_crtc_mode_get() figures out the correct
transcoder on its own, and that's what we should use.
If the BIOS boots L
From: Ville Syrjälä
Eliminate the duplicate code for pipe timing readout in
intel_crtc_mode_get() by using the functions we use for the normal state
readout.
Cc: dri-de...@lists.freedesktop.org
Cc: Rob Kramer
Cc: Daniel Vetter
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_displ
== Series Details ==
Series: drm/i915/bxt: Fix/enable display power well support/runtime PM (rev2)
URL : https://patchwork.freedesktop.org/series/5177/
State : success
== Summary ==
Series 5177v2 drm/i915/bxt: Fix/enable display power well support/runtime PM
http://patchwork.freedesktop.org/ap
On Thu, Mar 31, 2016 at 05:55:03PM -0300, Ezequiel Garcia wrote:
> Currently, our implementation of drm_connector_funcs.detect is
> based on getting a valid EDID.
>
> This requirement makes the driver fail to detect connected
> connectors in case of EDID corruption, which prevents from falling
> b
On Thu, Mar 31, 2016 at 10:06:37PM +, Zanoni, Paulo R wrote:
> Em Ter, 2016-02-23 às 18:46 +0200, ville.syrj...@linux.intel.com
> escreveu:
> > From: Ville Syrjälä
> >
> > DP dual mode type 1 DVI adaptors aren't required to implement any
> > registers, so it's a bit hard to detect them. The b
I caught a few errors in our current PHY/CDCLK programming by sanity
checking the actual programmed state, so I thought it would be also
useful for the future. In addition to verifying the state after
programming it also verify it after exiting DC5, to make sure DMC
restored/kept intact everything
Library support has landed, please use a proper commit message so we can
add this (i.e., tests/kms_rotation_crc: )
On Mon, Mar 07, 2016 at 03:55:03PM +0530, Pratik Vishwakarma wrote:
> From: pvishwak
>
> Depends on:
> https://patchwork.freedesktop.org/patch/76040/
>
> Signed-off-by: P
== Series Details ==
Series: drm/i915/bxt: Fix/enable display power well support/runtime PM
URL : https://patchwork.freedesktop.org/series/5177/
State : failure
== Summary ==
CC [M] drivers/gpu/drm/i915/intel_dp_link_training.o
CC [M] drivers/gpu/drm/i915/intel_dp_mst.o
CC [M] drivers
Hi Dave,
drm-intel-next-2016-03-30:
- VBT code refactor for a clean split between parsing&using of firmware
information (Jani)
- untangle the pll computation code, and splitting up the monster
i9xx_crtc_compute_clocks (Ander)
- dsi support for bxt (Jani, Shashank Sharma and others)
- color man
On pe, 2016-04-01 at 16:29 +0300, Jani Nikula wrote:
> On Fri, 01 Apr 2016, Imre Deak wrote:
> > The power-down step logically belongs to the individual PHY uninit
> > sequence so move it there. The only functional change is that we
> > will
> > power down now PHY 1 separately before PHY 0 and pre
On Fri, 01 Apr 2016, Imre Deak wrote:
> The power-down step logically belongs to the individual PHY uninit
> sequence so move it there. The only functional change is that we will
> power down now PHY 1 separately before PHY 0 and preserve the other bits
> in the register which are defined as reser
Hi Dave,
I figured it's time to open 4.7, also because we need the DCS patches from
this pull in i915:
- First patch of uapi header alignment with libdrm.
- random small stuff all over.
There's a small trivial conflict in amdgpu with the dummy
vgacon_text_force patch.
Cheers, Daniel
The follow
I caught a few errors in our current PHY/CDCLK programming by sanity
checking the actual programmed state, so I thought it would be also
useful for the future. In addition to verifying the state after
programming it also verify it after exiting DC5, to make sure DMC
restored/kept intact everything
On SKL/KBL suspend-to-idle (aka freeze/s0ix) is performed with DMC
firmware assistance where the target display power state is DC6. On
Broxton on the other hand we don't use the firmware for this, but rely
instead on a manual DC9 flow. For this we have to uninitialize the
display following the BSpe
If BIOS has already programmed and enabled a PHY, don't reprogram it as
that may interfere with the currently active outputs. A follow-up patch
will add state verification, so we can catch any misconfiguration on
BIOS's behalf.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 40 +
This patchset works around/fixes a few DMC and PHY issues and enables
display power well support and runtime PM.
CC: Mika Kuoppala
CC: Patrik Jakobsson
CC: Matt Ropert
Imre Deak (16):
drm/i915/bxt: Reject DMC firmware versions with known bugs
drm/i915/bxt: Fix GRC code register field defin
This register is read-only, so we have never actually set
OCL2_LDOFUSE_PWR_DIS in it as specified by the specification. Add a code
comment about this. I filed a specification update request to clarify
this there.
CC: Arthur J Runyan
Signed-off-by: Imre Deak
---
[ Art, CC'ing you in case you kn
With the preceding fixes runtime PM should be functional, I could
runtime suspend/resume the device without problems.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm
The display power well support and DC state management doesn't depend on
runtime PM support, so remove the incorrect asserts about this.
Also Broxton does support DC5, so the related assert in
assert_can_enable_dc5() is incorrect. There is a more generic and
correct assert for this already in gen9
Power well 1 is managed by the DMC firmware so don't toggle it on-demand
from the driver. This means we need to follow the BSpec display
initialization sequence during driver loading and resuming (both system
and runtime) and enable power well 1 only once there. Afterwards DMC
will toggle power wel
DMC forces on power well 1 by setting the corresponding request bit both
in the BIOS and the DEBUG power well request register. This is somewhat
unexpected since the firmware should really just save and restore state
but not alter it. We also depend on being able to disable power well 1,
before ent
DMC version 1.06 has a known bug, where the firmware polls forever for a port
PLL to lock, if the PLL was disabled when entering DC5. Version 1.07 fixes
this, so make that the minimum required version on BXT.
CC: Mika Kuoppala
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_csr.c | 20 +
For internal APIs passing dev_priv is preferred to reduce indirections,
so convert over a few DDI PHY, CDCLK helpers.
No functional change.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_drv.c | 12
drivers/gpu/drm/i915/intel_ddi.c | 10 --
drivers/gpu/dr
So far we only power well enabling was synchronous not disabling. Since
we don't exactly know how the firmware (both DMC and PCU) synchronizes
against the actual power well state during DC transitions, make the
disabling also synchronous.
CC: Mika Kuoppala
CC: Patrik Jakobsson
Signed-off-by: Imr
The power-down step logically belongs to the individual PHY uninit
sequence so move it there. The only functional change is that we will
power down now PHY 1 separately before PHY 0 and preserve the other bits
in the register which are defined as reserved.
Signed-off-by: Imre Deak
---
drivers/gp
With the preceding fixes power well support should be functional on
Broxton, I could enter/exit DC5 without problems.
This reverts commit 18024199579882265653bfe9e2b1a3dcb5697cd9.
CC: Matt Roper
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 5 -
1 file changed, 5 d
On Broxton we need to enable/disable power well 1 during the init/unit display
sequence similarly to Skylake/Kabylake. The code for this will be added in a
follow-up patch, but to prepare for that unexport skl_pw1_misc_io_init(). It's
a simple function called only from a single place and having it
When determining whether CDCLK is enabled by BIOS and so we should skip
reprogramming it, we didn't check the related DBUF power request and
state. In theory BIOS could enable one without the other so check for
this case and reprogram things if something is amiss.
Signed-off-by: Imre Deak
---
dr
This has been corrected in BSpec quite some time ago, but we missed it
somehow. The wrong field definitions resulted in configuring PHY0 with
an incorrect GRC value.
CC: Arthur J Runyan
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_reg.h | 6 +++---
1 file changed, 3 insertions(+), 3 d
== Series Details ==
Series: Revert "drm/i915: Fix races on fbdev"
URL : https://patchwork.freedesktop.org/series/5173/
State : success
== Summary ==
Series 5173v1 Revert "drm/i915: Fix races on fbdev"
http://patchwork.freedesktop.org/api/1.0/series/5173/revisions/1/mbox/
Test kms_pipe_crc_ba
On pe, 2016-04-01 at 13:02 +0100, Chris Wilson wrote:
> On Fri, Apr 01, 2016 at 02:41:01PM +0300, Joonas Lahtinen wrote:
> >
> > This reverts commit a7442b93cf32c1e1ddb721a26cd1f92302e2a222.
> >
> > With the patch applied SNB, IVB and ILK are experiencing hard machine
> > hangs. Original patch wa
On Fri, Apr 01, 2016 at 02:41:01PM +0300, Joonas Lahtinen wrote:
> This reverts commit a7442b93cf32c1e1ddb721a26cd1f92302e2a222.
>
> With the patch applied SNB, IVB and ILK are experiencing hard machine
> hangs. Original patch was to fix "just" kernel panics so it's not a good
> trade-off.
>
> Pr
On Thu, 24 Mar 2016, Mika Kahola wrote:
> Housekeeping stuff.
>
> Reviewed-by: Mika Kahola
Thanks, pushed this one patch to drm-intel-next-queued.
BR,
Jani.
>
> On Fri, 2016-03-18 at 13:11 +0200, Jani Nikula wrote:
>> The DSI sequence blocks contain gpio index references, not actual gpio
>> nu
This reverts commit a7442b93cf32c1e1ddb721a26cd1f92302e2a222.
With the patch applied SNB, IVB and ILK are experiencing hard machine
hangs. Original patch was to fix "just" kernel panics so it's not a good
trade-off.
Proper fix for the panic is on the way, lets revert until then.
Fixes: a7442b93c
On 01/04/16 08:46, Joonas Lahtinen wrote:
According to Chris, use of i915_vm_to_ppgtt is visible in benchmark
unless WARN_ON is removed, so lets get rid of it.
Cc: Chris Wilson
Reported-by: Chris Wilson
Reviewed-by: Chris Wilson
Signed-off-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_
On pe, 2016-04-01 at 10:06 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: use for_each_port_masked in bxt phy init for
> clarity
> URL : https://patchwork.freedesktop.org/series/5165/
> State : failure
>
> == Summary ==
>
> Series 5165v1 drm/i915: use for_each_port_masked
Hello,
I saw that you did some work for LPSS PWM:
https://lists.freedesktop.org/archives/intel-gfx/2016-January/085006.html
I cannot find a tree where the patches can be applied and the kernel links
properly. I tried two:
5ba001783ba6451fd3db0259d30549ca1fe91870
1df59b8497f47495e873c23abd6d3d290c
Hi Boris,
From: Boris Brezillon [mailto:boris.brezil...@free-electrons.com]
Sent: Wednesday, March 30, 2016 10:04 PM
Subject: [PATCH v5 08/46] hwmon: pwm-fan: use pwm_get_args() where
appropriate
>
> The PWM framework has clarified the concept of reference PWM config (the
> platform dependent con
Hello,
I saw that you did some work for LPSS PWM:
https://lists.freedesktop.org/archives/intel-gfx/2016-January/085006.html
I cannot find a tree where the patches can be applied and the kernel links
properly. I tried two:
5ba001783ba6451fd3db0259d30549ca1fe91870
1df59b8497f47495e873c23abd6d3d290c
Hi Boris,
From: Boris Brezillon [mailto:boris.brezil...@free-electrons.com]
Sent: Wednesday, March 30, 2016 10:04 PM
Subject: [PATCH v5 35/46] hwmon: pwm-fan: switch to the atomic API
>
> pwm_config/enable/disable() have been deprecated and should be replaced
> by pwm_apply_state().
>
> Signed-o
== Series Details ==
Series: drm/i915: use for_each_port_masked in bxt phy init for clarity
URL : https://patchwork.freedesktop.org/series/5165/
State : failure
== Summary ==
Series 5165v1 drm/i915: use for_each_port_masked in bxt phy init for clarity
http://patchwork.freedesktop.org/api/1.0/s
Temporary fluke, they are there now. Nothing special, just dellxps not deciding
which suspend-read-crc-pipe it hangs this time.
Tomi
On Friday 01 April 2016 13:12:41 Imre Deak wrote:
> On pe, 2016-04-01 at 08:33 +, Patchwork wrote:
> > BOOT FAILED for snb-dellxps
> >
> > Results at /archi
On pe, 2016-04-01 at 08:33 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: BXT DDI PHY sequence BUN (rev3)
> URL : https://patchwork.freedesktop.org/series/4687/
> State : failure
>
> == Summary ==
>
> Series 4687v3 drm/i915: BXT DDI PHY sequence BUN
> http://patchwork.fre
On pe, 2016-04-01 at 10:26 +0300, Jani Nikula wrote:
> On Thu, 31 Mar 2016, Vandana Kannan wrote:
> > According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be
> > checked to ensure that the register is in accessible state.
> > Also, based on a BSpec update, changing the timeout
== Series Details ==
Series: Pre-calculate SKL-style atomic watermarks
URL : https://patchwork.freedesktop.org/series/5158/
State : warning
== Summary ==
Series 5158v1 Pre-calculate SKL-style atomic watermarks
http://patchwork.freedesktop.org/api/1.0/series/5158/revisions/1/mbox/
Test drv_mod
== Series Details ==
Series: drm/i915/hdmi: Fix weak connector detection
URL : https://patchwork.freedesktop.org/series/5151/
State : success
== Summary ==
Series 5151v1 drm/i915/hdmi: Fix weak connector detection
http://patchwork.freedesktop.org/api/1.0/series/5151/revisions/1/mbox/
Test drv
== Series Details ==
Series: drm/i915: BXT DDI PHY sequence BUN (rev3)
URL : https://patchwork.freedesktop.org/series/4687/
State : failure
== Summary ==
Series 4687v3 drm/i915: BXT DDI PHY sequence BUN
http://patchwork.freedesktop.org/api/1.0/series/4687/revisions/3/mbox/
Test drv_module_rel
On 04/01/2016 04:01 PM, Jani Nikula wrote:
On Fri, 01 Apr 2016, Rob Kramer wrote:
My setup is an embedded GM45 based board with a screen connected via 24
bit LVDS. When trying a to use a newer kernel (3.14.57) with KMS, the
screen stays blank. I'm only testing KMS so far, no X. Older, pre-KMS
v
On Mi, 2016-03-30 at 11:51 +0200, Daniel Vetter wrote:
> No need to confuse userspace like this.
Reviewed-by: Gerd Hoffmann
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Mi, 2016-03-30 at 11:51 +0200, Daniel Vetter wrote:
> Only really needed for fbdev emulation at 8bpp. And bochs doesn't do
> that. And either way bochs only does 32bit rgb, so this is all pretty
> much wasted dead code.
Pointless leftover when I copyed things over from cirrus.
Reviewed-by: Ger
== Series Details ==
Series: series starting with [1/2] drm/i915: Use i915_vm_to_ppgtt instead of
manual container_of
URL : https://patchwork.freedesktop.org/series/5141/
State : success
== Summary ==
Series 5141v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/51
On Fri, 2016-04-01 at 10:44 +0300, Jani Nikula wrote:
> Make it easier to see which ports are configured for each phy. No
> functional changes.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ander Conselvan de Oliveira
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 10 +++---
> 1 file changed, 7
On Fri, 01 Apr 2016, Rob Kramer wrote:
> My setup is an embedded GM45 based board with a screen connected via 24
> bit LVDS. When trying a to use a newer kernel (3.14.57) with KMS, the
> screen stays blank. I'm only testing KMS so far, no X. Older, pre-KMS
> versions of the kernel worked fine.
Hi Lukas,
Ran this patch through the farm, and it seems that this patch might've helped
HSW, maybe even BSW.
ILK, IVB and SNB are still hanging hard to the same igt-test,
kms_pipe_crc_basic@suspend-read-crc-pipe-?
I'll try to make a kernel with the changes you proposed, but as I'm not
familiar
On Fri, Apr 01, 2016 at 10:46:41AM +0300, Joonas Lahtinen wrote:
> Looks much better without container_of everywhere.
>
> v2:
> - In i915_gem_restore_gtt_mappings too (Chris)
>
> v3:
> - Do not cause WARN by calling on non PPGTT object (Chris)
>
> Cc: Daniel Vetter
> Cc: Chris Wilson
> Signed-
dev_priv is what the macro works hard to extract, pass it directly.
v2:
- Include all wrapper macros too (Chris)
v3:
- Include sed cmdline (Chris)
Cc: Chris Wilson
Reviwed-by: Chris Wilson
Signed-off-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c| 4 +--
drivers/gpu/drm
Looks much better without container_of everywhere.
v2:
- In i915_gem_restore_gtt_mappings too (Chris)
v3:
- Do not cause WARN by calling on non PPGTT object (Chris)
Cc: Daniel Vetter
Cc: Chris Wilson
Signed-off-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 44 ++--
According to Chris, use of i915_vm_to_ppgtt is visible in benchmark
unless WARN_ON is removed, so lets get rid of it.
Cc: Chris Wilson
Reported-by: Chris Wilson
Reviewed-by: Chris Wilson
Signed-off-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
1 file changed, 1 deletion(-)
d
Make it easier to see which ports are configured for each phy. No
functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_ddi.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
On Thu, 2016-03-31 at 12:38 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/5] drm/i915: Splitting intel_dp_detect
> URL : https://patchwork.freedesktop.org/series/5044/
> State : success
I pushed those to dinq.
I fixed a couple of "Alignment should match ope
== Series Details ==
Series: drm/i915: Avoid unnecessary full synchronize for fbdev
URL : https://patchwork.freedesktop.org/series/5125/
State : failure
== Summary ==
Series 5125v1 drm/i915: Avoid unnecessary full synchronize for fbdev
http://patchwork.freedesktop.org/api/1.0/series/5125/revis
On Thu, 31 Mar 2016, Vandana Kannan wrote:
> According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be
> checked to ensure that the register is in accessible state.
> Also, based on a BSpec update, changing the timeout value to
> check iphypwrgood, from 10ms to wait for up to 100
On Fri, Apr 01, 2016 at 10:05:04AM +0300, Joonas Lahtinen wrote:
> According to Chris, use of i915_vm_to_ppgtt is visible in benchmark
> unless WARN_ON is removed, so lets get rid of it.
>
> Cc: Chris Wilson
> Reported-by: Chris Wilson
> Signed-off-by: Joonas Lahtinen
Reviewed-by: Chris Wilson
On Fri, Apr 01, 2016 at 10:05:05AM +0300, Joonas Lahtinen wrote:
> dev_priv is what the macro works hard to extract, pass it directly.
>
> v2:
> - Include all wrapper macros too (Chris)
For posterity, inlucde your sed line here:
s/\([A-Z].*\)(dev_priv->dev)/\1(dev_priv)/g
> Cc: Chris Wilson
>
On pe, 2016-04-01 at 08:12 +0100, Chris Wilson wrote:
> On Fri, Apr 01, 2016 at 10:05:03AM +0300, Joonas Lahtinen wrote:
> >
> > Looks much better without container_of everywhere.
> >
> > v2:
> >
> > - In i915_gem_restore_gtt_mappings too (Chris)
> > @@ -3294,9 +3282,7 @@ void i915_gem_restore_g
On Fri, 01 Apr 2016, "Zanoni, Paulo R" wrote:
> Em Ter, 2016-02-23 às 18:46 +0200, ville.syrj...@linux.intel.com
> escreveu:
>> From: Ville Syrjälä
>>
>> DP dual mode type 1 DVI adaptors aren't required to implement any
>> registers, so it's a bit hard to detect them. The best way would
>> be to
On Fri, Apr 01, 2016 at 10:05:03AM +0300, Joonas Lahtinen wrote:
> Looks much better without container_of everywhere.
>
> v2:
> - In i915_gem_restore_gtt_mappings too (Chris)
> @@ -3294,9 +3282,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device
> *dev)
> list_for_each_entry(
According to Chris, use of i915_vm_to_ppgtt is visible in benchmark
unless WARN_ON is removed, so lets get rid of it.
Cc: Chris Wilson
Reported-by: Chris Wilson
Signed-off-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm
dev_priv is what the macro works hard to extract, pass it directly.
v2:
- Include all wrapper macros too (Chris)
Cc: Chris Wilson
Signed-off-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c| 4 +--
drivers/gpu/drm/i915/i915_drv.c| 4 +--
drivers/gpu/drm/i915/i9
Looks much better without container_of everywhere.
v2:
- In i915_gem_restore_gtt_mappings too (Chris)
Cc: Daniel Vetter
Cc: Chris Wilson
Signed-off-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 40 -
1 file changed, 13 insertions(+), 27 dele
On Thu, 31 Mar 2016, Imre Deak wrote:
> On to, 2016-03-31 at 19:47 +0300, Kannan, Vandana wrote:
>> > -Original Message-
>> > From: Deak, Imre
>> > Sent: Thursday, March 31, 2016 9:45 AM
>> > To: Kannan, Vandana ; intel-
>> > g...@lists.freedesktop.org
>> > Cc: Nikula, Jani
>> > Subject:
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