== Series Details ==
Series: drm/i915/bxt: add missing DSI power domain to power well 1
URL : https://patchwork.freedesktop.org/series/4223/
State : failure
== Summary ==
Series 4223v1 drm/i915/bxt: add missing DSI power domain to power well 1
http://patchwork.freedesktop.org/api/1.0/series/42
== Series Details ==
Series: SKL WM fixes and Arbitrated Display Bandwidth WA (rev3)
URL : https://patchwork.freedesktop.org/series/4197/
State : failure
== Summary ==
Series 4197v3 SKL WM fixes and Arbitrated Display Bandwidth WA
http://patchwork.freedesktop.org/api/1.0/series/4197/revisions/
We are procuring the DVI-single-link cable, as we don't have one with us.
Sonika tested the Dual link cable, and that was working well.
We can do two things here:
- Add the gen check, which will allow the live_status check only for VLV and +
platforms, others will go as it is.
- Wait for some
+Shashank
Shashank was planning to give a patch to bypass live status checks for older
platforms.
Regards,
Sonika
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Wednesday, March 9, 2016 2:34 AM
To: Jindal, Sonika
Cc: intel-gfx@lists.freedesktop.org
Subje
-Original Message-
From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com]
Sent: Wednesday, February 24, 2016 5:18 AM
To: Belgaumkar, Vinay ;
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH i-g-t] tests/gem_buffered_svm: Buffered SVM
tests
Hi,
On 10/02/16 18:01,
These tests were initially reviewed/merged under the gem_softpin title.
They use softpinning and userptr mechanism to share buffers between
CPU and GPU.
The userptr part was decoupled from them recently. Adding these tests
under a different name to ensure buffered SVM usage testing.
The only chan
From: Sagar Arun Kamble
GuC SLPC need to be sent data related to Active pipes, refresh rates,
widi pipes, fullscreen pipes related via host to GuC display mode
change event. Based on this, SLPC will track FPS on active pipes.
This patch defines the event and implements trigger of the event.
v2:
From: Tom O'Rourke
Do not merge until SKL guc ver6 is published.
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/intel_guc_loader.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
From: Tom O'Rourke
Adds debugfs hooks for each slpc task.
The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.
Each of these can take the values:
"default", "enabled", or "disabled"
v2: update for SLPC v2015.2.4
dfps and turbo merged and renamed "gt
From: Tom O'Rourke
v2: Add mutex lock/unlock
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_slpc.c | 5 +
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_
From: Tom O'Rourke
When frequency requests are made by SLPC, host driver
should not attempt to make frequency requests due to
potential conflicts.
Host-based turbo operations are already avoided when
SLPC is used. This change covers other frequency
requests such as from sysfs or debugfs interfa
From: Tom O'Rourke
i915_slpc_info shows the contents of SLPC shared data
parsed into text format.
v2: reformat slpc info (Radek)
squashed query task state info
in slpc info, kunmap before seq_print (Paulo)
return void instead of ignored return value (Paulo)
Signed-off-by: Tom O'Rour
From: Tom O'Rourke
Send SLPC shutdown event during disable, suspend, and reset
operations. Sending shutdown event while already shutdown
is OK.
v2: return void instead of ignored error code (Paulo)
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/intel_slpc.c | 28 +++
From: Tom O'Rourke
This patch is expected as part of another series
and is included for convenience in testing this
series.
Do not merge unless Broxton guc v5 firmware is available.
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++
1 file changed, 7 insertio
From: Tom O'Rourke
Adds has_slpc to broxton info and adds broxton to
version check. The SLPC interface version 2015.2.4
is found in Broxton Guc v5.
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 3 ++-
2 files changed, 3
From: Tom O'Rourke
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/intel_slpc.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h
b/drivers/gpu/drm/i915/intel_slpc.h
index 06f1b28..de2df0c 100644
--- a/drivers/gpu/drm/i915/i
From: Dave Gordon
DO NOT MERGE: This patch is added for convenience in
reviewing SLPC patch series. This patch should be
merged as part of a separate series to enable guc
submission by default.
v5:
Rebased
Signed-off-by: Dave Gordon
Acked-by: Tom O'Rourke
---
drivers/gpu/drm/i915/i915_p
From: Tom O'Rourke
If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.
v2: Use intel_slpc_enabled() (Paulo)
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/inte
From: Tom O'Rourke
When SLPC is controlling requested frequency, the rps.cur_freq
value is not used to make the frequency request.
Before using rps.cur_freq in sysfs or debugfs, read
requested frequency from register to get the value
most recently requested by SLPC firmware.
v2: replace HAS_SLP
From: Tom O'Rourke
Add slpc_param_id enum values.
Add events for setting/unsetting parameters.
v2: use host2guc_slpc
update slcp_param_id enum values for SLPC 2015.2.4
return void instead of ignored error code (Paulo)
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/intel_slpc.c |
From: Tom O'Rourke
This patch makes SLPC enabled by default on
platforms with hardware/firmware support.
DO NOT MERGE: This patch is added for convenience in
reviewing SLPC patch series. This patch should be
merged after validation results show benefits of using SLPC.
Signed-off-by: Tom O'Rour
From: Tom O'Rourke
Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.
v2: Update for SLPC 2015.2.4 (params for both slice and unslice)
Replace HAS_SLPC with intel_slpc_active() (Paulo)
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/i915_debugfs
From: Tom O'Rourke
SLPC shared data is used to pass information
to/from SLPC firmware.
For Skylake, platform sku type and slice count
are identified from device id and fuse values.
Support for other platforms needs to be added.
v2: Update for SLPC interface version 2015.2.4
intel_slpc_acti
From: Peter Antoine
This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory
spaces do not overlap.
DO NOT MERGE: This patch is expected as part of another
series and is included for convenience in testing this
series.
Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
Signe
From: Sagar Arun Kamble
v2: Cleaning up defines for number of pipes and other cosmetic changes.
Signed-off-by: Sagar Arun Kamble
Acked-by: Tom O'Rourke
---
drivers/gpu/drm/i915/intel_slpc.h | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915
From: Tom O'Rourke
Add host2guc SLPC reset event and send reset event
during enable.
v2: extract host2guc_slpc to handle slpc status code
coding style changes (Paulo)
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/intel_slpc.c | 33 -
drivers/gpu/drm/
From: Sagar Arun Kamble
This patch will inform GuC SLPC about changes in the refresh rate
due to Seamless DRRS. Refresh rate changes due to Static DRRS will
be notified via commit path.
v2: Rebased on previous changed patch and printed error message if
H2G action fails.
v2(torourke): Updates sug
From: Tom O'Rourke
i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.
slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
Interpretation of default value is based on HAS_SLPC(), after
slpc_version_chec
From: Tom O'Rourke
Expose host2guc_action for use by SLPC in intel_slpc.c.
Expose functions to allocate and release objects used
by GuC to be used for SLPC shared memory object.
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/i915_guc_submission.c | 6 +++---
drivers/gpu/drm/i915/intel_g
From: Tom O'Rourke
The SLPC interface has changed and could continue to
change. Only GuC versions known to be compatible are
supported here.
On Skylake, GuC firmware v6 is supported. Other
platforms and versions can be added here later.
This patch also adds has_slpc to skylake info.
Signed-o
From: Tom O'Rourke
Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC). SLPC is
a replacement for some host-based power management
features.
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
1 file changed, 2 insertions(+)
diff
From: Tom O'Rourke
On platforms with SLPC support: call intel_slpc_*()
functions from corresponding intel_*_gt_powersave()
functions; and do not use rps functions.
v2: return void instead of ignored error code (Paulo)
enable/disable RC6 in SLPC flows (Sagar)
replace HAS_SLPC() use with i
From: Tom O'Rourke
SLPC (Single Loop Power Controller) is a replacement for
some host-based power management features. The SLPC
implemenation runs in firmware on GuC.
This series has been tested with SKL guc firmware
version 6.1 and BXT guc version 5.1.
The graphics power management features i
Jordan Justen writes:
> Signed-off-by: Jordan Justen
Reviewed-by: Francisco Jerez
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
> b/drivers/gpu/drm/i915/i915_cmd_parser.c
> ind
Jordan Justen writes:
> This is needed for the Mesa Vulkan driver on Haswell.
>
> Signed-off-by: Jordan Justen
Reviewed-by: Francisco Jerez
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 16
> drivers/gpu/drm/i915/i915_reg.h| 4
> 2 files changed, 20 insertio
Jordan Justen writes:
> This is needed for the Mesa Vulkan driver on Haswell.
>
> Signed-off-by: Jordan Justen
> Cc: Kristian Høgsberg
> Cc: Kenneth Graunke
Reviewed-by: Francisco Jerez
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/
Jordan Justen writes:
> Now that we can whitelist registers only on Haswell, move HSW_SCRATCH1
> and HSW_ROW_CHICKEN3 into a separate Haswell only table.
>
> Signed-off-by: Jordan Justen
> Cc: Francisco Jerez
Reviewed-by: Francisco Jerez
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++
On Tue, Sep 15, 2015 at 09:44:20AM +0530, Sonika Jindal wrote:
> The Bspec is very clear that Live status must be checked about before
> trying to read EDID over DDC channel. This patch makes sure that HDMI
> EDID is read only when live status is up.
>
> The live status doesn't seem to perform ver
On Tue, Mar 08, 2016 at 09:00:56PM +0200, Jani Nikula wrote:
> The DSI power domain was missing from BXT power well 1 definitions,
> failing to get the power well for DSI transcoders. As pipe A is in the
> same power well as DSI transcoders, the problem should only occur with
> pipes B and C.
>
>
The DSI power domain was missing from BXT power well 1 definitions,
failing to get the power well for DSI transcoders. As pipe A is in the
same power well as DSI transcoders, the problem should only occur with
pipes B and C.
Cc: Ramalingam C
Cc: Deepak M
Signed-off-by: Jani Nikula
---
This sh
From: Shobhit Kumar
This is needed for WM computation workaround for arbitrated display
bandwidth.
v2: Address Matt's review comments
- Be more paranoid while dmi decoding
- Also add support for decoding speed from configured memory speed
if availble in DMI memory entry
v3 (by Mat
On Tue, Mar 08, 2016 at 08:49:23PM +0200, Ville Syrjälä wrote:
> On Mon, Mar 07, 2016 at 05:05:45PM -0800, Matt Roper wrote:
> > From: Shobhit Kumar
> >
> > This is needed for WM computation workaround for arbitrated display
> > bandwidth.
> >
> > v2: Address Matt's review comments
> > - Be
On Tue, Mar 08, 2016 at 07:57:12AM +, Patchwork wrote:
> == Series Details ==
>
> Series: SKL WM fixes and Arbitrated Display Bandwidth WA
> URL : https://patchwork.freedesktop.org/series/4197/
> State : failure
>
> == Summary ==
>
> Series 4197v1 SKL WM fixes and Arbitrated Display Bandwi
On Mon, Mar 07, 2016 at 05:05:45PM -0800, Matt Roper wrote:
> From: Shobhit Kumar
>
> This is needed for WM computation workaround for arbitrated display
> bandwidth.
>
> v2: Address Matt's review comments
> - Be more paranoid while dmi decoding
> - Also add support for decoding speed fr
A couple of the EDAC drivers have a nice memdev_dmi_entry structure for
decoding DMI memory device entries. Move the structure definition to
dmi.h so that it can be shared between those drivers and also other
parts of the kernel; the i915 graphics driver is going to need to use
this structure soon
On Thu, Mar 03, 2016 at 10:53:50AM -0600, Bjorn Helgaas wrote:
> The purpose of this series is to:
>
> - Fix the "BAR 6: [??? 0x flags 0x2] has bogus alignment"
> messages reported by Linus [1], Andy [2], and others.
>
> - Move arch-specific shadow ROM location knowledge, e.g.,
>
On Mon, Mar 07, 2016 at 11:47:51AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Wait until after wm optimization to drop runtime PM
> reference
> URL : https://patchwork.freedesktop.org/series/4135/
> State : failure
>
> == Summary ==
>
> Series 4135v1 drm/i915: Wait u
I think it would be more idiomatic to replace:
+ for (i = 0; i < display->n_outputs; i++) {
+ igt_output_t *output = &display->outputs[i];
with:
+ for_each_connected_output(display, output)
And:
+ for (i = 0; i < pipe->n_planes; i++) {
+ igt_plane_t *plane = &pipe->pl
== Series Details ==
Series: Shared pll improvements (rev4)
URL : https://patchwork.freedesktop.org/series/3850/
State : warning
== Summary ==
Series 3850v4 Shared pll improvements
http://patchwork.freedesktop.org/api/1.0/series/3850/revisions/4/mbox/
Test kms_flip:
Subgroup basic-fli
Hi Maarten,
Yeah that would be much simpler I think.
Damien also looked at this patch over my shoulder and had additional
comments.
So more or less proxying :
- Not sure why we're exposing the new enums and the
igt_atomic_popuplate_* macros in igt_kms.h.
After all we're not using them any
Op 07-03-16 om 13:50 schreef Lionel Landwerlin:
> Hi Pratik,
>
> I'm really looking forward to get this merged.
> Just a few comments on the plane commit part below.
Would the following diff to the patch satisfy you? It would clean up things a
lot.
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
inde
Move shared dpll function prototype together with other shared dpll
definitions.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_dpll_mgr.h | 30 ++
drivers/gpu/drm/i915/intel_drv.h | 28
2 files changed, 30
Create the new file intel_dpll_mgr.c and move the shared dpll code to
it. Follow up patches that reorganize pll handling will move more code
there and tweak the interface.
No functional changes.
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_display.c | 348 +--
Include DPLL0 in the managed dplls for SKL/KBL. While it has to be kept
enabled because of it driving CDCLK, it is better to special case that
inside the DPLL code than in the higher level.
v2: Use INTEL_DPLL_ALWAYS_ON flag. (Ander)
v3: Remove extremely paranoid WARN_ONs. (Maarten)
Handle DPL
Manage the LCPLLs used with DisplayPort, so that all the HSW/BDW DPLLs
are managed by the shared dpll code.
v2: Introduce INTEL_DPLL_ALWAYS_ON flag to please state checker. (Ander)
v3: Initialize pll->flags in intel_shared_dpll_init(). (Ander)
Signed-off-by: Ander Conselvan de Oliveira
---
dr
No functional changes.
---
drivers/gpu/drm/i915/intel_ddi.c | 472 --
drivers/gpu/drm/i915/intel_dpll_mgr.c | 472 ++
drivers/gpu/drm/i915/intel_drv.h | 1 -
3 files changed, 472 insertions(+), 473 deletions(-)
diff --git
Move the code for selecting and configuring HSW/BDW DDI PLLs into the
shared dpll infrastructure. With this most of the PLL selection logic
for those platforms is in one place. DisplayPort is handled separately,
but that should be fixed on a follow up patch. It also allows a small
clean up of the S
Make the code neater by splitting the code for platforms with fixed PLL
to their own functions and splitting the logic for finding a shareable
or unused pll from the logic for setting it up.
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 109 +++---
1 file changed, 74 inse
Change the type of intel_crtc_state->shared_dpll to be a pointer to a
shared dpll. With this there is no need to first convert the id stored
in the crtc state to a pointer in order to use it. It does introduce a
bit of hassle on doing the opposite.
The long term objective is to hide details about
Use a table to store the per-platform shared dpll information in one
place. This way, there is no need for platform specific init funtions.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 16 +--
drivers/gpu/drm/i915/intel_dpll_mgr.c | 189 +++
Move the code for configurating BXT plls into the shared dpll code, so
that the platform specific details are hidden behind that interface.
Signed-off-by: Ander Conselvan de Oliveira
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_ddi.c | 141 +---
The function intel_get_shared_dpll() had a more or less generic
implementation with some platform specific checks to handle smaller
differences between platforms. However, the minimalist approach forces
bigger differences between platforms to be implemented outside of the
shared dpll code (see the
Move the declarations related to shared dplls from i915_drv.h to their
own header file.
The code that became the shared dpll infrastructre was first introcude
in commit ee7b9f93fd96 ("drm/i915: manage PCH PLLs separately from
pipes"), hence the 2012-2016 copyright years in the new header file.
Si
Here's an updated patch series with Maarten's comments addressed. The
last two patches also have fixes to please the state checker.
Thanks,
Ander
Ander Conselvan de Oliveira (13):
drm/i915: Move shared dpll code to a new file
drm/i915: Move ddi shared dpll code to intel_dpll_mgr.c
drm/i915:
Move the code for selecting plls for SKL/KLB into the shared dpll code,
so that the platform specific details are hidden behind that interface.
Signed-off-by: Ander Conselvan de Oliveira
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_ddi.c | 301 +---
So they don't cause unrelated subtests to be skipped when testing
drivers other than i915.
Signed-off-by: Tomeu Vizoso
---
Changes in v2: None
tests/kms_addfb_basic.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/tests/kms_addfb_basic.c b/tests/kms_addfb_basic.c
Move tests requiring tiled BOs to the end so they don't cause unrelated
subtests to be skipped when testing drivers with only dumb buffer
support.
Signed-off-by: Tomeu Vizoso
---
Changes in v2: None
tests/kms_addfb_basic.c | 50 -
1 file changed,
Which basically just calls DRM_IOCTL_MODE_MAP_DUMB and is similar to
gem_mmap__gtt().
Signed-off-by: Tomeu Vizoso
---
Changes in v2:
- Add helper kmstest_dumb_map_buffer as suggested by Daniel Vetter
lib/igt_kms.c | 16
lib/igt_kms.h | 3 +++
2 files changed, 19 insertions(+)
Because determining the Intel GFX generation requires a call to
DRM_IOCTL_I915_GETPARAM, move the code that requires it to a subtest
that can be skipped on drivers other than i915.
Signed-off-by: Tomeu Vizoso
---
Changes in v2: None
tests/kms_addfb_basic.c | 36 +++-
Because calls to gem_set_tiling will cause the subtest to be skipped on
drivers other than i915, move them to each subtest that needs them so
the other subtests aren't skipped as well.
Signed-off-by: Tomeu Vizoso
---
Changes in v2: None
tests/kms_addfb_basic.c | 8
1 file changed, 4 i
Many tests can do their work on drivers other than i915 and even with
just dumb buffers, so call igt_create_bo_with_dimensions instead of
gem_create which will paper out the differences and call the proper
ioctls or cause the subtest to be skipped if that's not possible.
Signed-off-by: Tomeu Vizos
For those tests that now pass on drivers other than i915, call
drm_open_driver_master with DRIVER_ANY.
Also do so from igt_enable_connectors.
Signed-off-by: Tomeu Vizoso
---
Changes in v2: None
lib/igt_kms.c | 2 +-
tests/drm_read.c| 2 +-
tests/kms_addfb_basic.c | 2 +-
tes
I915_PARAM_CHIPSET_ID is a i915-only thing, so if a subtest ends up
calling it when testing another driver, let's skip it.
Signed-off-by: Tomeu Vizoso
---
Changes in v2: None
lib/intel_chipset.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/intel_chipset.c b/lib/intel_chipset.c
ind
In order to test drivers that don't have support for proper buffer
objects, add a wrapper for creating dumb buffer objects that will be
called from the lib code for those subtests that don't need to care.
Signed-off-by: Tomeu Vizoso
---
Changes in v2:
- Rename dumb_create to kmstest_dumb_create
As it reflects more clearly what the function actually does.
Suggested-by: Chris Wilson
Signed-off-by: Tomeu Vizoso
---
Changes in v2: None
lib/drmtest.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/lib/drmtest.c b/lib/drmtest.c
index 7b2227fe0f6a..b00f423d53
Lib and test code can use this function to avoid i915-specific behavior
when running on other drivers.
Signed-off-by: Tomeu Vizoso
---
Changes in v2: None
lib/drmtest.c | 2 +-
lib/drmtest.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/lib/drmtest.c b/lib/drmtest.c
ind
igt_create_bo_with_dimensions() is intended to abstract differences
between drivers in buffer object creation.
The driver-specific ioctls will be called if the driver that is being
tested can satisfy the needs of the calling subtest, or it will be
skipped otherwise.
Signed-off-by: Tomeu Vizoso
-
If a buffer object is dumb, call DRM_IOCTL_MODE_MAP_DUMB when mapping
it. Also, don't call DRM_IOCTL_I915_GEM_SET_DOMAIN on dumb buffers.
Signed-off-by: Tomeu Vizoso
---
Changes in v2:
- Call dirtyfb after the cairo context associated to a FB backed by a
dumb buffer is destroyed. For this, I n
Add function that requires that the driver we are talking to is i915.
This allows us to skip subtests that are specific to that driver.
Signed-off-by: Tomeu Vizoso
---
Changes in v2:
- Rename is_intel to has_known_intel_chipset as suggested by Chris
Wilson.
lib/drmtest.c | 5 +
lib/drmt
Before calling a i915-specific IOCTL, require i915.
This allows us to skip subtests that are specific to that driver, though
what should eventually happen is that tests don't generally call
gem_set_tiling directly but go through an abstraction layer that
constructs the buffer object in a driver-sp
Just wraps drmModeDirtyFB and for now invalidates the whole FB.
Signed-off-by: Tomeu Vizoso
---
Changes in v2:
- Add igt_dirty_fb
lib/igt_fb.c | 14 ++
lib/igt_fb.h | 1 +
2 files changed, 15 insertions(+)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index f936961a484f..9d6cff0edd23
It only makes sense when testing the i915 driver, so don't call it
otherwise.
Signed-off-by: Tomeu Vizoso
---
Changes in v2: None
lib/igt_fb.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 7b535560033d..f936961a484f 100644
---
Hi,
have restarted work on getting tests in IGT to run on drivers other than
i915.
These changes make the modified tests pass in a Radxa Rock2 board by
using dumb buffers as much as possible and having subtests skip if they
require tiled BOs. The plan is for igt_create_bo_with_dimensions to be
ab
On Tue, Mar 08, 2016 at 10:57:16AM +0100, Maarten Lankhorst wrote:
> The raw watermark values are needed when planes are not part of the state,
> but this introduced a regression and possibly an overflow when merging
> the watermarks because invalid values may end up used. Solve this by
> calculat
On 08/03/2016 12:58, Tvrtko Ursulin wrote:
On 25/02/16 17:52, Arun Siluvery wrote:
On 11/01/2016 09:16, Chris Wilson wrote:
Migrate the request operations out of the main body of i915_gem.c and
into their own C file for easier expansion.
v2: Move __i915_add_request() across as well
Signed-of
On Mon, Mar 07, 2016 at 04:49:14PM -0800, O'Rourke, Tom wrote:
> On Mon, Mar 07, 2016 at 08:57:09PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Read out the RPS frequencies already in intel_init_gt_powersave()
> > on all the platforms. So far we only did that on VL
On 11/01/16 09:16, Chris Wilson wrote:
If we move the release of the GEM request (i.e. decoupling it from the
various lists used for client and context tracking) after it is complete
(either by the GPU retiring the request, or by the caller cancelling the
request), we can remove the requirement
On Tue, Mar 08, 2016 at 12:13:22PM +, Daniel Stone wrote:
> Hi,
>
> On 8 March 2016 at 11:45, Rob Bradford wrote:
> > On Fri, 2016-02-26 at 17:04 +, Lionel Landwerlin wrote:
> >> This series introduces pipe level color management through a set of
> >> properties
> >> attached to the CRTC.
On 25/02/16 17:52, Arun Siluvery wrote:
On 11/01/2016 09:16, Chris Wilson wrote:
Migrate the request operations out of the main body of i915_gem.c and
into their own C file for easier expansion.
v2: Move __i915_add_request() across as well
Signed-off-by: Chris Wilson
---
don't we lose the
On Tue, Mar 08, 2016 at 11:08:18AM +, Tvrtko Ursulin wrote:
> Well strictly speaking you don't need to do any platform matrix
> testing for an r-b. :) But yes, the situation you are seeing on BSW
> needs to be resolved.
As discussed on IRC, it does seem to be unreproducible on !bsw (the
presum
Hi Matt,
On Mon, 7 Mar 2016 17:05:44 -0800, Matt Roper wrote:
> A couple of the EDAC drivers have a nice memdev_dmi_entry structure for
> decoding DMI memory device entries. Move the structure definition to
> dmi.h so that it can be shared between those drivers and also other
> parts of the kern
On Fri, Mar 04, 2016 at 03:29:03PM +0200, Ville Syrjälä wrote:
> On Thu, Mar 03, 2016 at 10:17:42AM +0100, Maarten Lankhorst wrote:
> > connector_state->crtc can no longer be unset by accident,
> > so that check can be removed. The other code open-codes
> > drm_atomic_get_existing_crtc_state, so us
== Series Details ==
Series: Reset GuC and retry on fw load failure (rev2)
URL : https://patchwork.freedesktop.org/series/3985/
State : warning
== Summary ==
Series 3985v2 Reset GuC and retry on fw load failure
http://patchwork.freedesktop.org/api/1.0/series/3985/revisions/2/mbox/
Test kms_fl
Hi,
On 8 March 2016 at 11:45, Rob Bradford wrote:
> On Fri, 2016-02-26 at 17:04 +, Lionel Landwerlin wrote:
>> This series introduces pipe level color management through a set of
>> properties
>> attached to the CRTC. It also provides an implementation for some
>> Intel
>> platforms.
>> > Thi
On 08/03/16 10:42, Lionel Landwerlin wrote:
On 08/03/16 02:46, Matt Roper wrote:
On Thu, Feb 25, 2016 at 05:16:08PM +, Lionel Landwerlin wrote:
Hi,
This series enables testing pipe level color management using kernel patches
from this serie :
https://patchwork.freedesktop.org/series/2720/
Hey,
On 5 March 2016 at 12:30, Daniel Vetter wrote:
> On Wed, Mar 02, 2016 at 03:00:15PM +0100, Tomeu Vizoso wrote:
>> +int igt_create_bo_with_dimensions(int fd, int width, int height,
>
> Needs gtkdoc. Also this seems to overlap in functionality with the very
> recently added igt_calc_fb_size. C
On Fri, 2016-02-26 at 17:04 +, Lionel Landwerlin wrote:
> This series introduces pipe level color management through a set of
> properties
> attached to the CRTC. It also provides an implementation for some
> Intel
> platforms.
> > This series is based of a previous set of patches by Shashank S
Due to timing issues in the HW some of the status bits required for GuC
authentication doesn't get set occassionally, when that happens, GuC cannot
be initialized and we will be left with a wedged GPU. The WA suggested is
to perform a soft reset of GuC and attempt to reload the fw again for few
tim
Below changes add a mechanism to reset GuC and retry fw loading if the
initial load fails. There are cetain HW issues because of which fw load can
fail and the WA is to retry after resetting GuC.
A patch required for engine reset is partially reused as we use that
function to reset guc.
v2: used
Partial port of a patch from Mika that modifies reset function to handle
per engine resets. A domain reset function is introduces which accepts a
mask of all domains to be reset. In case of per engine reset only single
engine domain is specified where as for legacy full gpu reset all engine
domain
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