Jordan Justen <jordan.l.jus...@intel.com> writes: > Now that we can whitelist registers only on Haswell, move HSW_SCRATCH1 > and HSW_ROW_CHICKEN3 into a separate Haswell only table. > > Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> > Cc: Francisco Jerez <curroje...@riseup.net>
Reviewed-by: Francisco Jerez <curroje...@riseup.net>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
> b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 46ea40b..ba01836 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -472,6 +472,9 @@ static const struct drm_i915_reg_descriptor
> gen7_render_regs[] = {
> REG32(GEN7_L3SQCREG1),
> REG32(GEN7_L3CNTLREG2),
> REG32(GEN7_L3CNTLREG3),
> +};
> +
> +static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
> REG32(HSW_SCRATCH1,
> .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
> .value = 0),
> @@ -519,6 +522,7 @@ static const struct drm_i915_reg_table
> ivb_blt_reg_tables[] = {
>
> static const struct drm_i915_reg_table hsw_render_reg_tables[] = {
> { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
> + { hsw_render_regs, ARRAY_SIZE(hsw_render_regs), false },
> { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
> };
>
> --
> 2.7.0
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