In some cases, we just need one valid output to perform a test.
This macro can help in these situations by avoiding iterating
over all the outputs.
Suggested-by: Matt Roper
CC: Tvrtko Ursulin
CC: Matt Roper
Signed-off-by: Vivek Kasireddy
---
lib/igt_kms.h| 5 +
tests/kms_rotat
The main goal of this subtest is to trigger the following warning in
the function i915_gem_object_get_fence():
if (WARN_ON(!obj->map_and_fenceable))
To trigger this warning, the subtest first creates a Y-tiled object and
an associated framebuffer with the Y-fb modifier. Furthermore, to
pre
While pinning a fb object to the display plane, only install a fence
if the object is using a normal view. This corresponds with the
behavior found in i915_gem_object_do_pin() where the fencability
criteria is determined only for objects with normal views.
v2:
Look at the object's map_and_fenceabl
On Wed, Sep 23, 2015 at 01:27:12PM +0200, Maarten Lankhorst wrote:
> Make pinning and waiting a separate step, and wait for object idle
> without struct_mutex held.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 -
> drivers/gpu/drm/i915/i915_gem.c
On Wed, Sep 23, 2015 at 01:27:11PM +0200, Maarten Lankhorst wrote:
> Only acquire the struct_mutex once, and interruptibly.
>
> Signed-off-by: Maarten Lankhorst
Your headline/commit message seem a bit sparse here...you may want to
make it clear that this refers to framebuffer preparation/cleanup
From: Animesh Manna
As during disabling dc6 no need to check for csr firmware
loading status, so removed the assert call (Requested by Damien).
Cc: Damien Lespiau
Signed-off-by: Animesh Manna
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 1 -
1 file changed, 1 deletion
From: Daniel Vetter
Grabbing a runtime pm reference with intel_runtime_pm_get will only
prevent device D3. But dmc firmware is required even earlier (namely
for the skl power well 2).
Hence we need to grab a rpm reference higher up in the hierarchy. For
simplicity just grab the _INIT display pow
From: Daniel Vetter
Standard is to align continuations of parameter lists and if
conditions to the opening ( in i915 and drm code.
Apply this across the entire file since it was sticking out a bit too
much.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signe
This is a rebased version of [1], addressing the review comments. It
depends on Mika's FW version blacklisting/capture patchset [2].
I have added my Reviewed-by to those patches that I only rebased or
updated the commit message, patches 1,4,12 have changes from me, so
someone else would need to re
From: Daniel Vetter
Avoids non-static functions since all the callers are in intel_rpm.c.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
[imre: removed note about reg definitions from commit message, since
it's not relevant any m
From: Daniel Vetter
The loader function will get a bit more complicated soon, extract the
parsing code to make the control flow clearer. While doing that just
use dev_priv->csr.dmc_payload as the indicator for whether it all
suceeded or not.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
S
From: Animesh Manna
During driver unload to ensure we dont have any pending task,
flush_work added to complete firmware loading task.
v1: Initial version.
v2: As per review comments from Daniel,
Removed flush_work from skl_set_power_well. As we have taken
power well refernece and rpm count duri
From: Daniel Vetter
Two benefits:
- We can use FW_LOADER_USERSPACE_FALLBACK.
- We can use flush_work to synchronize with the oustanding worker,
which is a notch more obvious what it does than having a special
completion.
The next patch will properly synchronize against the async loader in
th
From: Daniel Vetter
We need to make sure we don't put garbage into the hw if dmc firmware
loading failed mid-thru.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
Currently during system s/r we enable/disable DC6, so before we do so
make sure that the firmware loading is complete.
Note that whether we need to enable DC6 for S3/S4 is still open. At
least the firmware program is lost during S3 and we need to reprogram it
after resuming. Until this is clarifi
From: Animesh Manna
Skl is fully dependent on dmc for going to low power state (dc5/dc6).
This requires a trigger from rpm. To ensure the dmc firmware
is available for runtime pm support rpm-reference-count is used
by not releasing the rpm reference if firmware loading is
not completed.
So moved
From: Daniel Vetter
This removes two anti-patterns:
- Locking shouldn't be used to synchronize with async work (of any
form, whether callbacks, workers or other threads). This is what the
mutex_lock/unlock seems to have been for in intel_csr_load_program.
Instead ordering should be ensured
From: Daniel Vetter
As all csr firmware related opertion are not using any
any data structures of drm framework level, so better to
use dev_priv instead of dev. it's a new style! :)
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
R
From: Daniel Vetter
If we really want to we can be more verbose here, but we really don't
need an entire function for this.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/i915_drv.
On 09/30/2015 07:36 AM, Yetunde Adebisi wrote:
> This patch adds support for eDP backlight control using DPCD registers to
> backlight hooks in intel_panel.
>
> It checks for backlight control over AUX channel capability and sets up
> function pointers to get and set the backlight brightness level
On Wed, Oct 28, 2015 at 12:44:30PM -0700, Rodrigo Vivi wrote:
> On Wed, Oct 28, 2015 at 12:31 PM, Chris Wilson
> wrote:
> > On Wed, Oct 28, 2015 at 04:16:45AM -0700, Rodrigo Vivi wrote:
> >
> >> +static const struct intel_device_info intel_kabylake_info = {
> >> + .is_preliminary = 1,
> >> +
On Wed, 28 Oct 2015, Rodrigo Vivi wrote:
> From: Deepak S
>
> v2: (Rodrigo) Rebase after commit 3cb27f38f
> ("drm/i915: remove an extra level of indirection in PCI ID list")
>
> Cc: Jani Nikula
> Reviewed-by: Damien Lespiau
> Signed-off-by: Deepak S
> Signed-off-by: Damien Lespiau
> Signe
On Wed, Oct 28, 2015 at 12:31 PM, Chris Wilson wrote:
> On Wed, Oct 28, 2015 at 04:16:45AM -0700, Rodrigo Vivi wrote:
>
>> +static const struct intel_device_info intel_kabylake_info = {
>> + .is_preliminary = 1,
>> + .is_kabylake = 1,
>> + .gen = 9,
>> + .num_pipes = 3,
>> + .n
On Wed, Oct 28, 2015 at 12:32 PM, Jani Nikula wrote:
> On Wed, 28 Oct 2015, Rodrigo Vivi wrote:
>> I like this idea, but a small complain is that we had already 2
>> reviewed patches at the mailing list waiting to get merged that
>> conflicted with this one.
>
> I was aware of the conflict but fa
On Wed, Oct 28, 2015 at 04:16:45AM -0700, Rodrigo Vivi wrote:
> +static const struct intel_device_info intel_kabylake_info = {
> + .is_preliminary = 1,
> + .is_kabylake = 1,
> + .gen = 9,
> + .num_pipes = 3,
> + .need_gfx_hws = 1, .has_hotplug = 1,
> + .ring_mask = RENDER_R
On Wed, 28 Oct 2015, Rodrigo Vivi wrote:
> I like this idea, but a small complain is that we had already 2
> reviewed patches at the mailing list waiting to get merged that
> conflicted with this one.
I was aware of the conflict but failed to see they were reviewed already
and thought you needed
I like this idea, but a small complain is that we had already 2 reviewed
patches at the mailing list waiting to get merged that conflicted with this one.
Please, next time consider merging the already reviewed patches that
touches same part before merging so quickly a patch like this.
On Wed, Oct
From: Deepak S
v2: (Rodrigo) Rebase after commit 3cb27f38f
("drm/i915: remove an extra level of indirection in PCI ID list")
Cc: Jani Nikula
Reviewed-by: Damien Lespiau
Signed-off-by: Deepak S
Signed-off-by: Damien Lespiau
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.c
From: Deepak S
v2: separate out device info into different GT (Damien)
v3: Add is_kabylake to the KBL gt3 structuer (Damien)
Sort the platforms in older -> newer order (Damien)
v4: Split platform definition since is_skylake=1 on
kabylake structure was Nacked. (Rodrigo)
v5: (Rodrigo) Reb
On Wed, 28 Oct 2015, Rodrigo Vivi wrote:
> Kabylake is a Intel® Processor containing Intel® HD Graphics
> following Skylake.
>
> It is Gen9p5, so it inherits everything from Skylake.
>
> Let's start by adding the platform separated from Skylake
> but reusing most of all features, functions etc. La
Kabylake is a Intel® Processor containing Intel® HD Graphics
following Skylake.
It is Gen9p5, so it inherits everything from Skylake.
Let's start by adding the platform separated from Skylake
but reusing most of all features, functions etc. Later we
rebase the PCI-ID patch without is_skylake=1
so
On Wed, 28 Oct 2015, Jani Nikula wrote:
> Add the PCI IDs directly in the pciidlist array instead of defining an
> extra macro. The minor benefit from this is neater diffs when adding to
> the end of the list.
>
> v2: drop the "aka" comment (Ville)
>
> Reviewed-by: Ville Syrjälä
> Signed-off-by:
On Wed, Oct 28, 2015 at 05:24:18PM +, Zanoni, Paulo R wrote:
> Em Ter, 2015-10-27 às 20:29 +, Chris Wilson escreveu:
> > On Tue, Oct 27, 2015 at 02:50:25PM -0200, Paulo Zanoni wrote:
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index a9434
Add the PCI IDs directly in the pciidlist array instead of defining an
extra macro. The minor benefit from this is neater diffs when adding to
the end of the list.
v2: drop the "aka" comment (Ville)
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.c | 73
Em Ter, 2015-10-27 às 20:29 +, Chris Wilson escreveu:
> On Tue, Oct 27, 2015 at 02:50:25PM -0200, Paulo Zanoni wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index a9434d1..fdbe068 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/driv
On Wed, Oct 28, 2015 at 04:56:39PM +, Zanoni, Paulo R wrote:
> Em Ter, 2015-10-27 às 20:32 +0200, Ville Syrjälä escreveu:
> > On Tue, Oct 27, 2015 at 02:50:04PM -0200, Paulo Zanoni wrote:
> > > The hardware already takes care of disabling and recompressing FBC
> > > when we do a page flip, so a
On 23/10/15 12:46, Mika Kuoppala wrote:
Chris Wilson writes:
On Fri, Oct 23, 2015 at 02:07:35PM +0300, Mika Kuoppala wrote:
Chris Wilson writes:
Having flushed all requests from all queues, we know that all
ringbuffers must now be empty. However, since we do not reclaim
all space when ret
On 28 October 2015 at 11:29, David Weinehall
wrote:
> Some tests should not be run by default, due to their slow,
> and sometimes superfluous, nature.
>
> We still want to be able to run these tests in some cases.
> Until now there's been no unified way of handling this. Remedy
> this by introduci
On Wed, 28 Oct 2015, Ville Syrjälä wrote:
> On Wed, Oct 28, 2015 at 01:57:09PM +0200, Jani Nikula wrote:
>> Although we don't support or enable CPU PWM with LPT/SPT based systems,
>> it may have been enabled prior to loading the driver. Disable the CPU
>> PWM on LPT/SPT backlight disable to avoid
On ke, 2015-10-28 at 16:52 +0100, Patrik Jakobsson wrote:
> On Tue, Oct 27, 2015 at 08:41:31PM +0200, Imre Deak wrote:
> > On pe, 2015-10-23 at 11:41 +0200, Patrik Jakobsson wrote:
> > > The current CSR loading code depends on the CSR program memory to be
> > > cleared after boot. This is unfortuna
On Wed, Oct 28, 2015 at 06:38:21PM +0200, Jani Nikula wrote:
> > Are you seeing a bug? it's totally possible, I've never used an actual
> > conformance tool when I wrote that code, so it's likely buggy and the
> > VIC in the AVI infoframe may well be wrong.
>
> Possibly relevant
> https://bugs.fre
Em Ter, 2015-10-27 às 19:50 +, Chris Wilson escreveu:
> On Tue, Oct 27, 2015 at 02:50:04PM -0200, Paulo Zanoni wrote:
> > @@ -1021,13 +1078,48 @@ void intel_fbc_flush(struct
> > drm_i915_private *dev_priv,
> > if (origin == ORIGIN_GTT)
> > return;
> >
> > + /* Hardware track
Em Ter, 2015-10-27 às 20:32 +0200, Ville Syrjälä escreveu:
> On Tue, Oct 27, 2015 at 02:50:04PM -0200, Paulo Zanoni wrote:
> > The hardware already takes care of disabling and recompressing FBC
> > when we do a page flip, so all we need to do is to update the fence
> > registers and move on.
> >
>
On Wed, Oct 28, 2015 at 01:57:09PM +0200, Jani Nikula wrote:
> Although we don't support or enable CPU PWM with LPT/SPT based systems,
> it may have been enabled prior to loading the driver. Disable the CPU
> PWM on LPT/SPT backlight disable to avoid warnings on LCPLL disable.
>
> The issue has be
On Wed, 28 Oct 2015, Damien Lespiau wrote:
> On Wed, Oct 28, 2015 at 01:58:55PM +, Sharma, Shashank wrote:
>>Hi Damien
>>
>>This is regarding one of the patches:
>>drm: Add support for alternate clocks of 4k modes
>>(3f2f653378112c1453c0d83c81746a9225e4bc75)
>>
>>I am see
2015-10-28 9:29 GMT-02:00 David Weinehall :
> Some tests should not be run by default, due to their slow,
> and sometimes superfluous, nature.
>
> We still want to be able to run these tests in some cases.
> Until now there's been no unified way of handling this. Remedy
> this by introducing the --
On Tue, Oct 27, 2015 at 08:41:31PM +0200, Imre Deak wrote:
> On pe, 2015-10-23 at 11:41 +0200, Patrik Jakobsson wrote:
> > The current CSR loading code depends on the CSR program memory to be
> > cleared after boot. This is unfortunately not true on all hardware.
> > Instead make use of the FW_UNIN
On 28/10/15 13:01, John Harrison wrote:
On 27/07/2015 14:00, Tvrtko Ursulin wrote:
[snip]
+if (!sync_fence) {
+put_unused_fd(fd);
+*fence_fd = -1;
+return -ENOMEM;
+}
+
+sync_fence_install(sync_fence, fd);
+*fence_fd = fd;
+
+// Necessary??? Who do
On Wed, Oct 28, 2015 at 01:58:55PM +, Sharma, Shashank wrote:
>Hi Damien
>
>This is regarding one of the patches:
>drm: Add support for alternate clocks of 4k modes
>(3f2f653378112c1453c0d83c81746a9225e4bc75)
>
>I am seeing that from function drm_match_hdmi_mode we are not
Hi Damien
This is regarding one of the patches:
drm: Add support for alternate clocks of 4k modes
(3f2f653378112c1453c0d83c81746a9225e4bc75)
I am seeing that from function drm_match_hdmi_mode we are not returning correct
VIC's for 4k modes (listed in edid_4k_modes[])
Looks like we are returning
On 28/10/15 13:00, John Harrison wrote:
On 23/07/2015 15:25, Tvrtko Ursulin wrote:
Hi,
On 07/17/2015 03:31 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The request structure is reference counted. When the count reached
zero, the request was immediately freed and all associated
On 27/07/2015 14:00, Tvrtko Ursulin wrote:
On 07/17/2015 03:31 PM, john.c.harri...@intel.com wrote:
From: John Harrison
Various projects desire a mechanism for managing dependencies between
work items asynchronously. This can also include work items across
complete different and independent sy
On 27/07/2015 12:33, Tvrtko Ursulin wrote:
Hi,
On 07/17/2015 03:31 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The intended usage model for struct fence is that the signalled
status should be
set on demand rather than polled. That is, there should not be a need
for a
'signaled
On 23/07/2015 15:25, Tvrtko Ursulin wrote:
Hi,
On 07/17/2015 03:31 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The request structure is reference counted. When the count reached
zero, the request was immediately freed and all associated objects
were unrefereced/unallocated. This
Have finally had some time to come back to this and respond
to/incorporate the comments made some while ago...
On 23/07/2015 14:50, Tvrtko Ursulin wrote:
Hi,
On 07/17/2015 03:31 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The fence object used inside the request structure requ
On Wed, Oct 28, 2015 at 01:54:10PM +0200, Jani Nikula wrote:
> Add the PCI IDs directly in the pciidlist array instead of defining an
> extra macro. The minor benefit from this is neater diffs when adding to
> the end of the list.
>
> Signed-off-by: Jani Nikula
I was tempted to do this mysefl a
On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote:
> I managed to split out all the cleanup stuff upfront, but there is quite a bit
> of it. I did include a few random patches no strictly needed, but as long as I
> was going through the register macros I tried to fix whatever was wrong.
Ple
On Tue, 27 Oct 2015, John Doe wrote:
> On 27/10/2015 10:40, Jani Nikula wrote:
>> On Tue, 27 Oct 2015, Kai Huang wrote:
>>> I got below Call Trace when booting my 4.3.0-rc3+ kernel on my SKL DT
>>> machine. Although my machine boots up despite this call trace, I think
>>> it's better to report
From: Ankitprasad Sharma
A call to i915_gem_obj_ggtt_pin is being made after this, which again
calls the get_pages function. Hence removing the redundant call to
get_pages.
Signed-off-by: Ankitprasad Sharma
---
drivers/gpu/drm/i915/i915_guc_submission.c | 5 -
1 file changed, 5 deletions(-
Although we don't support or enable CPU PWM with LPT/SPT based systems,
it may have been enabled prior to loading the driver. Disable the CPU
PWM on LPT/SPT backlight disable to avoid warnings on LCPLL disable.
The issue has been present on BDW since BDW enabling, but was recently
introduced on HS
Add the PCI IDs directly in the pciidlist array instead of defining an
extra macro. The minor benefit from this is neater diffs when adding to
the end of the list.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.c | 71 -
1 file changed, 34 in
On Thu, 2015-10-08 at 12:02 +0100, Chris Wilson wrote:
> On Thu, Oct 08, 2015 at 11:54:29AM +0530, ankitprasad.r.sha...@intel.com
> wrote:
> > + /* stolen objects are already pinned to prevent shrinkage */
> > + memset(&node, 0, sizeof(node));
> > + ret = drm_mm_insert_node_in_range_generic(
On Tue, 27 Oct 2015, Rodrigo Vivi wrote:
> Kabylake is a Intel® Processor containing Intel® HD Graphics
> following Skylake.
>
> It is Gen9p5, so it inherits everything from Skylake.
>
> First version adding PCI IDs was also defining the platform
> with is_skylake=1. But this was bringing even mor
On Thu, 2015-10-08 at 14:56 +0100, Tvrtko Ursulin wrote:
> Hi,
>
> On 08/10/15 07:24, ankitprasad.r.sha...@intel.com wrote:
> > From: Ankitprasad Sharma
> >
> > This patch adds support for extending the pread/pwrite functionality
> > for objects not backed by shmem. The access will be made throug
When gem_concurrent_blit was converted to use the new common framework
for choosing whether or not to include slow/combinatorial tests,
gem_concurrent_all became superfluous. This patch removes it.
Signed-off-by: David Weinehall
---
tests/.gitignore |1 -
tests/Makefile.sources
Some tests should not be run by default, due to their slow,
and sometimes superfluous, nature.
We still want to be able to run these tests in some cases.
Until now there's been no unified way of handling this. Remedy
this by introducing the --all option to igt_core,
and use it in gem_concurrent_bl
Until now we've had no unified way to handle slow/combinatorial tests.
Most of the time we don't want to run slow/combinatorial tests, so this
should remain the default, but when we do want to run such tests,
it has been handled differently in different tests.
This patch adds an --all command line
We'll both rename gem_concurrent_all over gem_concurrent_blit
and change gem_concurrent_blit in this changeset. To make
this easier to follow we first do the the rename.
Signed-off-by: David Weinehall
---
tests/gem_concurrent_blit.c | 1116 ++-
1 file chan
On 27/10/15 18:58, Ville Syrjälä wrote:
On Tue, Oct 27, 2015 at 06:47:19PM +, Chris Wilson wrote:
On Tue, Oct 27, 2015 at 08:35:36PM +0200, Ville Syrjälä wrote:
On Tue, Oct 27, 2015 at 06:03:52PM +, Chris Wilson wrote:
On Tue, Oct 27, 2015 at 02:26:55PM +, Tvrtko Ursulin wrote:
Automated test data that is updated when a test is requested is not cleared
till next automated test request is recevied which can cause various
problems. This patch fixes this by clearing this during the next
short pulse and on hot unplug.
For example, when TEST_LINK_TRAINING is requested it is u
On tis, 2015-10-27 at 17:31 +, Chris Wilson wrote:
> On Tue, Oct 27, 2015 at 04:49:49PM +0100, Robert Fekete wrote:
> > +static const char *plane_rotation(unsigned int rotation)
> > +{
> > + static char buf[48];
> > + /*
> > +* According to doc only one DRM_ROTATE_ is allowed but this
>
On Tue, 27 Oct 2015, Rodrigo Vivi wrote:
> Kabylake will also be defined as gen9 and !is_skylake.
> So we need start by creating a proper Broxton
> definition, otherwise we will break broxton with the
> introduction of Kabylake.
>
> Signed-off-by: Rodrigo Vivi
Reviewed-by: Jani Nikula
> ---
>
On Tue, Oct 27, 2015 at 07:29:39PM +0200, Ville Syrjälä wrote:
> On Tue, Oct 27, 2015 at 08:58:17AM +0200, David Weinehall wrote:
> > On Fri, Oct 23, 2015 at 12:39:31PM -0700, Jesse Barnes wrote:
> > > On 10/22/2015 01:35 PM, ville.syrj...@linux.intel.com wrote:
> > > > From: Ville Syrjälä
> > > >
On Tue, Oct 27, 2015 at 10:02:09AM -0700, Jesse Barnes wrote:
> > Depending on what the hardware supports, for hibernate to disk there's ipmi
> > power-on.
> >
> > ipmi-power -h $hostname --stat will show the status of the machine,
> > ipmi-power -h $hostname --on will power it on.
> >
> > Maybe
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