Dear,
I would like to hardcode the safe watermark value for BDW for some tests and
don't care about power,
Do you have a safe watermark value at hand so that I can give a try?
Thanks
William
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in:
drivers/gpu/drm/i915/i915_irq.c
between commit:
4e3d1e26c2b2 ("drm/i915: Pass hpd_status_i915[] to intel_get_hpd_pins() in
pre-g4x")
from Linus' tree and commit:
58f2cf241fb9 ("drm/i915: Don't call intel_get_hpd_
tree: git://anongit.freedesktop.org/drm-intel drm-intel-nightly
head: 7738abac2b4564d3e4dfac769054dde326fbcafb
commit: a50fc26383859d01caa8f886b611fdeb86946757 [3/5] Merge remote-tracking
branch 'origin/topic/drm-misc' into drm-intel-nightly
config: i386-allnoconfig (attached as .config)
repro
tree: git://anongit.freedesktop.org/drm-intel topic/drm-misc
head: 28cc504e8d52248962f5b485bdc65f539e3fe21d
commit: bbb1e52402b2a288b09ae37e8182599931c7e9df [33/35] drm/fb-helper: atomic
restore_fbdev_mode()..
reproduce: make htmldocs
All warnings (new ones prefixed by >>):
Warning(driver
On Fri, Sep 11, 2015 at 01:55:22PM +0200, Patrik Jakobsson wrote:
> We need to be able to control if DC6 is allowed or not. Much like
> requesting power to a specific piece of the hardware we need to be able
> to request that we don't enter DC6 during certain hw access.
>
> To solve this without i
On 9/14/2015 1:16 PM, Daniel Vetter wrote:
On Fri, Sep 11, 2015 at 12:36:24AM +0530, Animesh Manna wrote:
On 9/10/2015 8:15 PM, Daniel Vetter wrote:
On Thu, Sep 10, 2015 at 01:58:54AM +0530, Animesh Manna wrote:
On 9/2/2015 2:24 PM, Daniel Vetter wrote:
On Wed, Aug 26, 2015 at 07:40:54PM +
On 09/14/2015 02:30 AM, Maarten Lankhorst wrote:
> + if (!crtc_state->connectors_changed &&
> + !crtc_state->active_changed &&
> + crtc_state->active &&
> + intel_pipe_config_compare(state->dev,
> +
On 09/14/2015 02:30 AM, Maarten Lankhorst wrote:
> The scaler_id in intel_pipe_config_compare should not be checked
> when adjusting in intel_pipe_config_compare. The hw scaler id may
> be changed in intel_update_pipe_config.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/inte
From: Ville Syrjälä
Finally managed to dig up enough hints as to where the stolen
reserved stuff lives on ctg/elk. So add the code to decode it.
This was a combination of old chipset specs, diggin up an old
elk grits release with an ctg/elk AubLoad etc.
This was only tested on an elk as I don't
On Wed, Sep 16, 2015 at 11:06:59PM +0530, Shashank Sharma wrote:
> From: Kausal Malladi
>
> The DRM color management framework is targeting various hardware
> platforms and drivers. Different platforms can have different color
> correction and enhancement capabilities.
>
> A commom user space ap
On Wed, Sep 16, 2015 at 11:06:58PM +0530, Shashank Sharma wrote:
> From: Kausal Malladi
>
> Color Management is an extension to Kernel display framework. It allows
> abstraction of hardware color correction and enhancement capabilities by
> virtue of DRM properties.
>
> This patch initializes co
On Wed, 16 Sep 2015 09:03:33 +0100
Chris Wilson wrote:
> On Tue, Sep 15, 2015 at 07:05:12PM -0700, Vivek Kasireddy wrote:
> > While pinning a fb object to the display plane, only install a fence
> > if the object is using a normal view. This corresponds with the
> > behavior found in i915_gem_obj
BDW/SKL/BXT platforms support various Gamma correction modes
which are:
1. Legacy 8-bit mode
2. 10-bit mode
3. 10-bit Split Gamma mode
4. 12-bit mode
This patch does the following:
1. Adds the core function to program Gamma correction values
for BDW/SKL/BXT platforms
2. Adds Gamma correction ma
BDW/SKL/BXT supports Degamma color correction feature, which
linearizes the non-linearity due to gamma encoded color values.
This will be applied before Color Transformation.
This patch does the following:
1. Adds the core function to program DeGamma correction values for
BDW/SKL/BXT platform
2
From: Kausal Malladi
This patch adds atomic set property interface for Intel CRTC. This
interface will be used for set operation on any DRM properties.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/intel_atomic.c | 9 +
drivers/gpu/drm/i915/int
DRM color manager allows the driver to showcase its best color
correction capabilities using the cm_crtc_palette_capabilities_property.
This patch adds no of coefficitents for degamma color correction
modes possible in CHV, in device info structure, which is:
CGM Degamma(10 bit, CGM HW unit):- 65
From: Kausal Malladi
This patch create new files intel_color_manager.c which
will contain the core color correction code for I915 driver
and its header intel_color_manager.h
The per color property patches coming up in this patch series
will fill the appropriate functions in this file.
Signed-of
The color correction blob values are loaded during set_property
calls. This patch adds a function to find the blob and apply the
correction values to the display registers, during the atomic
commit call.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/intel
Function intel_attach_color_properties_to_crtc attaches a
color property to its CRTC object. This patch calls this
function from crtc initialization sequence.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_
From: Kausal Malladi
Color Manager framework defines a color correction property for color
space transformation and Gamut mapping. This property is called CTM (Color
Transformation Matrix).
This patch adds a new structure in DRM layer for CTM.
This structure can be used by all user space agents
DRM color manager allows the driver to showcase its best color
correction capabilities using the cm_crtc_palette_capabilities_property.
Driver loads the no. of coefficients for various color correction
as per the platform, during the init time.
This patch adds no of coefficitents for best gamma co
I915 color manager registers pipe gamma correction as palette
correction after CTM property.
For BDW and higher platforms, split gamma correction is the best
gamma correction. This patch adds the no of coefficients(512) for
split gamma correction as "num_samples_after_ctm" parameter in device
info
CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into CGM (Color Gamut Mapping) registers.
This patch does the following:
1. Attaches CSC property to CRTC
2. Adds the core function to program CSC correction values
3. Adds CSC correction macros
Signed-of
I915 color manager registers pipe degamma correction as palette
correction before CTM, DRM property.
This patch adds the no of coefficients(65) for degamma correction
as "num_samples_before_ctm" parameter in device info structures,
for BDW and higher platforms.
Signed-off-by: Shashank Sharma
---
This patch adds set_property and get_property handlers for pipe
level CSC color correction for CHV/BSW platform. The set
function just attaches the CSC blob to CRTC state, that later
gets committed using atomic path.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/d
I915 driver registers gamma correction as palette correction
property with DRM layer. This patch adds set_property() and get_property()
handlers for pipe level gamma correction.
The set function attaches the Gamma correction blob to CRTC state, these
values will be committed during atomic commit.
DRM color manager contains these color properties:
1. "crtc_palette_capabilities_property": to allow a
core driver to load and showcase its color correction
capabilities to user space.
2. "ctm": Color transformation matrix property, where a
color transformation matrix of 9 correction values gets
a
CHV/BSW supports DeGamma color correction, which linearizes all
the non-linear color values. This will be applied before Color
Transformation.
This patch does the following:
1. Attach deGamma property to CRTC
2. Add the core function to program DeGamma correction values for
CHV/BSW platform
2.
From: Kausal Malladi
CHV/BSW platform supports two different pipe level gamma
correction modes, which are:
1. Legacy 8-bit mode
2. 10-bit CGM (Color Gamut Mapping) mode
This patch does the following:
1. Attaches Gamma property to CRTC
3. Adds the core Gamma correction function for CHV/BSW
4. Add
This patch adds set_property and get_property handlers for deGamma
color correction capability at Pipe level.
Set function just attaches the deGamma correction blob to CRTC state, which
will be later committed in the atomic commit path.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Mallad
From: Kausal Malladi
This patch adds atomic get property interface for Intel CRTC. This
interface will be used for get operation on any non-core DRM properties.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/intel_atomic.c | 9 +
drivers/gpu/drm
From: Kausal Malladi
The DRM color management framework is targeting various hardware
platforms and drivers. Different platforms can have different color
correction and enhancement capabilities.
A commom user space application can query these capabilities using the
DRM property interface. Each d
From: Kausal Malladi
This patch adds new variables in CRTC state, to hold respective color
correction blobs. These blobs will be required during the atomic commit
for writing the color correction values in correction registers.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
From: Kausal Malladi
This patch adds new structures in DRM layer for Palette color
correction.These structures will be used by user space agents
to configure appropriate number of samples and Palette LUT for
a platform.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
include/
From: Kausal Malladi
Color Management is an extension to Kernel display framework. It allows
abstraction of hardware color correction and enhancement capabilities by
virtue of DRM properties.
This patch initializes color management framework by :
1. Introducing new pointers in DRM mode_config st
This patch set adds Color Manager implementation in DRM layer. Color Manager
is an extension in DRM framework to support color correction/enhancement.
Various Hardware platforms can support several color correction capabilities.
Color Manager provides abstraction of these capabilities and allows a
2015-09-14 14:16 GMT-03:00 Daniel Vetter :
> On Mon, Sep 14, 2015 at 09:35:42PM +0530, Sagar Arun Kamble wrote:
>> Shared frontbuffer bits are causing warnings when same FB is displayed
>> in another plane without clearing the bits from previous plane.
>>
>> v2: Removing coversion of fb bits to 64
2015-09-14 16:34 GMT-03:00 :
> From: Ville Syrjälä
>
> Finally managed to dig up enough hints as to where the stolen
> reserved stuff lives on ctg/elk. So add the code to decode it.
> This was a combination of old chipset specs, diggin up an old
> elk grits release with an ctg/elk AubLoad etc.
>
Use the new debug info in the intel_crtc struct in these functions
rather than passing them as args.
v2: move min/max assignment back above first trace call (Ville)
use scanline from crtc->debug rather than fetching a new one (Ville)
Requested-by: Ville Syrjälä
Signed-off-by: Jesse Barnes
-
On Mon, Sep 14, 2015 at 8:22 AM, Daniel Vetter wrote:
> Hi Dave,
>
> -rc1 is out the door and here's my first pull request for drm-next. It's
> all over:
> - better atomic helpers for runtime pm drivers
> - atomic fbdev
David Herrmann just pointed out to me that atomic fbdev isn't actually
in thi
This allows multiple subtests to be specified using standard wildcard
characters when using the --run-subtest command line option.
Signed-off-by: Thomas Wood
---
lib/igt_core.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index 129476c..59
On Tue, 15 Sep 2015, Geliang Tang wrote:
> Fix the following 'make htmldocs' warnings:
>
> .//drivers/gpu/drm/i915/i915_gem_gtt.c:758: warning: No description found
> for parameter 'length'
> .//drivers/gpu/drm/i915/i915_gem_gtt.c:818: warning: No description found
> for parameter 'length'
>
On Tue, 15 Sep 2015, Geliang Tang wrote:
> Fix the following 'make htmldocs' warnings:
>
> .//drivers/gpu/drm/i915/intel_lrc.c:780: warning: No description found for
> parameter 'req'
> .//drivers/gpu/drm/i915/intel_lrc.c:780: warning: Excess function parameter
> 'request' description in 'in
On Thu, 10 Sep 2015, Deepak M wrote:
> Currently the iomap for VBT works only if the size of the
> VBT is less than 6KB, but if the size of the VBT exceeds
> 6KB than the physical address and the size of the VBT to
> be iomapped is specified in the mailbox3 and is iomapped
> accordingly.
>
> v2: -
On Wed, Sep 16, 2015 at 02:48:37PM +0530, Gaurav K Singh wrote:
> Hi,
>
> These patches enable DSI dual link mode on BXT boards. These set of patches
> build on top of the floated DSI Video mode patches on BXT (Uma's patches).
BTW I posted a few DSI related patch. Maybe you can take a look?
http
Op 14-09-15 om 21:43 schreef ville.syrj...@linux.intel.com:
> From: Ville Syrjälä
>
> Collect the timestamping constants alongside the rest of the relevant
> stuff under drm_vblank_crtc.
>
> We can now get rid of the 'refcrtc' parameter to
> drm_calc_vbltimestamp_from_scanoutpos().
>
> Signed-off-
On Wed, Sep 16, 2015 at 02:48:41PM +0530, Gaurav K Singh wrote:
> Program the required mmio regs for hactive and vactive display size.
This doesn't program anything, just reads them out.
As for readout, do the pipe registers contain the same values? In that
case we could just do a sanity check to
On Wed, Sep 16, 2015 at 02:48:39PM +0530, Gaurav K Singh wrote:
> Earlier, pclk was getting used for calculating DSI clk. For single link
> MIPI panels, it will work fine. But for dual link MIPI, since pclk gets
> halved, DSI clk will have a wrong value.
Shouldn't we then do pclk*!!dual_link. pclk
Op 27-08-15 om 17:36 schreef ville.syrj...@linux.intel.com:
> From: Ville Syrjälä
>
> Restructure intel_dp_check_mst_status() to be more straightforward to
> read.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_dp.c | 92
> +
> 1 file
On Wed, Sep 16, 2015 at 02:48:38PM +0530, Gaurav K Singh wrote:
> Enable BIT 0 of MIPI Port Ctrl reg to enable dual link mode.
>
> Signed-off-by: Deepak M
> Signed-off-by: Gaurav K Singh
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h |7 ---
> drivers/gpu/drm/i91
On Fri, 11 Sep 2015, libin.y...@intel.com wrote:
> From: Libin Yang
>
> When modeset occurs and the TMDS frequency is set to some
> speical values, the N/CTS need to be set manually if audio
> is playing.
>
> Signed-off-by: Libin Yang
> ---
> drivers/gpu/drm/i915/intel_audio.c | 56
> ++
On ke, 2015-09-16 at 09:17 +0100, Chris Wilson wrote:
> On Tue, Sep 15, 2015 at 09:30:20PM +0300, Imre Deak wrote:
> > The execlist context object is mapped with a CPU/GPU coherent mapping
> > everywhere, but on BXT A stepping due to a HW issue the coherency is not
> > guaranteed. To work around th
Hey,
Op 27-08-15 om 17:36 schreef ville.syrj...@linux.intel.com:
> From: Ville Syrjälä
>
> I'm not a fan of deeply nested ifs. Just pull most of the conditions
> into a single place to flatten things a bit.
I like flat..
Reviewed-by: Maarten Lankhorst
___
Hey,
Op 03-09-15 om 14:11 schreef Ville Syrjälä:
> On Thu, Aug 27, 2015 at 06:36:48PM +0300, ville.syrj...@linux.intel.com wrote:
>> From: Ville Syrjälä
>>
>> Grab the connection_mutex around MSR link retraining to protect it
>> against a concurrent modeset. We already do the same for SST.
>>
>>
Hi Jani,
>-Original Message-
>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>Sent: Wednesday, September 16, 2015 3:18 PM
>To: R, Durgadoss; intel-gfx@lists.freedesktop.org
>Cc: R, Durgadoss
>Subject: Re: [RFC DP-typeC 0/2] Support USB typeC based DP on BXT
>
>On Tue, 15 Sep 2015,
On Tue, 15 Sep 2015, Lucas Tanure wrote:
> Hi,
>
> I would like to start to contribute to drm part of kernel. I tried a few
> things:
>
> - Compiled linux-next tree using C=1 (sparse) to find things to improve.
> But couldn't find any problem or issue.
> - I looked in "www.x.org/wiki/DRMJanitors/"
On Wed, Sep 16, 2015 at 11:50:50AM +0200, Michał Winiarski wrote:
> According to bspec, some parts of HW expect the addresses to be in
> a canonical form where bits [63:48] == [47].
> If we're using 32b addressing, we never need to handle such high
> addresses, but since we've recently added 48b ad
It would be initialized just moments later by i915_init_vm.
v2: Commit msg update,
s/i915_init_vm/i915_address_space_init, move to i915_gem_gtt.c,
init address_space during i915_gem_setup_global_gtt for ggtt.
v3: Do not init global_link - we are adding it to vm_list moments later,
make
According to bspec, some parts of HW expect the addresses to be in
a canonical form where bits [63:48] == [47].
If we're using 32b addressing, we never need to handle such high
addresses, but since we've recently added 48b address space support,
lets satisfy the HW by converting the address prior t
On Tue, 15 Sep 2015, Durgadoss R wrote:
> This is an RFC series to start the review/discussion on approach
> to support USB type C based DP panel.
>
> To support USB type C alternate DP mode, the display driver needs to
> know the number of lanes required by the DP panel as well as number
> of lan
Fix the following 'make htmldocs' warnings:
.//drivers/gpu/drm/i915/i915_gem_gtt.c:758: warning: No description found for
parameter 'length'
.//drivers/gpu/drm/i915/i915_gem_gtt.c:818: warning: No description found for
parameter 'length'
.//drivers/gpu/drm/i915/i915_gem_gtt.c:818: warning:
Fix the following 'make htmldocs' warnings:
.//drivers/gpu/drm/i915/intel_audio.c:439: warning: No description found for
parameter 'intel_encoder'
.//drivers/gpu/drm/i915/intel_audio.c:439: warning: Excess function parameter
'encoder' description in 'intel_audio_codec_disable'
.//drivers/g
Fix the following 'make htmldocs' warnings:
.//drivers/gpu/drm/i915/i915_gem.c:1729: warning: No description found for
parameter 'vma'
.//drivers/gpu/drm/i915/i915_gem.c:1729: warning: No description found for
parameter 'vmf'
.//drivers/gpu/drm/i915/i915_gem.c:4962: warning: No descriptio
Fix the following 'make htmldocs' warnings:
.//drivers/gpu/drm/i915/intel_lrc.c:780: warning: No description found for
parameter 'req'
.//drivers/gpu/drm/i915/intel_lrc.c:780: warning: Excess function parameter
'request' description in 'intel_logical_ring_begin'
.//drivers/gpu/drm/i915/int
Enable BIT 0 of MIPI Port Ctrl reg to enable dual link mode.
Signed-off-by: Deepak M
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_reg.h |7 ---
drivers/gpu/drm/i915/intel_dsi.c |9 ++---
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/
Program the required mmio regs for hactive and vactive display size.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_display.c | 37 ++
1 file changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel
Earlier, pclk was getting used for calculating DSI clk. For single link
MIPI panels, it will work fine. But for dual link MIPI, since pclk gets
halved, DSI clk will have a wrong value.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi_pll.c |4 +++-
1 file changed, 3 insertion
Hi,
These patches enable DSI dual link mode on BXT boards. These set of patches
build on top of the floated DSI Video mode patches on BXT (Uma's patches).
Regards
Gaurav
Gaurav K Singh (4):
drm/i915: Enable dual link mode in BXT
drm/i915: Use adjusted mode clk for calculating DSI clk
drm/i
Before setting the MIPI device to ready state, execute the RESET
sequence.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi.c |2 ++
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 15 +++
include/drm/drm_panel.h|9 +
3 fil
On Tue, 2015-09-15 at 16:14 +0100, Tvrtko Ursulin wrote:
> On 09/15/2015 09:33 AM, ankitprasad.r.sha...@intel.com wrote:
> > From: Chris Wilson
> >
> > If we run out of stolen memory when trying to allocate an object, see if
> > we can reap enough purgeable objects to free up enough contiguous fre
On Tue, Sep 15, 2015 at 09:30:20PM +0300, Imre Deak wrote:
> The execlist context object is mapped with a CPU/GPU coherent mapping
> everywhere, but on BXT A stepping due to a HW issue the coherency is not
> guaranteed. To work around this flush the CPU cache after any change
> from the CPU to the
On Tue, Sep 15, 2015 at 07:05:12PM -0700, Vivek Kasireddy wrote:
> While pinning a fb object to the display plane, only install a fence
> if the object is using a normal view. This corresponds with the
> behavior found in i915_gem_object_do_pin() where the fencability
> criteria is determined only
When diagnosing a unrelated bug for someone on irc, it would seem the hardware
can
be brought up by the BIOS with the embedded displayport using the SPLL for
spread spectrum.
Right now this is not handled well in i915, and it calculates the crtc needs to
be reprogrammed on the first modeset with
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