On Wed, Jun 17, 2015 at 04:19:22PM +0100, Peter Antoine wrote:
> This change adds the programming of the MOCS registers to the gen 9+
> platforms. This change set programs the MOCS register values to a set
> of values that are defined to be optimal.
>
> It creates a fixed register set that is prog
On Thu, Jun 18, 2015 at 07:42:10AM +0200, Maarten Lankhorst wrote:
> Op 18-06-15 om 03:48 schreef Matt Roper:
> > On Mon, Jun 15, 2015 at 12:33:43PM +0200, Maarten Lankhorst wrote:
> >> It's easier to read separate functions for crtc and plane scaler state.
> >>
> >> Changes since v1:
> >> - Updat
On Thu, 18 Jun 2015, Edgardo Gho wrote:
> Hi,
> I have an AIO computer with a Pegatron BYT-T1 motherboard. Looks like a
> cheap motherboard (using J1900).
> It has an innolux 1366x768 panel (LVDS). The Motherboard also has LVDS
> written on the connector.
> I'm running kernel 4.0.5 on it (tinyco
On Thu, Jun 18, 2015 at 06:08:46AM +, Jindal, Sonika wrote:
> Looks good to me.
> Reviewed-by: Sonika Jindal
>
> > -Original Message-
> > From: Kannan, Vandana
> > Sent: Thursday, June 18, 2015 11:01 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Jindal, Sonika; Kannan, Vandana
>
On Wed, Jun 17, 2015 at 06:37:03PM +0100, Chris Wilson wrote:
> On Wed, Jun 17, 2015 at 05:03:19PM +0200, Daniel Vetter wrote:
> > On Wed, Jun 17, 2015 at 01:53:17PM +0100, Chris Wilson wrote:
> > > On Wed, Jun 17, 2015 at 02:49:47PM +0200, Daniel Vetter wrote:
> > > > On Wed, Jun 10, 2015 at 07:09
Looks good to me.
Reviewed-by: Sonika Jindal
> -Original Message-
> From: Kannan, Vandana
> Sent: Thursday, June 18, 2015 11:01 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Jindal, Sonika; Kannan, Vandana
> Subject: [PATCH v5] drm/i915/bxt: eDP Panel Power sequencing
>
> Changes for BX
Hi Dave, i915 fixes for drm-next/v4.2.
BR,
Jani.
The following changes since commit bf546f8158e2df2656494a475e6235634121c87c:
drm/i915/skl: Fix DMC API version in firmware file name (2015-06-05 12:08:01
+0300)
are available in the git repository at:
git://anongit.freedesktop.org/drm-int
Hi Dave, final i915 fixes for v4.1.
BR,
Jani.
The following changes since commit 0f57d86787d8b1076ea8f9cba2a46d534a27:
Linux 4.1-rc8 (2015-06-14 15:51:10 -1000)
are available in the git repository at:
git://anongit.freedesktop.org/drm-intel tags/drm-intel-fixes-2015-06-18
for you to
Op 18-06-15 om 03:48 schreef Matt Roper:
> On Mon, Jun 15, 2015 at 12:33:43PM +0200, Maarten Lankhorst wrote:
>> It's easier to read separate functions for crtc and plane scaler state.
>>
>> Changes since v1:
>> - Update documentation.
>> Changes since v2:
>> - Get rid of parameters to skl_update
Changes for BXT - added a IS_BROXTON check to use the macro related to PPS
registers for BXT.
BXT does not have PP_DIV register. Making changes to handle this.
Second set of PPS registers have been defined but will be used when VBT
provides a selection between the 2 sets of registers.
v2:
[Jani] A
Jani,
On Mon, Jun 15, 2015 at 02:40:42PM +0300, Jani Nikula wrote:
> On Mon, 15 Jun 2015, Ville Syrjälä wrote:
> > On Mon, Jun 15, 2015 at 01:25:38AM -0700, Jeremiah Mahler wrote:
> >> Daniel,
> >>
> >> On Mon, Jun 15, 2015 at 08:57:47AM +0200, Daniel Vetter wrote:
> >> > Can you please retest w
On Mon, Jun 15, 2015 at 12:33:46PM +0200, Maarten Lankhorst wrote:
> By passing crtc_state to the check_plane functions a lot of duplicated
> code can be removed. There are still some transitional helper calls,
> they will be removed later.
>
> Changes since v1:
> - Revert state->visible changes.
On Mon, Jun 15, 2015 at 12:33:43PM +0200, Maarten Lankhorst wrote:
> It's easier to read separate functions for crtc and plane scaler state.
>
> Changes since v1:
> - Update documentation.
> Changes since v2:
> - Get rid of parameters to skl_update_scaler only used for traces.
>This avoids n
On Wed, 2015-06-10 at 11:59 +0100, Chris Wilson wrote:
>
> sudo perf record -g -a -c 1 -e i915:i915_gem_request_wait_begin is
> likely to capture the culprit. Though to be precise you need to look at
> wait_begin + wait_end to measure the stall (some waits are more harmless
> than others). As a fi
On 17/06/2015 21:21, Chris Wilson wrote:
On Wed, Jun 17, 2015 at 07:48:16PM +0100, Siluvery, Arun wrote:
On 16/06/2015 21:25, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 08:25:20PM +0100, Arun Siluvery wrote:
+static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
+
Hi,
I have an AIO computer with a Pegatron BYT-T1 motherboard. Looks like a
cheap motherboard (using J1900).
It has an innolux 1366x768 panel (LVDS). The Motherboard also has LVDS
written on the connector.
I'm running kernel 4.0.5 on it (tinycore custom kernel) and xrandr
displays the port as e
2015-06-17 17:25 GMT-03:00 Chris Wilson :
> On Wed, Jun 17, 2015 at 04:39:32PM -0300, Paulo Zanoni wrote:
>> 2015-06-17 4:52 GMT-03:00 Chris Wilson :
>> > These busy bits are locked higher up. In fact I want to migrate that
>> > lock to a spinlock, which has implications here. I didn't see anything
On Wed, Jun 17, 2015 at 01:05:54PM -0500, Nathan Schulte wrote:
> On 06/17/2015 09:56 AM, Nathan Schulte wrote:
> >I'll give these two patches a try and report back.
>
> These two patches worked beautifully. Thanks! I assume you can
> take care of getting them included upstream?
I'll taked that
On Wed, Jun 17, 2015 at 04:39:32PM -0300, Paulo Zanoni wrote:
> 2015-06-17 4:52 GMT-03:00 Chris Wilson :
> > These busy bits are locked higher up. In fact I want to migrate that
> > lock to a spinlock, which has implications here. I didn't see anything
> > that mandated using a mutex for fbc, right
On Wed, Jun 17, 2015 at 07:48:16PM +0100, Siluvery, Arun wrote:
> On 16/06/2015 21:25, Chris Wilson wrote:
> >On Tue, Jun 16, 2015 at 08:25:20PM +0100, Arun Siluvery wrote:
> >>+static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
> >>+ uint32_t offset,
>
On 17/06/2015 19:48, Siluvery, Arun wrote:
On 16/06/2015 21:25, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 08:25:20PM +0100, Arun Siluvery wrote:
+static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
+ uint32_t offset,
+
2015-06-17 4:52 GMT-03:00 Chris Wilson :
> On Tue, Jan 02, 2001 at 04:58:58AM -0200, Paulo Zanoni wrote:
>> void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
>> unsigned int frontbuffer_bits,
>> enum fb_op_origin origin)
>> @@ -691,6 +725,
On 16/06/2015 21:25, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 08:25:20PM +0100, Arun Siluvery wrote:
+static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
+ uint32_t offset,
+ uint32_t *num_dwords)
+{
+ uin
From: Ville Syrjälä
Take the HDMI 12bpc mode and pixel repeat into account when extracting
the dotclock from the hardware on DDI platforms.
Tested on HSW only.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 49
1 file changed, 24 i
From: Ville Syrjälä
HDMI 12bpc should be working fine now. Let it loose.
This reverts commit 5e3daaca09f5158eff9c92290faa1d2001ecc6e4.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_hdmi.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/
On 06/17/2015 09:56 AM, Nathan Schulte wrote:
I'll give these two patches a try and report back.
These two patches worked beautifully. Thanks! I assume you can take
care of getting them included upstream?
--
Nate
___
Intel-gfx mailing list
Intel-
A few entry points in the GEM API are expected to raise EIO if we
encounter a wedged GPU. This testcase aims to do so by first injecting a
GPU hang with GPU resets disabled (thus causing the GPU to become wedged)
and then exercises the various API to check for the expected errors.
Signed-off-by: C
On Wed, Jun 17, 2015 at 05:03:19PM +0200, Daniel Vetter wrote:
> On Wed, Jun 17, 2015 at 01:53:17PM +0100, Chris Wilson wrote:
> > On Wed, Jun 17, 2015 at 02:49:47PM +0200, Daniel Vetter wrote:
> > > On Wed, Jun 10, 2015 at 07:09:03PM +0100, Chris Wilson wrote:
> > > > On Wed, Jun 10, 2015 at 05:46
Hi
These patches were then submitted to wider lists and reviewed at
http://lkml.iu.edu/hypermail/linux/kernel/1504.3/03382.html
Few of them are already merged and few got Acked/Reviwed-By. Rework was pending
on couple of them. I am working on the same and updated set can be expected
this week.
On Tue, 16.06.15 23:25, Lennart Poettering (lenn...@poettering.net) wrote:
> > In the same sysyfs directory there's "enabled" (indicating that an output
> > is logically in use) and "dpms" (which shows the dpms state, but that is
> > not clamped to Off when the output isn't in use because of ABI h
On Wed, Jun 17, 2015 at 04:19:22PM +0100, Peter Antoine wrote:
> This change adds the programming of the MOCS registers to the gen 9+
> platforms. This change set programs the MOCS register values to a set
> of values that are defined to be optimal.
>
> It creates a fixed register set that is prog
On Wed, Jun 17, 2015 at 04:54:42PM +0200, Daniel Vetter wrote:
> On Wed, Jun 17, 2015 at 03:27:08PM +0100, Chris Wilson wrote:
> > On Wed, Jun 17, 2015 at 03:31:59PM +0200, Daniel Vetter wrote:
> > > On Fri, May 29, 2015 at 05:44:09PM +0100, john.c.harri...@intel.com wrote:
> > > > From: John Harri
On Wed, Jun 17, 2015 at 05:07:31PM +0200, Daniel Vetter wrote:
> On Wed, Jun 17, 2015 at 03:16:10PM +0100, Chris Wilson wrote:
> > We have gone far off topic.
> >
> > The question is how we want __i915_wait_request() to handle a wedged
> > GPU.
> >
> > It currently reports EIO, and my argument is
On Wed, Jun 17, 2015 at 03:02:31PM +, Antoine, Peter wrote:
> On Wed, 2015-06-10 at 11:37 +0100, Chris Wilson wrote:
> > > +/* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
> > > +#define MOCS_CACHEABILITY(value)((value & 0x03) << 0)
> >
> > value & mask? These macros should on
This change adds the programming of the MOCS registers to the gen 9+
platforms. This change set programs the MOCS register values to a set
of values that are defined to be optimal.
It creates a fixed register set that is programmed across the different
engines so that all engines have the same tab
On Wed, Jun 17, 2015 at 05:28:20PM +0300, Jani Nikula wrote:
> On Wed, 17 Jun 2015, Chris Wilson wrote:
> > Here's an idea I want to float to see if anyone has a better idea.
>
> I'll give it some thought, but it pains me that things like this make it
> harder for source code cross referencers an
On Wed, Jun 17, 2015 at 03:16:10PM +0100, Chris Wilson wrote:
> We have gone far off topic.
>
> The question is how we want __i915_wait_request() to handle a wedged
> GPU.
>
> It currently reports EIO, and my argument is that is wrong wrt to the
> semantics of the wait completion and that no call
On Wed, 2015-06-10 at 11:37 +0100, Chris Wilson wrote:
> On Wed, Jun 10, 2015 at 09:12:16AM +0100, Peter Antoine wrote:
> > This change adds the programming of the MOCS registers to the gen 9+
> > platforms. This change set programs the MOCS register values to a set
> > of values that are defined t
On 15/06/15 21:20, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 07:36:22PM +0100, Dave Gordon wrote:
>> From: Alex Dai
>>
>> intel_guc_api.h contains the subset of the GuC interface that we
>> will need for submission of commands through the GuC. These MUST
>> be kept in sync with the definitions
On Wed, Jun 17, 2015 at 01:53:17PM +0100, Chris Wilson wrote:
> On Wed, Jun 17, 2015 at 02:49:47PM +0200, Daniel Vetter wrote:
> > On Wed, Jun 10, 2015 at 07:09:03PM +0100, Chris Wilson wrote:
> > > On Wed, Jun 10, 2015 at 05:46:54PM +0100, Michel Thierry wrote:
> > > > There are some allocations t
On Tue, Jun 09, 2015 at 04:56:01PM +0100, Tomas Elf wrote:
> On 04/06/2015 19:23, john.c.harri...@intel.com wrote:
> >From: John Harrison
> >
> >A previous patch (read-read optimisation) changed the early exit
> >condition in i915_gem_retire_requests_ring() from checking the request
> >list to che
On 06/17/2015 04:13 AM, Chris Wilson wrote:
On Wed, Jun 17, 2015 at 09:46:25AM +0100, Chris Wilson wrote:
I think this is the right fix:
diff --git a/xrandr.c b/xrandr.c
index fbfd93e..c0feac3 100644
--- a/xrandr.c
+++ b/xrandr.c
@@ -3029,7 +3029,7 @@ main (int argc, char **argv)
i
On Wed, Jun 17, 2015 at 03:27:08PM +0100, Chris Wilson wrote:
> On Wed, Jun 17, 2015 at 03:31:59PM +0200, Daniel Vetter wrote:
> > On Fri, May 29, 2015 at 05:44:09PM +0100, john.c.harri...@intel.com wrote:
> > > From: John Harrison
> > >
> > > Now that the *_ring_begin() functions no longer call
On ma, 2015-06-15 at 11:59 +0300, Ville Syrjälä wrote:
> On Wed, Jun 10, 2015 at 01:18:28PM -0700, Bob Paauwe wrote:
> > The registers and process differ from other platforms.
> >
> > Signed-off-by: Bob Paauwe
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 27 +++
> >
On Wed, Jun 17, 2015 at 03:31:59PM +0200, Daniel Vetter wrote:
> On Fri, May 29, 2015 at 05:44:09PM +0100, john.c.harri...@intel.com wrote:
> > From: John Harrison
> >
> > Now that the *_ring_begin() functions no longer call the request allocation
> > code, it is finally safe for the request allo
On Wed, 17 Jun 2015, Chris Wilson wrote:
> Here's an idea I want to float to see if anyone has a better idea.
I'll give it some thought, but it pains me that things like this make it
harder for source code cross referencers and even grep to find what you
you're looking for.
BR,
Jani.
> Daniel
On Wed, Jun 17, 2015 at 04:06:05PM +0200, Daniel Vetter wrote:
> On Fri, May 29, 2015 at 05:44:16PM +0100, john.c.harri...@intel.com wrote:
> > From: John Harrison
> >
> > The i915_gem_object_flush_active() call used to do lots. Over time it has
> > done
> > less and less. Now all it does check
We have gone far off topic.
The question is how we want __i915_wait_request() to handle a wedged
GPU.
It currently reports EIO, and my argument is that is wrong wrt to the
semantics of the wait completion and that no caller actually cares about
EIO from __i915_wait_request().
* Correction: one c
On Fri, May 29, 2015 at 05:44:16PM +0100, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> The i915_gem_object_flush_active() call used to do lots. Over time it has done
> less and less. Now all it does check the various associated requests to see if
> they can be retired. Hence this pa
On Thu, Jun 04, 2015 at 01:06:34PM +0100, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> It is a bad idea for i915_add_request() to fail. The work will already have
> been
> send to the ring and will be processed, but there will not be any tracking or
> management of that work.
>
>
On Fri, May 29, 2015 at 05:44:09PM +0100, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Now that the *_ring_begin() functions no longer call the request allocation
> code, it is finally safe for the request allocation code to call
> *_ring_begin().
> This is important to guarantee t
On Wed, 2015-06-17 at 15:42 +0300, Jani Nikula wrote:
> On Wed, 17 Jun 2015, Ander Conselvan De Oliveira wrote:
> > On Wed, 2015-06-17 at 15:04 +0300, Jani Nikula wrote:
> >> On Tue, 16 Jun 2015, Ander Conselvan de Oliveira
> >> wrote:
> >> > Since the force restore logic will restore the CRTCs
BXT introduces DSI ports, for which we need to skip the DDI port setup.
Also there is no real reason for having a BUG for unknown port types so
convert it to a WARN.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
On Wed, Jun 17, 2015 at 01:53:55PM +0200, Daniel Vetter wrote:
> On Tue, Jun 16, 2015 at 05:30:19PM +0100, Chris Wilson wrote:
> > On Tue, Jun 16, 2015 at 06:21:53PM +0200, Daniel Vetter wrote:
> > > On Tue, Jun 16, 2015 at 01:10:33PM +0100, Chris Wilson wrote:
> > > > On Mon, Jun 15, 2015 at 06:34
On Wed, Jun 17, 2015 at 02:49:47PM +0200, Daniel Vetter wrote:
> On Wed, Jun 10, 2015 at 07:09:03PM +0100, Chris Wilson wrote:
> > On Wed, Jun 10, 2015 at 05:46:54PM +0100, Michel Thierry wrote:
> > > There are some allocations that must be only referenced by 32bit
> > > offsets. To limit the chanc
On Wed, Jun 17, 2015 at 01:49:15PM +0200, Daniel Vetter wrote:
> On Tue, Jun 16, 2015 at 08:33:13PM +0100, Chris Wilson wrote:
> > On Tue, Jun 16, 2015 at 06:32:22PM +0100, Tomas Elf wrote:
> > > On 16/06/2015 17:55, Chris Wilson wrote:
> > > >On Tue, Jun 16, 2015 at 04:43:55PM +0100, Tomas Elf wro
Here's an idea I want to float to see if anyone has a better idea.
Daniel is very keen on using READ_ONCE/WRITE_ONCE/ACCESS_ONCE to
document where we play games with memory barriers instead outside of the
usual locks. However, that falls down given that we have a lot of
bitfields and the macros to
On Wed, Jun 10, 2015 at 07:09:03PM +0100, Chris Wilson wrote:
> On Wed, Jun 10, 2015 at 05:46:54PM +0100, Michel Thierry wrote:
> > There are some allocations that must be only referenced by 32bit
> > offsets. To limit the chances of having the first 4GB already full,
> > objects not requiring this
On Mon, Jun 15, 2015 at 07:36:18PM +0100, Dave Gordon wrote:
> This patch series enables command submission via the GuC. In this mode,
> instead of the host CPU driving the execlist port directly, it hands
> over work items to the GuC, using a doorbell mechanism to tell the GuC
> that new items hav
On Wed, 17 Jun 2015, Ander Conselvan De Oliveira wrote:
> On Wed, 2015-06-17 at 15:04 +0300, Jani Nikula wrote:
>> On Tue, 16 Jun 2015, Ander Conselvan de Oliveira
>> wrote:
>> > Since the force restore logic will restore the CRTCs state one at a
>> > time, it is possible that the state will be
On Wed, 17 Jun 2015, Daniel Vetter wrote:
> On Fri, Jun 12, 2015 at 09:25:36PM +0100, Dave Gordon wrote:
>> Updated version split into two. The first tidies up the _ring_prepare()
>> functions and removes the corner case where we might have had to wait
>> twice; the second is a temporary workaroun
On Wed, Jun 17, 2015 at 02:22:19PM +0200, Daniel Vetter wrote:
> On Wed, Jun 17, 2015 at 09:20:44AM +0100, Dave Gordon wrote:
> > On 16/06/15 10:24, Chris Wilson wrote:
> > > On Mon, Jun 15, 2015 at 07:36:30PM +0100, Dave Gordon wrote:
> > >> +static void direct_interrupts_to_guc(struct drm_i915_pr
In order for skl+ hardware to guarantee that no context switch
takes place during engine reset and that current context is properly
saved, the driver needs to notify and query hw before commencing
with reset.
We will only proceed with reset if all engines report that they
are ready for reset.
As
On Wed, 2015-06-17 at 15:04 +0300, Jani Nikula wrote:
> On Tue, 16 Jun 2015, Ander Conselvan de Oliveira
> wrote:
> > Since the force restore logic will restore the CRTCs state one at a
> > time, it is possible that the state will be inconsistent until the whole
> > operation finishes. A call to
On Wed, 2015-06-17 at 15:13 +0300, Jani Nikula wrote:
> On Wed, 17 Jun 2015, Jani Nikula wrote:
> > On Tue, 16 Jun 2015, Ander Conselvan de Oliveira
> > wrote:
> >> Since the force restore logic will restore the CRTCs state one at a
> >> time, it is possible that the state will be inconsistent u
On Wed, Jun 17, 2015 at 09:20:44AM +0100, Dave Gordon wrote:
> On 16/06/15 10:24, Chris Wilson wrote:
> > On Mon, Jun 15, 2015 at 07:36:30PM +0100, Dave Gordon wrote:
> >> +static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
> >> +{
> >> + struct intel_engine_cs *ring;
> >> +
>
> > > The biggest change here is 4.1 stopped forcing the probe from sysfs
> > > precisely because systemd was hitting them so often for illogical
> > > reasons (being docked depends on having the lid open and an
> > > external display connected!). To force the probe, you must do
> > > $ echo
I am running Debian Sid on a laptop machine with an Intel Haswell CPU
with Intel HD 4600 graphics.
$ Xorg -version
X.Org X Server 1.17.1
Release Date: 2015-02-10
X Protocol Version 11, Revision 0
Build Operating System: Linux 3.16.0-4-amd64 x86_64 Debian
Current Operating System: Linux desmas-
On Mon, Jun 15, 2015 at 07:36:25PM +0100, Dave Gordon wrote:
> In order to fully initialise the default contexts, we have to execute
> batchbuffer commands on the GPU engines. But in the case of GuC-based
> batch submission, we can't do that until any required firmware has
> been loaded, which may
On Wed, 17 Jun 2015, Jani Nikula wrote:
> On Tue, 16 Jun 2015, Ander Conselvan de Oliveira
> wrote:
>> Since the force restore logic will restore the CRTCs state one at a
>> time, it is possible that the state will be inconsistent until the whole
>> operation finishes. A call to intel_modeset_ch
On Tue, 16 Jun 2015, Ander Conselvan de Oliveira
wrote:
> Since the force restore logic will restore the CRTCs state one at a
> time, it is possible that the state will be inconsistent until the whole
> operation finishes. A call to intel_modeset_check_state() is done once
> it's over, so don't c
On Mon, Jun 15, 2015 at 07:36:20PM +0100, Dave Gordon wrote:
> Current devices may contain one or more programmable microcontrollers
> that need to have a firmware image (aka "binary blob") loaded from an
> external medium and transferred to the device's memory.
>
> This file provides generic supp
On Wed, Jun 17, 2015 at 08:23:40AM +0100, Dave Gordon wrote:
> On 15/06/15 21:09, Chris Wilson wrote:
> > On Mon, Jun 15, 2015 at 07:36:19PM +0100, Dave Gordon wrote:
> >> From: Alex Dai
> >>
> >> i915_gem_object_write() is a generic function to copy data from a plain
> >> linear buffer to a paged
On Wed, 17 Jun 2015, Jani Nikula wrote:
> On Wed, 17 Jun 2015, Chris Wilson wrote:
>> On Wed, Jun 17, 2015 at 02:01:57PM +1000, Dave Airlie wrote:
>>> From: Dave Airlie
>>>
>>> This just adds enables for the codecs and debugfs
>>> support for mst connectors to print the audio info.
>>>
>>> Thi
On Wed, 17 Jun 2015, Chris Wilson wrote:
> On Wed, Jun 17, 2015 at 02:01:57PM +1000, Dave Airlie wrote:
>> From: Dave Airlie
>>
>> This just adds enables for the codecs and debugfs
>> support for mst connectors to print the audio info.
>>
>> This relies on patches to the audio code to do anythi
On Tue, Jun 16, 2015 at 05:30:19PM +0100, Chris Wilson wrote:
> On Tue, Jun 16, 2015 at 06:21:53PM +0200, Daniel Vetter wrote:
> > On Tue, Jun 16, 2015 at 01:10:33PM +0100, Chris Wilson wrote:
> > > On Mon, Jun 15, 2015 at 06:34:51PM +0200, Daniel Vetter wrote:
> > > > On Thu, Jun 11, 2015 at 09:01
On Tue, Jun 16, 2015 at 04:54:14PM +0100, Tomas Elf wrote:
> On 16/06/2015 14:49, Daniel Vetter wrote:
> >On Mon, Jun 08, 2015 at 06:03:21PM +0100, Tomas Elf wrote:
> >>In preparation for per-engine reset add way for setting context reset stats.
> >>
> >>OPEN QUESTIONS:
> >>1. How do we deal with g
On Tue, Jun 16, 2015 at 08:33:13PM +0100, Chris Wilson wrote:
> On Tue, Jun 16, 2015 at 06:32:22PM +0100, Tomas Elf wrote:
> > On 16/06/2015 17:55, Chris Wilson wrote:
> > >On Tue, Jun 16, 2015 at 04:43:55PM +0100, Tomas Elf wrote:
> > >>On 16/06/2015 14:43, Daniel Vetter wrote:
> > >>>On Mon, Jun
On Tue, Jun 16, 2015 at 04:46:05PM +0100, Tomas Elf wrote:
> On 16/06/2015 14:44, Daniel Vetter wrote:
> >On Mon, Jun 08, 2015 at 06:03:19PM +0100, Tomas Elf wrote:
> >>When submitting semaphores in execlist mode the hang checker crashes in this
> >>function because it is only runnable in ring subm
On Wed, Jun 17, 2015 at 07:47:23AM +0200, Maarten Lankhorst wrote:
> Hey,
>
> Op 17-06-15 om 00:12 schreef Matt Roper:
> > On Mon, Jun 08, 2015 at 06:59:38AM +0200, Maarten Lankhorst wrote:
> >> Hey,
> >>
> >> Op 06-06-15 om 00:08 schreef Matt Roper:
> >>> We need to call drm_atomic_set_mode_for_c
On Tue, Jun 16, 2015 at 04:46:40PM +0300, Ville Syrjälä wrote:
> On Tue, Jun 16, 2015 at 03:40:16PM +0200, Daniel Vetter wrote:
> > On Mon, Jun 15, 2015 at 09:03:09PM +, Konduru, Chandra wrote:
> > > > >
> > > > > Cdclk < crtc_clock is not allowed and suggests a different problem
> > > > > els
On Tue, Jun 16, 2015 at 10:33:35PM +0530, Singh, Gaurav K wrote:
>
>
> On 6/15/2015 4:03 PM, Daniel Vetter wrote:
> >On Sat, Jun 13, 2015 at 12:24:57PM +0530, Mohan Marimuthu, Yogesh wrote:
> >>
> >>On 5/29/2015 10:51 PM, Daniel Vetter wrote:
> >>>On Fri, May 29, 2015 at 04:07:03PM +0530, Gaurav
On Tue, Jun 16, 2015 at 10:24:57PM +0530, Singh, Gaurav K wrote:
>
>
> On 5/29/2015 10:53 PM, Daniel Vetter wrote:
> >On Fri, May 29, 2015 at 07:14:43PM +0200, Daniel Vetter wrote:
> >>On Fri, May 29, 2015 at 04:06:58PM +0530, Gaurav K Singh wrote:
> >>>vblank interrupt should be disabled before
On Tue, Jun 16, 2015 at 05:07:46PM +0100, Chris Wilson wrote:
> On Tue, Jun 16, 2015 at 04:10:19PM +0100, Tvrtko Ursulin wrote:
> >
> >
> > On 06/16/2015 02:53 PM, Chris Wilson wrote:
> > >On Tue, Jun 16, 2015 at 02:32:40PM +0100, Tvrtko Ursulin wrote:
> > >>
> > >>On 06/16/2015 12:48 PM, Chris W
On Wed, Jun 17, 2015 at 04:21:10PM +0530, Sagar Arun Kamble wrote:
> DC9 entry and exit programming is critical part of suspend/resume
> sequences. This patch adds tracepoints that can help analyze time
> taken using analyze_suspend.py/FTrace.
>
> Change-Id: I22fca5313c4349f8937eeb5a1c441c8ef76e5f
On Wed, Jun 17, 2015 at 02:01:57PM +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> This just adds enables for the codecs and debugfs
> support for mst connectors to print the audio info.
>
> This relies on patches to the audio code to do anything
> more useful.
>
> Signed-off-by: Dave Airlie
On Wed, Jun 17, 2015 at 10:29:48AM +0200, David Herrmann wrote:
> Hi
>
> On Tue, Jun 16, 2015 at 11:25 PM, Lennart Poettering
> wrote:
> > On Tue, 16.06.15 13:47, Daniel Vetter (dan...@ffwll.ch) wrote:
> >
> >> > But what does that actually mean? should logind ever echo "detect"
> >> > itself int
On Fri, Jun 12, 2015 at 09:25:36PM +0100, Dave Gordon wrote:
> Updated version split into two. The first tidies up the _ring_prepare()
> functions and removes the corner case where we might have had to wait
> twice; the second is a temporary workaround to solve a kernel OOPS that
> can occur if log
Atm when calculating the maximum plane scale factor, we use the active
CDCLK rate. The target CDCLK rate for the upcoming modeset may be
different from this, so use the target rate instead.
This fixes the modeset on BXT, where the initial rate was smaller than
the target rate. On SKL we use a fixe
For GEN9 the target cdclk frequency is needed during the modeset state check
phase too, so factor out this functionality.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_display.c | 48 ++--
1 file changed, 30 insertions(+), 18 deletions(-)
diff --git a/d
DC9 entry and exit programming is critical part of suspend/resume
sequences. This patch adds tracepoints that can help analyze time
taken using analyze_suspend.py/FTrace.
Change-Id: I22fca5313c4349f8937eeb5a1c441c8ef76e5f4e
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c | 9
On 16/06/2015 21:33, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 08:25:20PM +0100, Arun Siluvery wrote:
+static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
+{
+ int ret;
+ struct drm_device *dev = ring->dev;
You only use it once, keeping it as a local seems cou
On 6/17/2015 2:45 PM, Jindal, Sonika wrote:
On 6/12/2015 3:57 PM, Vandana Kannan wrote:
Changes for BXT - added a IS_BROXTON check to use the macro related to
PPS
registers for BXT.
BXT does not have PP_DIV register. Making changes to handle this.
Second set of PPS registers have been define
On 6/12/2015 3:57 PM, Vandana Kannan wrote:
Changes for BXT - added a IS_BROXTON check to use the macro related to PPS
registers for BXT.
BXT does not have PP_DIV register. Making changes to handle this.
Second set of PPS registers have been defined but will be used when VBT
provides a selectio
On Wed, Jun 17, 2015 at 09:46:25AM +0100, Chris Wilson wrote:
> On Tue, Jun 16, 2015 at 10:40:17AM -0500, Nathan Schulte wrote:
> > I am running Debian Sid on a laptop machine with an Intel Haswell
> > CPU with Intel HD 4600 graphics.
> >
> > >$ Xorg -version
> > >
> > >X.Org X Server 1.17.1
> > >
On Tue, Jun 16, 2015 at 10:40:17AM -0500, Nathan Schulte wrote:
> I am running Debian Sid on a laptop machine with an Intel Haswell
> CPU with Intel HD 4600 graphics.
>
> >$ Xorg -version
> >
> >X.Org X Server 1.17.1
> >Release Date: 2015-02-10
> >X Protocol Version 11, Revision 0
> >Build Operati
Hi
On Tue, Jun 16, 2015 at 11:25 PM, Lennart Poettering
wrote:
> On Tue, 16.06.15 13:47, Daniel Vetter (dan...@ffwll.ch) wrote:
>
>> > But what does that actually mean? should logind ever echo "detect"
>> > itself into the file? Should it follow uevents for the files? How
>> > should treat this f
On Fri, Apr 10, 2015 at 8:15 PM, Rodrigo Vivi wrote:
>
> /**
> + * intel_psr_single_frame_update - Single Frame Update
> + * @dev: DRM device
> + *
> + * Some platforms support a single frame update feature that is used to
> + * send and update only one frame on Remote Frame Buffer.
> + * So far
On 16/06/15 10:24, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 07:36:30PM +0100, Dave Gordon wrote:
>> +static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
>> +{
>> +struct intel_engine_cs *ring;
>> +int i, irqs;
>> +
>> +/* tell all command streamers to forward in
On Tue, Jan 02, 2001 at 04:58:58AM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Make sure we're not gonna have weird races in really weird cases where
> a lot of different CRTCs are doing rendering and modesets at the same
> time.
>
> v2:
> - Rebase (6 months later)
> - Also lock debugf
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