On 5/29/2015 10:51 PM, Daniel Vetter wrote:
On Fri, May 29, 2015 at 04:07:03PM +0530, Gaurav K Singh wrote:
During enable sequence for MIPI encoder in command mode, enable
MIPI display self-refresh mode bit in Pipe Ctrl reg.
Signed-off-by: Gaurav K Singh
Signed-off-by: Yogesh Mohan Marimuthu
Hi Matthew,
here is the patch I've mentioned on irc today:
http://cgit.freedesktop.org/~vivijim/drm-intel/commit/?h=psr_for_mjg59&id=83809492138f2395bfb12c19e6de916de64b9246
And I prepared this branch for now:
http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=psr_for_mjg59
I'm not sending ye
Dell Optiplex GX280
P4 32 bit Hyperthreading enabled 0F34 2.8GHz CPU
00:02.0 VGA compatible controller: Intel Corporation 82915G/GV/910GL Integrated
Graphics Controller (rev 04)
/etc/X11/xinit/xinitrc.d/setup contains:
xrandr --fbmm 387x218 --fb 2560x1440 --output VGA1 --mode 1920x1440 --panning
On Thu, Jun 11, 2015 at 03:34:14PM +0200, Patrik Jakobsson wrote:
> On Thu, Jun 11, 2015 at 02:27:12AM +0300, Dmitry V. Levin wrote:
> > On Wed, Jun 10, 2015 at 02:45:24PM +0200, Patrik Jakobsson wrote:
> > > On Wed, Jun 10, 2015 at 01:35:35AM +0300, Dmitry V. Levin wrote:
> > > > On Tue, Jun 09, 2
On Thu, Jun 11, 2015 at 04:11:49PM +0200, Patrik Jakobsson wrote:
> On Thu, Jun 11, 2015 at 02:26:59AM +0300, Dmitry V. Levin wrote:
> > On Wed, Jun 10, 2015 at 01:52:33PM +0200, Patrik Jakobsson wrote:
> > > On Wed, Jun 10, 2015 at 01:14:20AM +0300, Dmitry V. Levin wrote:
> > > > On Tue, Jun 09, 2
From: Paulo Zanoni
We tried to fix this in the following commit:
commit fdc454c1484a20e1345cf4e4d7a9feaee814147f
Author: Michel Thierry
Date: Tue Mar 24 15:46:19 2015 +
drm/i915: Prevent out of range pt in gen6_for_each_pde
but the static analyzer still complains that, just before we
On Fri, Jun 12, 2015 at 08:55:09PM +0100, Dave Gordon wrote:
> > However, that makes an incorrect assumption about the waiter. Given that
> > the current code is written such that ringbuf->last_retired_head =
> > request->postfix and that space is identical to the repeated
> > calculation, what is
Updated version split into two. The first tidies up the _ring_prepare()
functions and removes the corner case where we might have had to wait
twice; the second is a temporary workaround to solve a kernel OOPS that
can occur if logical_ring_begin is called while the ringbuffer is not
mapped because
In the case that the ringbuffer was near-full AND 'tail' was
near the end of the buffer, we could have ended up waiting twice:
once to gain ownership of the space between TAIL and the end
(which we just want to fill with padding, so as not to split a
single command sequence across the end of the ri
The original idea of preallocating the OLR was implemented in
> 9d773091 drm/i915: Preallocate next seqno before touching the ring
and the sequence of operations was to allocate the OLR, then wrap past
the end of the ring if necessary, then wait for space if necessary.
But subsequently intel_ring
On 12/06/15 19:12, Chris Wilson wrote:
> On Fri, Jun 12, 2015 at 06:09:07PM +0100, Dave Gordon wrote:
>> When calculating the available space in a ringbuffer, we should
>> use the effective_size rather than the true size of the ring.
>>
>> v2: rebase to latest drm-intel-nightly
>> v3: rebase to lat
On Fri, Jun 12, 2015 at 07:54:17PM +0100, Dave Gordon wrote:
> On 12/06/15 19:05, Chris Wilson wrote:
> > On Fri, Jun 12, 2015 at 06:09:08PM +0100, Dave Gordon wrote:
> >> The original idea of preallocating the OLR was implemented in
> >>
> >>> 9d773091 drm/i915: Preallocate next seqno before touch
On 12/06/15 19:05, Chris Wilson wrote:
> On Fri, Jun 12, 2015 at 06:09:08PM +0100, Dave Gordon wrote:
>> The original idea of preallocating the OLR was implemented in
>>
>>> 9d773091 drm/i915: Preallocate next seqno before touching the ring
>>
>> and the sequence of operations was to allocate the O
On Fri, Jun 12, 2015 at 06:09:07PM +0100, Dave Gordon wrote:
> When calculating the available space in a ringbuffer, we should
> use the effective_size rather than the true size of the ring.
>
> v2: rebase to latest drm-intel-nightly
> v3: rebase to latest drm-intel-nightly
>
> Signed-off-by: Dav
On Fri, Jun 12, 2015 at 06:09:08PM +0100, Dave Gordon wrote:
> The original idea of preallocating the OLR was implemented in
>
> > 9d773091 drm/i915: Preallocate next seqno before touching the ring
>
> and the sequence of operations was to allocate the OLR, then wrap past
> the end of the ring if
From: Akash Goel
Read the efficient frequency (aka RPe) value through the the mailbox
command (0x1A) from the pcode, as done on Haswell and Broadwell.
The turbo minimum frequency softlimit is not revised as per the
efficient frequency value.
v2: Replaced the conditional expression operator with
On Fri, Jun 12, 2015 at 02:36:17PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Thanks for the V1 reviews and comments!
>
> Paulo Zanoni (4):
> drm/i915: print FBC compression status on debugfs
> drm/i915: add FBC_ROTATION to enum no_fbc_reason
> drm/i915: unify no_fbc_reason messag
From: Paulo Zanoni
Thanks for the V1 reviews and comments!
Paulo Zanoni (4):
drm/i915: print FBC compression status on debugfs
drm/i915: add FBC_ROTATION to enum no_fbc_reason
drm/i915: unify no_fbc_reason message printing
drm/i915: don't set the FBC plane select bits on HSW+
drivers/g
From: Paulo Zanoni
Because we're currently using FBC_UNSUPPORTED_MODE for two different
cases.
This commit will also allow us to write the next one without hiding
information from the user.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +++
drivers/gpu/drm/i915/i915_
From: Paulo Zanoni
This commit is just to make the intentions explicit: on HSW+ these
bits are MBZ, but since we only support plane A and the macro
evaluates to zero when plane A is the parameter, we're not fixing any
bug.
v2:
- Remove useless extra blank like (Chris).
- Init dpfc_ctl in anoth
From: Paulo Zanoni
This commit has two main advantages: simplify intel_fbc_update()
and deduplicate the strings.
v2:
- Rebase due to changes on P1.
- set_no_fbc_reason() can now return void (Chris).
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_debugfs.c | 49 +++
From: Paulo Zanoni
We already had a few bugs in the past where FBC was compressing
nothing when it was enabled, which makes the feature quite useless.
Add this information to debugfs so the test suites can check for
regressions in this piece of the code.
Our igt/tests/kms_frontbuffer_tracking al
Hi Kausal Malladi,
On 5 June 2015 at 13:00, Jindal, Sonika wrote:
> On 6/4/2015 7:12 PM, Kausal Malladi wrote:
>>
>> From: Kausal Malladi
>>
...
>> v2: Addressing Daniel Stone's comment, added a variable sized array to
>> carry Gamma correction values as blob property.
>>
>> Signed-off-by: Shash
When calculating the available space in a ringbuffer, we should
use the effective_size rather than the true size of the ring.
v2: rebase to latest drm-intel-nightly
v3: rebase to latest drm-intel-nightly
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_lrc.c|5 +++--
driver
The original idea of preallocating the OLR was implemented in
> 9d773091 drm/i915: Preallocate next seqno before touching the ring
and the sequence of operations was to allocate the OLR, then wrap past
the end of the ring if necessary, then wait for space if necessary.
But subsequently intel_ring
Updates and supersedes the referenced patch,
"Reinstate order of operations in {intel,logical}_ring_begin()"
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 12/06/15 12:58, Siluvery, Arun wrote:
> On 09/06/2015 19:43, Dave Gordon wrote:
>> On 05/06/15 14:57, Arun Siluvery wrote:
>>> In Per context w/a batch buffer,
>>> WaRsRestoreWithPerCtxtBb
>>>
>>> v2: This patches modifies definitions of MI_LOAD_REGISTER_MEM and
>>> MI_LOAD_REGISTER_REG; Add GEN
On 05/26/2015 10:22 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Switch from using 31 PFI credits to 63 PFI credits when cdclk>=czclk on
CHV. The spec lists both 31 and 63 as "suggested" values, but based on
feedback from hardware folks we should actually be using 63. Originally
Hi folks,
the attached patch fixes the resume from suspend on the IBM X30 (Bug
49838) by keeping a backup of the IVCH registers during initialization
and by replaying those values when re-setting a mode. The patch has been
successfully tested on an IBM X30 and on an IBM R31 laptop, both of
which m
Op 12-06-15 om 13:43 schreef Ville Syrjälä:
> On Fri, Jun 12, 2015 at 02:27:54PM +0300, Ville Syrjälä wrote:
>> On Fri, Jun 12, 2015 at 12:31:37PM +0200, Maarten Lankhorst wrote:
>>> Op 12-06-15 om 12:16 schreef Ville Syrjälä:
On Fri, Jun 12, 2015 at 11:15:40AM +0200, Maarten Lankhorst wrote:
Hey,
Op 12-06-15 om 14:45 schreef Jani Nikula:
> On Fri, 12 Jun 2015, Maarten Lankhorst
> wrote:
>> Commit f662af8c5c1619 reverts
>> "drm/i915: Read hw state into an atomic state struct, v2."
>> but it doesn't take into account other changes that were done in that time.
>> Before I continue on t
On Fri, 12 Jun 2015, Maarten Lankhorst
wrote:
> Commit f662af8c5c1619 reverts
> "drm/i915: Read hw state into an atomic state struct, v2."
> but it doesn't take into account other changes that were done in that time.
> Before I continue on the atomic fixes I want to fix the fallout first,
> and s
On Thu, Jun 11, 2015 at 04:02:26PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> This commit has two main advantages: simplify intel_fbc_update()
> and deduplicate the strings.
>
> Signed-off-by: Paulo Zanoni
I had some things around that topic as well in feb. May be of interest:
http:/
On Fri, Jun 12, 2015 at 11:15:39AM +0200, Maarten Lankhorst wrote:
> This should fix fallout caused by making intel_crtc_control
> and update_dpms atomic, which became a problem after reverting the
> atomic hw readout patch.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90929
> Report
On Thu, Jun 11, 2015 at 04:02:24PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> We already had a few bugs in the past where FBC was compressing
> nothing when it was enabled, which makes the feature quite useless.
> Add this information to debugfs so the test suites can check for
> regress
On 09/06/2015 19:43, Dave Gordon wrote:
On 05/06/15 14:57, Arun Siluvery wrote:
In Per context w/a batch buffer,
WaRsRestoreWithPerCtxtBb
v2: This patches modifies definitions of MI_LOAD_REGISTER_MEM and
MI_LOAD_REGISTER_REG; Add GEN8 specific defines for these instructions
so as to not break a
On 05/06/2015 15:48, Ville Syrjälä wrote:
On Fri, Jun 05, 2015 at 02:56:48PM +0100, Arun Siluvery wrote:
In Indirect context w/a batch buffer,
+WaFlushCoherentL3CacheLinesAtContextSwitch
Signed-off-by: Rafael Barbalho
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
On Fri, Jun 12, 2015 at 12:32:24PM +0200, Maarten Lankhorst wrote:
> Op 12-06-15 om 12:26 schreef Ville Syrjälä:
> > On Fri, Jun 12, 2015 at 11:15:42AM +0200, Maarten Lankhorst wrote:
> >> The cursor should only be enabled if it's visible. This fixes
> >> igt/kms_cursor_crc, which may otherwise pro
On Fri, Jun 12, 2015 at 02:27:54PM +0300, Ville Syrjälä wrote:
> On Fri, Jun 12, 2015 at 12:31:37PM +0200, Maarten Lankhorst wrote:
> > Op 12-06-15 om 12:16 schreef Ville Syrjälä:
> > > On Fri, Jun 12, 2015 at 11:15:40AM +0200, Maarten Lankhorst wrote:
> > >> Use a full atomic call instead. intel_c
On Fri, 2015-06-12 at 13:32 +0300, Ville Syrjälä wrote:
> On Fri, Jun 12, 2015 at 03:01:08PM +0530, akash.g...@intel.com wrote:
> > From: Akash Goel
> >
> > Read the efficient frequency (aka RPe) value through the the mailbox
> > command (0x1A) from the pcode, as done on Haswell and Broadwell.
>
On Thu, Jun 11, 2015 at 04:02:23PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Let's try to get the easy stuff merged while the rest is not ready
> yet.
>
> This is a nice opportunity for you to easily increase your patch
> review count!
Sigh. I was until you said this. A couple of mino
On Fri, Jun 12, 2015 at 12:31:37PM +0200, Maarten Lankhorst wrote:
> Op 12-06-15 om 12:16 schreef Ville Syrjälä:
> > On Fri, Jun 12, 2015 at 11:15:40AM +0200, Maarten Lankhorst wrote:
> >> Use a full atomic call instead. intel_crtc_page_flip will still
> >> have to live until async updates are allo
On Thu, Jun 11, 2015 at 04:02:26PM -0300, Paulo Zanoni wrote:
> @@ -439,6 +472,8 @@ static bool set_no_fbc_reason(struct drm_i915_private
> *dev_priv,
> return false;
>
> dev_priv->fbc.no_fbc_reason = reason;
> + DRM_DEBUG_KMS("Disabling FBC: %s\n", intel_no_fbc_reason_st
On Thu, Jun 11, 2015 at 04:02:27PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> This commit is just to make the intentions explicit: on HSW+ these
> bits are MBZ, but since we only support plane A and the macro
> evaluates to zero when plane A is the parameter, we're not fixing any
> bug.
On Thu, Jun 11, 2015 at 02:51:19PM +0100, Chris Wilson wrote:
> On Thu, Jun 11, 2015 at 04:31:14PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Currently intel_gen4_compute_page_offset() simply picks the closest
> > page boundary below the linear offset. That howeve
Fixed variables incorrectly declared as int instead of size_t.
v2: Addressed comments from Tim Gore
v3: Removed 'unused parameter' changes
v4: Changed to size_t
v5: Moved declarations out of for loops
Signed-off-by: Derek Morton
---
lib/igt_core.c | 18 +++---
1 file changed, 11 ins
On Fri, Jun 12, 2015 at 03:01:08PM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> Read the efficient frequency (aka RPe) value through the the mailbox
> command (0x1A) from the pcode, as done on Haswell and Broadwell.
> The turbo minimum frequency softlimit is not revised as per the
>
Op 12-06-15 om 12:26 schreef Ville Syrjälä:
> On Fri, Jun 12, 2015 at 11:15:42AM +0200, Maarten Lankhorst wrote:
>> The cursor should only be enabled if it's visible. This fixes
>> igt/kms_cursor_crc, which may otherwise produce the following
>> warning:
>>
>> [ cut here ]
>
Op 12-06-15 om 12:16 schreef Ville Syrjälä:
> On Fri, Jun 12, 2015 at 11:15:40AM +0200, Maarten Lankhorst wrote:
>> Use a full atomic call instead. intel_crtc_page_flip will still
>> have to live until async updates are allowed.
>>
>> This doesn't seem to be a regression from the convert to atomic,
On Fri, Jun 12, 2015 at 11:15:42AM +0200, Maarten Lankhorst wrote:
> The cursor should only be enabled if it's visible. This fixes
> igt/kms_cursor_crc, which may otherwise produce the following
> warning:
>
> [ cut here ]
> WARNING: CPU: 0 PID: 3425 at drivers/gpu/drm/i915
From: Akash Goel
Read the efficient frequency (aka RPe) value through the the mailbox
command (0x1A) from the pcode, as done on Haswell and Broadwell.
The turbo minimum frequency softlimit is not revised as per the
efficient frequency value.
v2: Replaced the conditional expression operator with
On Fri, Jun 12, 2015 at 11:15:41AM +0200, Maarten Lankhorst wrote:
> This was introduced after converting hw readout to atomic,
> so it should have been part of the revert too.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90929
> Reported-by: Ville Syrjälä
> Signed-off-by: Maarten L
On Fri, Jun 12, 2015 at 11:15:40AM +0200, Maarten Lankhorst wrote:
> Use a full atomic call instead. intel_crtc_page_flip will still
> have to live until async updates are allowed.
>
> This doesn't seem to be a regression from the convert to atomic,
> part 3 patch. During GPU reset it fixes the fo
Unit test to check a segfaulting subtest is handled correctly.
v2: Added script to check subtest results
v3: Removed script. Updated test to use fork to monitor return status.
v4: Added igt_segfault to .gitignore
Signed-off-by: Derek Morton
---
lib/tests/.gitignore | 1 +
lib/tests/Make
This is the same as the previously submitted patch except the text encoding
should (hopefully) now be correct.
//Derek
>
>
>-Original Message-
>From: Morton, Derek J
>Sent: Friday, June 12, 2015 11:05 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Wood, Thomas; dan...@ffwll.ch; Morton, De
Changes for BXT - added a IS_BROXTON check to use the macro related to PPS
registers for BXT.
BXT does not have PP_DIV register. Making changes to handle this.
Second set of PPS registers have been defined but will be used when VBT
provides a selection between the 2 sets of registers.
v2:
[Jani] A
In intel it's useful to keep track of some state changes with old
crtc state vs new state, for example to disable initial planes or
when a modeset's prevented during fastboot.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 6 --
drivers/gpu/drm/drm_ato
This should fix fallout caused by making intel_crtc_control
and update_dpms atomic, which became a problem after reverting the
atomic hw readout patch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90929
Reported-by: Ville Syrjälä
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i9
The cursor should only be enabled if it's visible. This fixes
igt/kms_cursor_crc, which may otherwise produce the following
warning:
[ cut here ]
WARNING: CPU: 0 PID: 3425 at drivers/gpu/drm/i915/intel_display.c:9995
intel_crtc_update_cursor+0x14c/0x4d0 [i915]()
Missing sw
This was introduced after converting hw readout to atomic,
so it should have been part of the revert too.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90929
Reported-by: Ville Syrjälä
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 in
Commit f662af8c5c1619 reverts
"drm/i915: Read hw state into an atomic state struct, v2."
but it doesn't take into account other changes that were done in that time.
Before I continue on the atomic fixes I want to fix the fallout first,
and some of the reasons I identified that could cause a failure
Use a full atomic call instead. intel_crtc_page_flip will still
have to live until async updates are allowed.
This doesn't seem to be a regression from the convert to atomic,
part 3 patch. During GPU reset it fixes the following warning:
[ cut here ]
WARNING: CPU: 0 PID:
On Thu, 11 Jun 2015, Damien Lespiau wrote:
> On Wed, Jun 10, 2015 at 09:18:29AM -0700, Matt Roper wrote:
>> On Thu, Jun 04, 2015 at 06:01:35PM +0300, Imre Deak wrote:
>> > According to bspec the DDI PHY vswing scale value is "don't care" in
>> > case the scale enable bit [27] is clear. But this do
On Wed, 10 Jun 2015, "O'Rourke, Tom" wrote:
>> > +
>> > + dev_priv->rps.efficient_freq *=
>> > + (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
>
> This line seems awkward. I suppose a good compiler could
> optimize out the multiply by one.
>
> I wou
The code in intel_crtc_restore_mode() sets the enabled value of all the
CRTCs when restoring the mode after a suspend/resume cycle. When more
than one CRTC is enabled, that causes drm_atomic_helper_check_modeset()
to fail if there is more than one pipe enabled, since only one CRTC has
valid connect
Hi,
These three patches solve two issues in drm-intel-next-fixes. The most
important one is the fail to restore modes properly in the force_restore
path, after a suspend/resume cycle, fixed by the last two patches. The
other is a fix a sent before, for the multiple checks during force
restore.
Th
The force restore path relies on the staged config to preserve the
configuration used before a suspend/resume cycle. The update done to it
in intel_modeset_fixup_state() would cause that information to be lost
after the first modeset, making it impossible to restore the modes for
pipes B and C.
Re
Since the force restore logic will restore the CRTCs state one at a
time, it is possible that the state will be inconsistent until the whole
operation finishes. A call to intel_modeset_check_state() is done once
it's over, so don't check the state multiple times in between. This
regression was intr
For Cherryview the CD clock is limited up
to 320MHz.
Based on the received comments, I cleaned up
the if-else tree.
Mika Kahola (1):
drm/i915: Limit CHV max cdclk
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
--
1.9.1
_
Limit CHV maximum cdclk to 320MHz.
v2: Rebase to the latest
v3: Clean up of if-else tree
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5
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