Hey,
Op 20-05-15 om 18:04 schreef maarten.lankho...@linux.intel.com:
> From: Ander Conselvan de Oliveira
>
> To make this work we load the new hardware state into the
> atomic_state, then swap it with the sw state.
>
> This lets us change the force restore path in setup_hw_state()
> to use a sing
On Thu, May 21, 2015 at 5:04 AM, Animesh Manna wrote:
> Naming convention of csr firmware will be -
> _dmc__.bin
>
> Accordingly updated the same in code.
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/intel_csr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --
Hi!
Debian 8 based system. X suddenly froze. Not quite reproducible, I'm afraid.
Pavel
[331445.592203] ftdi_sio 5-2:1.0: device disconnected
[331447.063345] r8169 :03:00.0 eth0: link up
[331447.930260] PM: resume of devices comp
On Thu, 21 May 2015 10:37:07 +0200
Daniel Vetter wrote:
> On Wed, May 20, 2015 at 10:07:58AM -0700, Bob Paauwe wrote:
> > On Fri, 15 May 2015 12:39:20 +0300
> > Ville Syrjälä wrote:
> >
> > > On Tue, Feb 24, 2015 at 09:52:16PM +0100, Daniel Vetter wrote:
> > > > On Tue, Feb 24, 2015 at 10:37:10
On Tue, May 26, 2015 at 05:25:48PM +0200, Daniel Vetter wrote:
> On Tue, May 26, 2015 at 03:21:22PM +0100, Michel Thierry wrote:
> > There are some allocations that must be only referenced by 32bit
> > offsets.
> > To limit the chances of having the first 4GB already full,
> > objects not requirin
Thank you Jani and Paul.
We had a recent server migration and software update on 01.org that
might cause some issues like that, or outdated pages or 404 erros, or
others.
Please let me know any issues you might face that I'll work close to IT
to get them fixed and/or updated.
Thanks,
Rodrigo.
O
From: Ville Syrjälä
chv_enable_pll() doesn't need to hold sb_lock for the entire duration of
the function. Drop the lock as soon as possible.
valleyview_set_cdclk() does a potential lock+unlock+lock+unlock cycle
with sb_lock. Move Grab the lock a few lines earlier so we can make do
with a single
From: Ville Syrjälä
Rename dpio_lock to sb_lock to inform the reader that its primary
purpose is to protect the sideband mailbox rather than some DPIO
state.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_dma.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h| 4 +--
From: Ville Syrjälä
The primary plane frobbing was removed from the sprite code in
commit ecce87ea3ab55ad0dc64460e6422c357d158a55e
Author: Maarten Lankhorst
Date: Tue Apr 21 17:12:50 2015 +0300
drm/i915: Remove implicitly disabling primary plane for now
but the intel_flush_primary_pla
From: Ville Syrjälä
The two DPIO patches here were part of my DPIO powergating series, but as the
actualy DPIO powergating needs further work I've left that particular patch
behind for now. These other two are good to go without it however so here they
are. I clarified the pipe-a power well comm
From: Ville Syrjälä
Not sure which LDO programming sequence delay should be used for the CHV
PHY, but the spec says that 600ns is "Used by default for initial
bringup", and the BIOS seems to use that, so let's do the same.
Reviewed-by: Deepak S
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm
From: Ville Syrjälä
Expecting CHV power wells to be just an extended versions of the VLV
power wells, a bunch of commented out power wells were added in
anticipation when Punit folks would implement it all. Turns out they
never did, and instead CHV has fewer power wells than VLV. Rip out all
the
From: Ville Syrjälä
Switch from using 31 PFI credits to 63 PFI credits when cdclk>=czclk on
CHV. The spec lists both 31 and 63 as "suggested" values, but based on
feedback from hardware folks we should actually be using 63. Originally
I picked the 31 basically by flipping a coin.
Signed-off-by:
On 5/26/2015 4:25 PM, Daniel Vetter wrote:
On Tue, May 26, 2015 at 03:21:22PM +0100, Michel Thierry wrote:
There are some allocations that must be only referenced by 32bit
offsets. To limit the chances of having the first 4GB already full,
objects not requiring this workaround don't use the firs
-Original Message-
From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of
Daniel Vetter
Sent: Tuesday, May 26, 2015 4:27 PM
To: Morton, Derek J
Cc: intel-gfx; Wood, Thomas
Subject: Re: [Intel-gfx] [PATCH i-g-t] lib/tests/igt_segfault.c Add unit test
to test segfault h
On Tue, May 26, 2015 at 5:05 PM, Derek Morton wrote:
> + * The test consists of three subtests. The first and third should pass
> + * while the second should cause a segfault.
> + * The overall result should be a failure with two subtests passing.
You need to split this up into separate binaries
On Tue, May 26, 2015 at 03:21:22PM +0100, Michel Thierry wrote:
> There are some allocations that must be only referenced by 32bit
> offsets. To limit the chances of having the first 4GB already full,
> objects not requiring this workaround don't use the first 2 PDPs.
>
> User must pass EXEC_OBJEC
On Tue, May 26, 2015 at 02:57:19PM +0100, Damien Lespiau wrote:
> It was reported that this comment was confusing, and indeed it is.
>
> v2: (one year later!) Add the range for the DRM_I915_* iotcl defines
> (Daniel)
>
> Signed-off-by: Damien Lespiau
Queued for -next, thanks for the patch.
2015-05-26 8:13 GMT-03:00 Thomas Wood :
> On 25 May 2015 at 22:40, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> This is a new test that should exercise the frontbuffer tracking
>> feature of the Kernel in a number of different ways. We use different
>> drawing methods, we use the primary, curs
On 5/26/2015 3:21 PM, Michel Thierry wrote:
When 48b is enabled, gen8_ppgtt_insert_entries needs to read the Page Map
Level 4 (PML4), before it selects which Page Directory Pointer (PDP)
it will write to.
Similarly, gen8_ppgtt_clear_range needs to get the correct PDP/PD range.
This patch was in
Unit test to check a segfaulting subtest is handled correctly.
Signed-off-by: Derek Morton
---
lib/tests/Makefile.sources | 2 ++
lib/tests/igt_segfault.c | 57 ++
2 files changed, 59 insertions(+)
create mode 100644 lib/tests/igt_segfault.c
diff
Signed-off-by: Mayuresh Gharpure
---
tests/Makefile.sources | 1 +
tests/kms_render_compression.c | 359 +
2 files changed, 360 insertions(+)
create mode 100644 tests/kms_render_compression.c
diff --git a/tests/Makefile.sources b/tests/Makefile.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 17 +
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i91
PML4 has no special attributes, and there will always be a PML4.
So simply initialize it at creation, and destroy it at the end.
The code for 4lvl is able to call into the existing 3lvl page table code
to handle all of the lower levels.
v2: Return something at the end of gen8_alloc_va_range_4lvl
GTT is only 32b and its max value is 4GB. In order to allow objects
bigger than 4GB in 48b PPGTT, i915_gem_userptr_ioctl needs to check
against max 48b range (1ULL << 48).
Whenever possible, read the PPGTT's total instead of the GTT one, this
will be accurate in 32 and 48 bit modes.
v2: Use the d
Similar to PDs, while setting up a page directory pointer, make all entries
of the pdp point to the scratch pdp before mapping (and make all its entries
point to the scratch page); this is to be safe in case of out of bound
access or proactive prefetch.
Systems without LLC require an explicit flu
v2: Clean up patch after rebases.
v3: gen8_dump_ppgtt for 32b and 48b PPGTT.
v4: Use used_pml4es/pdpes (Akash).
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_debugfs.c | 18
drivers/gpu/drm/i915/i915_gem_gtt.c | 88 +++
Test EXEC_OBJECT_NEEDS_32BADDRESS flag to use reserved 32b segment.
Driver will try to use lower PDPs of each PPGTT for the objects
requiring Wa32bitGeneralStateOffset or Wa32bitInstructionBaseOffset.
Signed-off-by: Michel Thierry
---
tests/gem_ppgtt.c | 90 ++
Use 48b addresses if hw supports it and i915.enable_ppgtt=3.
Note, aliasing PPGTT remains 32b only.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +
drivers/gpu/drm/i915/i915_params.c | 2 +-
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers
gen8_clamp_pd clamps to the next page directory boundary, but the macro
gen8_for_each_pde already has a check to stop at the page directory boundary.
Furthermore, i915_pte_count also restricts to the next page table
boundary.
Suggested-by: Akash Goel
Signed-off-by: Michel Thierry
---
drivers/g
In a 48b world, users can try to allocate buffers bigger than 4GB; in
these cases it is important that size is a 64b variable.
Also added a warning for illegal bind with size = 0.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem.c | 5 +++--
drivers/gpu/drm/i915/i915_gem_gtt.
In 64b (48bit canonical) PPGTT addressing, the PDP0 register contains
the base address to PML4, while the other PDP registers are ignored.
In LRC, the addressing mode must be specified in every context descriptor.
v2: PML4 update in legacy context switch is left for historic reasons,
the preferre
The insert_entries function was the function used to write PTEs. For the
PPGTT it was "hardcoded" to only understand two level page tables, which
was the case for GEN7. We can reuse this for 4 level page tables, and
remove the concept of insert_entries, which was never viable past 2
level page tabl
The dynamic page allocation patch series added it for GEN6, this patch
adds them for GEN8.
v2: Consolidate pagetable/page_directory events
v3: Multiple rebases.
v4: Rebase after s/page_tables/page_table/.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v3+)
---
drivers/gpu/drm/i915/
When 48b is enabled, gen8_ppgtt_insert_entries needs to read the Page Map
Level 4 (PML4), before it selects which Page Directory Pointer (PDP)
it will write to.
Similarly, gen8_ppgtt_clear_range needs to get the correct PDP/PD range.
This patch was inspired by Ben's "Depend exclusively on map and
There are some allocations that must be only referenced by 32bit
offsets. To limit the chances of having the first 4GB already full,
objects not requiring this workaround don't use the first 2 PDPs.
User must pass EXEC_OBJECT_NEEDS_32BADDRESS flag to indicate it needs a
32b address.
The flag is i
As a step towards implementing 4 levels, while not discarding the
existing pte map functions, we need to pass the sg_iter through. The
current function understands to the page directory granularity. An
object's pages may span the page directory, and so using the iter
directly as we write the PTEs a
This transitional patch doesn't do much for the existing code. However,
it should make upcoming patches to use the full 48b address space a bit
easier. The patch also introduces the PML4, ie. the new top level structure
of the page tables.
v2: Renamed pdp_free to be similar to pd/pt (unmap_and_f
In order expand the GPU address space, a 4th level translation is added, the
Page Map Level 4 (PML4). This PML4 has 256 PML4 Entries (PML4E), PML4[0-255],
each pointing to a PDP. All the existing "dynamic alloc ppgtt" functions are
used, only adding the 4th level changes. I also updated some remain
Up until now, ppgtt->pdp has always been the root of our page tables.
Legacy 32b addresses acted like it had 1 PDP with 4 PDPEs.
In preparation for 4 level page tables, we need to stop use ppgtt->pdp
directly unless we know it's what we want. The future structure will use
ppgtt->pml4 for the top l
Add a make file for android so the unit tests can be built.
Enabled asserts for the library code so the unit test behaviour
is correct.
Signed-off-by: Derek Morton
---
lib/Android.mk | 4 +++-
lib/tests/Android.mk | 41 +
2 files changed, 44 inserti
It was reported that this comment was confusing, and indeed it is.
v2: (one year later!) Add the range for the DRM_I915_* iotcl defines
(Daniel)
Signed-off-by: Damien Lespiau
---
include/uapi/drm/i915_drm.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/
2015-05-26 8:13 GMT-03:00 Thomas Wood :
> On 25 May 2015 at 22:40, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> This is a new test that should exercise the frontbuffer tracking
>> feature of the Kernel in a number of different ways. We use different
>> drawing methods, we use the primary, curs
On Tue, May 26, 2015 at 02:38:44PM +0200, Thierry Reding wrote:
> On Wed, May 20, 2015 at 04:53:53PM +0200, Daniel Vetter wrote:
> > Unfortunately old userspace didn't clear this properly, but since
> > we've added fb modifiers that's fixed. Checking properly that unused
> > fields is important for
On Wed, May 20, 2015 at 04:53:53PM +0200, Daniel Vetter wrote:
> Unfortunately old userspace didn't clear this properly, but since
> we've added fb modifiers that's fixed. Checking properly that unused
> fields is important for abi extensions, and just right now there's a
> bunch of discussions goi
The lib changes ensure the following:
1) Get the value of rc property during igt_display_init
2) Set the value of rc property during do_display_commit
3) Add supporting method to set rc property from kms_test
Signed-off-by: Mayuresh Gharpure
---
lib/igt_kms.c | 40 +++
BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.
v2: Adding clock in bxt_clk_div struct and then look for the entry with
required rate (Ville)
v3: 'clock' has the selected value, no need to use link_b
On Sat, 23 May 2015, Antti Koskipaa wrote:
> This is a basic sanity test of the backlight sysfs interface.
>
> Issue: VIZ-3377
> Signed-off-by: Antti Koskipaa
> ---
> tests/.gitignore | 1 +
> tests/Makefile.sources | 1 +
> tests/pm_backlight.c | 144
> +
On 25 May 2015 at 22:40, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> This is a new test that should exercise the frontbuffer tracking
> feature of the Kernel in a number of different ways. We use different
> drawing methods, we use the primary, cursor and sprite planes, we can
> test both on sin
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Chris Wilson
> Sent: Saturday, May 23, 2015 5:11 PM
> To: Mika Kuoppala
> Cc: intel-gfx@lists.freedesktop.org; m...@iki.fi
> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915: Let hardware kee
tree: git://anongit.freedesktop.org/drm-intel for-linux-next
head: 568797315ef0b293630a76d1c8cb5e88c667e66e
commit: 568797315ef0b293630a76d1c8cb5e88c667e66e [92/92] drm/i915/bxt: edp1.4
Intermediate Freq support
config: i386-randconfig-ib0-05261733 (attached as .config)
reproduce:
git checko
On 5/26/2015 3:29 PM, Daniel Vetter wrote:
On Tue, May 26, 2015 at 12:57:26PM +0300, Jani Nikula wrote:
On Tue, 26 May 2015, Daniel Vetter wrote:
On Tue, May 26, 2015 at 02:51:38PM +0530, Sonika Jindal wrote:
BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz,
On Tue, May 26, 2015 at 11:56:18AM +0200, Daniel Vetter wrote:
> On Tue, May 26, 2015 at 09:49:15AM +0100, Chris Wilson wrote:
> > On Tue, May 26, 2015 at 10:01:24AM +0200, Daniel Vetter wrote:
> > > On Mon, May 25, 2015 at 06:48:44PM +0100, Chris Wilson wrote:
> > > > Since the advent of mmap(wc),
On Tue, May 26, 2015 at 12:57:26PM +0300, Jani Nikula wrote:
> On Tue, 26 May 2015, Daniel Vetter wrote:
> > On Tue, May 26, 2015 at 02:51:38PM +0530, Sonika Jindal wrote:
> >> BXT supports following intermediate link rates for edp:
> >> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> >> Adding support for
On Tue, 26 May 2015, Daniel Vetter wrote:
> On Tue, May 26, 2015 at 02:51:38PM +0530, Sonika Jindal wrote:
>> BXT supports following intermediate link rates for edp:
>> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
>> Adding support for programming the intermediate rates.
>>
>> v2: Adding clock in bxt_clk_
On Tue, May 26, 2015 at 09:49:15AM +0100, Chris Wilson wrote:
> On Tue, May 26, 2015 at 10:01:24AM +0200, Daniel Vetter wrote:
> > On Mon, May 25, 2015 at 06:48:44PM +0100, Chris Wilson wrote:
> > > Since the advent of mmap(wc), where we reused the same cache domain for
> > > WC and GTT paths (oh,
On Tue, 26 May 2015, Sonika Jindal wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
>
> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> required rate (Ville)
> v
On Tue, May 26, 2015 at 02:51:38PM +0530, Sonika Jindal wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
>
> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> requ
BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.
v2: Adding clock in bxt_clk_div struct and then look for the entry with
required rate (Ville)
v3: 'clock' has the selected value, no need to use link_b
On Tue, May 26, 2015 at 10:01:24AM +0200, Daniel Vetter wrote:
> On Mon, May 25, 2015 at 06:48:44PM +0100, Chris Wilson wrote:
> > Since the advent of mmap(wc), where we reused the same cache domain for
> > WC and GTT paths (oh, how I regret that double-edged advice), we need to
> > be extra cautio
On Tue, May 26, 2015 at 10:20:26AM +0200, Daniel Vetter wrote:
> On Tue, May 26, 2015 at 08:57:13AM +0100, Chris Wilson wrote:
> > On Tue, May 26, 2015 at 07:47:22AM +0200, Daniel Vetter wrote:
> > > This reverts commit 118182e9d7d5afa0c7c10f568afb46ab78b462e9.
> > >
> > > It's causing too much tr
This needs to be a global check because at the time of crtc checking
not all modesets have to be calculated yet. Use intel_crtc->atomic
because there's no reason to keep it in state.
Changes since v1:
- Use intel_crtc->atomic as a place to put hsw_workaround_pipe.
- Make sure quirk only applies
Assume the callers lock everything with drm_modeset_lock_all.
This change had to be done after converting suspend/resume to
use atomic_state so the atomic state is preserved, otherwise
all transitional state is erased.
Now all callers of .crtc_enable and .crtc_disable go through
atomic modeset! :
Calculate all state using a normal transition, but afterwards fudge
crtc->state->active back to its old value. This should still allow
state restore in setup_hw_state to work properly.
Calling intel_set_mode will cause intel_display_set_init_power to be
called, make sure init_power gets set again
This is a function used to disable all crtc's. This makes it clearer
to distinguish between when mode needs to be preserved and when
it can be trashed.
Changes since v1:
- Copy power changes from intel_crtc_control.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_drv.c | 4
On Tue, May 26, 2015 at 10:19:50AM +0300, Jani Nikula wrote:
> On Tue, 26 May 2015, Daniel Vetter wrote:
> > On Mon, May 25, 2015 at 01:25:56PM +0300, Jani Nikula wrote:
> >> On Fri, 22 May 2015, Uma Shankar wrote:
> >> > + * but DDI interface doesn't support DSI yet, so don't do
> >> >
On 22 May 2015 at 19:48, Daniel Vetter wrote:
> Hi all,
>
> New -testing cycle with cool stuff:
> - cpt modeset sequence fixes from Ville
> - more rps boosting tuning from Chris
> - S3 support for skl (Damien)
> - a pile of w/a for bxt from various people
> - cleanup of primary plane pixel formats
On Tue, May 26, 2015 at 08:57:13AM +0100, Chris Wilson wrote:
> On Tue, May 26, 2015 at 07:47:22AM +0200, Daniel Vetter wrote:
> > This reverts commit 118182e9d7d5afa0c7c10f568afb46ab78b462e9.
> >
> > It's causing too much trouble when compile-testing for non-i915 folks.
>
> What's the argument a
On Thu, May 21, 2015 at 5:30 PM, Daniel Vetter wrote:
> On Thu, May 21, 2015 at 04:22:55PM +0100, Chris Wilson wrote:
>> On Thu, May 21, 2015 at 04:21:46PM +0200, Daniel Vetter wrote:
>> > Hm right. What about emphasising this a bit more in the comment:
>> >
>> > /*
>> > * Empirical evide
On Mon, May 25, 2015 at 06:48:44PM +0100, Chris Wilson wrote:
> Since the advent of mmap(wc), where we reused the same cache domain for
> WC and GTT paths (oh, how I regret that double-edged advice), we need to
> be extra cautious when using GTT iomap_wc internally. Since userspace maybe
> modifyin
On Tue, May 26, 2015 at 07:47:22AM +0200, Daniel Vetter wrote:
> This reverts commit 118182e9d7d5afa0c7c10f568afb46ab78b462e9.
>
> It's causing too much trouble when compile-testing for non-i915 folks.
What's the argument against using COMPILE_TEST as a proxy for detecting
all(yes|mod)config as i
On Fri, May 22, 2015 at 09:04:12PM +0200, Thomas Richter wrote:
> Hi folks,
>
> this is re-submitting the intel DVO patch that closes bug #49838, namely
> that resuming from suspend-to-RAM on the IBM x30 leaves the laptop with
> a blank screen. See the attached patch for details.
>
> Please let m
On Tue, 26 May 2015, Daniel Vetter wrote:
> On Mon, May 25, 2015 at 01:25:56PM +0300, Jani Nikula wrote:
>> On Fri, 22 May 2015, Uma Shankar wrote:
>> > + * but DDI interface doesn't support DSI yet, so don't do anything
>> > + * for DSI encoders
>> > + */
>> > + if (!(HAS_DDI(dev) && has_
On Fri, May 22, 2015 at 08:18:46PM +0300, Mika Kuoppala wrote:
> According to bspec, with ring mode scheduling on gen >= 8,
> we need to disable ring idle message before writing zero to
> Ring Buffer Enable.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
On Fri, May 22, 2015 at 08:04:57PM +0300, Mika Kuoppala wrote:
> We can have exactly 4GB sized ppgtt with 32bit system.
> size_t is inadequate for this.
>
Is there a
v2: Convert a lot more places (Daniel)
missing here? The patch looks a lot bigger, but not sure ...
-Daniel
> Signed-off-by: Mik
On Mon, May 25, 2015 at 01:25:56PM +0300, Jani Nikula wrote:
> On Fri, 22 May 2015, Uma Shankar wrote:
> > +* but DDI interface doesn't support DSI yet, so don't do anything
> > +* for DSI encoders
> > +*/
> > + if (!(HAS_DDI(dev) && has_encoder_ddi(type))) {
>
> HAS_DDI() is always
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