On Thu, Apr 30, 2015 at 08:43:13PM -0700, Chandra Konduru wrote:
> This patch updates baseline bpp when primary plane
> is running with NV12. It is same as 8-bpc RGB formats
> because NV12 also has 8-bits per channel.
>
> Signed-off-by: Chandra Konduru
This code was removed in
commit d328c9d78d
On Thu, Apr 30, 2015 at 08:43:10PM -0700, Chandra Konduru wrote:
> This patch adds NV12 to list of supported formats for
> primary plane.
>
> Signed-off-by: Chandra Konduru
> Testcase: igt/kms_nv12
> ---
> drivers/gpu/drm/i915/intel_display.c | 32 +++-
> 1 file cha
On Wed, May 06, 2015 at 03:51:52PM +0530, ankitprasad.r.sha...@intel.com wrote:
> From: Ankitprasad Sharma
>
> This patch adds the testcases for verifying the new extended
> gem_create ioctl. By means of this extended ioctl, memory
> placement of the GEM object can be specified, i.e. either
> shm
On Fri, May 01, 2015 at 08:11:39PM -0700, Chandra Konduru wrote:
> From: chandra konduru
>
> This patch adds kms_nv12 test case. It covers testing NV12 in
> all supported linear/tile-X/tile-Y/tile-Yf tile formats in
> 0 and 180 orientations. For each tiling format, it tests
> various combinations
On Wed, May 06, 2015 at 03:01:30PM +0100, daniele.ceraolospu...@intel.com wrote:
> From: Daniele Ceraolo Spurio
>
> Using imported objects should not leak i915 vmas (and vms).
>
> In practice this simulates Xorg importing fbcon and leaking (or not) one vma
> per Xorg startup cycle.
>
> v2: use
On Wed, May 06, 2015 at 03:05:04PM +0300, Imre Deak wrote:
> On ke, 2015-05-06 at 14:28 +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Do a POSTING_READ() between the DBUF_CTL register write and the
> > udelay() to make sure we really wait after the register write has
On Wed, May 06, 2015 at 07:32:08PM +0300, Imre Deak wrote:
> On Wed, 2015-05-06 at 17:01 +0100, Nick Hoath wrote:
> > On 29/04/2015 14:02, Deak, Imre wrote:
> > > On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote:
> > >> Signed-off-by: Nick Hoath
> > >> ---
> > >> drivers/gpu/drm/i915/intel_rin
BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to
VCO frequencies. Program i_lockthresh in PORT_PLL_9.
VCO calculated based on the formula:
Desired Output = Port bit rate in MHz (DisplayPort HBR2 is 5400 MHz)
Fast Clock = Desired Output / 2
VCO = Fast Clock * P1 * P2
Prop
Making lane stagger calculation common for HDMI and DP
Signed-off-by: Vandana Kannan
---
drivers/gpu/drm/i915/intel_ddi.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 49b9fd8.
Oh great then :)
Thanks,
Sonika
-Original Message-
From: R, Durgadoss
Sent: Thursday, May 7, 2015 11:19 AM
To: Jindal, Sonika; intel-gfx@lists.freedesktop.org
Subject: RE: [PATCH] Removing redundant is_edp_psr
>-Original Message-
>From: Jindal, Sonika
>Sent: Thursday, May 7, 201
>-Original Message-
>From: Jindal, Sonika
>Sent: Thursday, May 7, 2015 9:58 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Jindal, Sonika; R, Durgadoss
>Subject: [PATCH] Removing redundant is_edp_psr
>
>Since we already store the sink's psr status in dev_priv, use it.
>Without this we were ig
Hi all,
After merging the drm-intel tree, today's linux-next build (i386 defconfig)
produced this warning:
drivers/gpu/drm/i915/i915_gem_gtt.c: In function 'gen8_ppgtt_init':
drivers/gpu/drm/i915/i915_gem_gtt.c:954:22: warning: large integer implicitly
truncated to unsigned type [-Woverflow]
p
Since we already store the sink's psr status in dev_priv, use it.
Without this we were ignoring the case where sink supports psr2.
Cc: Durgadoss R
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/intel_psr.c |7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drive
BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/intel_ddi.c | 44 --
drivers/gpu/drm/i915/intel_dp.c |
The sink rate read from supported link rate table is in KHz as per spec
while in drm, the saved clock is in deca-KHz. So divide the link rate by
10 before storing.
Cc: Ville Syrjälä
Signed-off-by: Sonika Jindal
---
Just resending it along with the other intermediate link rate patches
(It was pos
Renaming gen9_rates to skl_rates because other platforms may have different
supported rates.
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/intel_dp.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/in
On 5/6/2015 8:35 PM, Jani Nikula wrote:
On Mon, 04 May 2015, Vandana Kannan wrote:
Changes based on future platform readiness patches related to
HAS_PCH_SPLIT(). Use HAS_GMCH_DISPLAY() instead of HAS_PCH_SPLIT.
This needs an update to reflect the patch.
BXT does not have PP_DIV register.
The values that ultimately get passed to
intel_update_sprite_watermarks() are pulled out of the plane state
(which has already been swapped into plane->state) as we update the
plane programming. Drop the function parameters and just pull the
relevant values out of the state structure inside the fu
We never removed the sprite watermark updates from our low-level
foo_update_plane() functions; since our hardware updates happen under
vblank evasion, we're not supposed to be calling potentially sleeping
functions there (since interrupts are disabled). Ensure that we
properly set the atomic.updat
Our atomic transaction maintains a bitmask of planes that we need to
update sprite watermarks for once vblank evasion is complete. When we
actually go to make use of that bitmask, we've been comparing against
the plane index rather than the plane mask; we need to update our
comparison to check '(1
Hi,
This error happens when crtc_state in driver not matching with hardware
registers.
On skylake board that I have, I am not able to reproduce the issue.
Can you send the system configuration and steps to reproduce the issue?
Also can you send the full dmesg.log file?
-Chandra
> -Original M
> @@ -1765,14 +1765,6 @@ void igt_plane_set_fb(igt_plane_t *plane, struct
> igt_fb *fb)
> plane->fb = fb;
> /* hack to keep tests working that don't call igt_plane_set_size() */
> if (fb) {
> - plane->crtc_w = fb->width;
> - plane->crtc_h = fb->height;
>
> -Original Message-
> From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com]
> Sent: Tuesday, May 05, 2015 2:53 AM
> To: Intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko; Konduru, Chandra; Wood, Thomas
> Subject: [PATCH v2 i-g-t 1/4] igt_kms: Avoid NULL ptr deref when commitin
On Sun, Dec 21, 2014 at 14:47:58 +, Chris Wilson wrote:
> Snapshot 2.99.917 (2014-12-21)
> ==
> 3 months drifted by whilst I looked elsewhere for bugs.. The highlight of
> bugs fixed here are a couple of workarounds required for Broadwell and
> making sure that the
> diff --git a/lib/igt_kms.c b/lib/igt_kms.c index b5ba273..0665d70 100644
> --- a/lib/igt_kms.c
> +++ b/lib/igt_kms.c
> @@ -1765,9 +1765,7 @@ void igt_plane_set_fb(igt_plane_t *plane, struct
> igt_fb *fb)
> plane->fb = fb;
> /* hack to keep tests working that don't call igt_plane_set_
> -Original Message-
> From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com]
> Sent: Wednesday, May 06, 2015 2:29 AM
> To: Konduru, Chandra; Intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko; Wood, Thomas
> Subject: Re: [PATCH i-g-t 4/4] kms_plane_scaling: Find the image regard
On Wednesday, May 06, 2015 08:25:28 PM Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > On Wed, May 06, 2015 at 03:38:44PM +0200, Daniel Vetter wrote:
> >> On Tue, Apr 21, 2015 at 10:13:31PM -0700, Kenneth Graunke wrote:
> >> > The BLT engine on Gen8+ requires linear surfaces to be cacheline
> >
Chris Wilson writes:
> On Wed, May 06, 2015 at 03:38:44PM +0200, Daniel Vetter wrote:
>> On Tue, Apr 21, 2015 at 10:13:31PM -0700, Kenneth Graunke wrote:
>> > The BLT engine on Gen8+ requires linear surfaces to be cacheline
>> > aligned. This restriction was added as part of converting the BLT t
On Wed, 2015-05-06 at 17:01 +0100, Nick Hoath wrote:
> On 29/04/2015 14:02, Deak, Imre wrote:
> > On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote:
> >> Signed-off-by: Nick Hoath
> >> ---
> >> drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
> >> 1 file changed, 5 insertions(+)
> >>
> >> di
On 29/04/2015 14:02, Deak, Imre wrote:
On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote:
Signed-off-by: Nick Hoath
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ring
On 05/05/2015 17:18, Deak, Imre wrote:
On ti, 2015-05-05 at 15:20 +0100, Nick Hoath wrote:
On 29/04/2015 15:35, Deak, Imre wrote:
On pe, 2015-03-20 at 09:29 +, Nick Hoath wrote:
This stepping isn't listed separately in the specs, so needs confirmation.
Signed-off-by: Nick Hoath
---
dr
This was accidentally lost in
commit 75d04a3773ecee617847de963ae4195d6aa74c28
Author: Mika Kuoppala
Date: Tue Apr 28 17:56:17 2015 +0300
drm/i915/gtt: Allocate va range only if vma is not bound
While at it implement an improved version suggested by Chris which
avoids the double-bind irres
On Wed, May 06, 2015 at 04:49:36PM +0200, Linus Walleij wrote:
> On Wed, Apr 29, 2015 at 3:59 PM, Shobhit Kumar
> wrote:
>
> > In case we unload and load a driver module again that is registering a
> > lookup table, without this it will result in multiple entries. Provide
> > an option to remove
On Mon, 04 May 2015, Vandana Kannan wrote:
> Changes based on future platform readiness patches related to
> HAS_PCH_SPLIT(). Use HAS_GMCH_DISPLAY() instead of HAS_PCH_SPLIT.
This needs an update to reflect the patch.
> BXT does not have PP_DIV register. Making changes to handle this.
> Second s
On Wed, Apr 29, 2015 at 4:00 PM, Shobhit Kumar wrote:
> On some Intel SoC platforms, the panel enable/disable signals are
> controlled by CRC PMIC. Add those control as a new GPIO in a lookup
> table for gpio-crystalcove chip during CRC driver load
>
> v2: Make the lookup table static (Thierry)
>
On Wed, Apr 29, 2015 at 3:59 PM, Shobhit Kumar wrote:
> In case we unload and load a driver module again that is registering a
> lookup table, without this it will result in multiple entries. Provide
> an option to remove the lookup table on driver unload
>
> v2: Ccing maintainers
>
> Cc: Samuel
This adds a dispatcher for extending drm ioctl debugging info and adds
the i915 ioctls to the xlat framework.
Signed-off-by: Patrik Jakobsson
---
Makefile.am | 2 +
defs.h | 2 +
drm.c | 104
drm_
Signed-off-by: Patrik Jakobsson
---
drm_i915.c | 235 +
xlat/drm_i915_getparams.in | 28 ++
xlat/drm_i915_setparams.in | 4 +
3 files changed, 267 insertions(+)
create mode 100644 xlat/drm_i915_getparams.in
create mode 100644 xl
This patch set aims to make strace more useful when tracing i915 ioctls.
The ioctl type is first checked for being drm and then the driver
backing the opened device is identified by looking at sysfs. Other
drivers than i915 can easily be added.
Only a subset of the i915 ioctls are included. I will
On Wed, May 06, 2015 at 04:44:13PM +0300, Ville Syrjälä wrote:
> On Wed, May 06, 2015 at 02:36:27PM +0100, Damien Lespiau wrote:
> > Robert noticed that the FF_SLICE_CS_CHICKEN2 offset was wrong. Ooops.
> >
> > Ville noticed that the write was wrong since FF_SLICE_CS_CHICKEN2 is a
> > masked regis
On Thu, Mar 26, 2015 at 02:17:25PM +, Damien Lespiau wrote:
> On Wed, Mar 25, 2015 at 07:27:16PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Replace the hardcoded 9 with a call to intel_freq_opcode(450).
> >
> > Signed-off-by: Ville Syrjälä
>
> Reviewed-by:
On Wed, May 06, 2015 at 05:35:48PM +0530, Sonika Jindal wrote:
> This provides an option to override the value set by VBT
> for selecting edp Vswing Pre-emph setting table.
>
> v2: Adding comment about this being a temporary workaround and
> making the parameter read-only (Jani)
> v3: Changing mod
On Wed, May 06, 2015 at 04:11:11PM +0300, Jani Nikula wrote:
> On Wed, 29 Apr 2015, Shobhit Kumar wrote:
> > The CRC (Crystal Cove) PMIC, controls the panel enable and disable
> > signals for BYT for dsi panels. This is indicated in the VBT fields. Use
> > that to initialize and use GPIO based con
On Wed, May 06, 2015 at 02:51:47PM +0300, Imre Deak wrote:
> On ti, 2015-05-05 at 15:24 +0100, Nick Hoath wrote:
> > On 29/04/2015 13:26, Deak, Imre wrote:
> > > On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote:
> > >> Signed-off-by: Nick Hoath
> > >> ---
> > >> drivers/gpu/drm/i915/i915_reg.h
From: Daniele Ceraolo Spurio
Using imported objects should not leak i915 vmas (and vms).
In practice this simulates Xorg importing fbcon and leaking (or not) one vma
per Xorg startup cycle.
v2: use low-level ioctl wrappers and bo offset to check the leak (Chris)
v3: use the flinked bo as batch
On Wed, May 06, 2015 at 03:38:44PM +0200, Daniel Vetter wrote:
> On Tue, Apr 21, 2015 at 10:13:31PM -0700, Kenneth Graunke wrote:
> > The BLT engine on Gen8+ requires linear surfaces to be cacheline
> > aligned. This restriction was added as part of converting the BLT to
> > use 48-bit addressing.
On Wed, May 06, 2015 at 02:36:27PM +0100, Damien Lespiau wrote:
> Robert noticed that the FF_SLICE_CS_CHICKEN2 offset was wrong. Ooops.
>
> Ville noticed that the write was wrong since FF_SLICE_CS_CHICKEN2 is a
> masked register. Re-oops.
>
> A wonder if went through 2 people while having roughly
On Wed, 29 Apr 2015, Shobhit Kumar wrote:
> Use the CRC PWM device in intel_panel.c and add new MIPI backlight
> specififc callbacks
>
> v2: Modify to use pwm_config callback
>
> CC: Samuel Ortiz
> Cc: Linus Walleij
> Cc: Alexandre Courbot
> Cc: Thierry Reding
> Signed-off-by: Shobhit Kumar
>
On Tue, Apr 21, 2015 at 10:13:31PM -0700, Kenneth Graunke wrote:
> The BLT engine on Gen8+ requires linear surfaces to be cacheline
> aligned. This restriction was added as part of converting the BLT to
> use 48-bit addressing.
>
> intel_emit_linear_blit needs to handle blits that are not cacheli
Robert noticed that the FF_SLICE_CS_CHICKEN2 offset was wrong. Ooops.
Ville noticed that the write was wrong since FF_SLICE_CS_CHICKEN2 is a
masked register. Re-oops.
A wonder if went through 2 people while having roughly a bug per line...
The problem was introduced in the original patch:
com
On ke, 2015-05-06 at 14:29 +0100, Chris Wilson wrote:
> On Wed, May 06, 2015 at 04:22:23PM +0300, Joonas Lahtinen wrote:
> > On ke, 2015-05-06 at 14:15 +0100, Chris Wilson wrote:
> > > On Wed, May 06, 2015 at 03:31:10PM +0300, Joonas Lahtinen wrote:
> > > >
> > > > Use pread right after moving out
On Wed, May 06, 2015 at 04:22:23PM +0300, Joonas Lahtinen wrote:
> On ke, 2015-05-06 at 14:15 +0100, Chris Wilson wrote:
> > On Wed, May 06, 2015 at 03:31:10PM +0300, Joonas Lahtinen wrote:
> > >
> > > Use pread right after moving out of CPU domain to verify all
> > > writes flushed correctly.
> >
On ke, 2015-05-06 at 14:15 +0100, Chris Wilson wrote:
> On Wed, May 06, 2015 at 03:31:10PM +0300, Joonas Lahtinen wrote:
> >
> > Use pread right after moving out of CPU domain to verify all
> > writes flushed correctly.
>
> Wrong test, see gem_pread. Adding extra work may have the unintended
> si
On Mon, May 4, 2015 at 7:19 PM, Paulo Zanoni wrote:
> It seems the problem is happening because we're now trying 12bpc
> instead of 8bpc, and 12bpc is broken for HDMI. In fact, 12bpc was
> already broken before this patch, the problem is that this patch is
> now trying to use it. It even generates
On Wed, May 06, 2015 at 02:04:50PM +0100, Damien Lespiau wrote:
> Robert noticed that the FF_SLICE_CS_CHICKEN2 offset was wrong. Ooops.
>
> The problem was introduced in the original patch:
>
> commit 2caa3b260aa6a3d015352c07d1bce1461825fa6c
> Author: Damien Lespiau
> Date: Mon Feb 9 19:
On Wed, May 06, 2015 at 03:31:10PM +0300, Joonas Lahtinen wrote:
>
> Use pread right after moving out of CPU domain to verify all
> writes flushed correctly.
Wrong test, see gem_pread. Adding extra work may have the unintended
side-effects of masking bugs. If you want to mix access modes, call it
On Wed, 29 Apr 2015, Shobhit Kumar wrote:
> The CRC (Crystal Cove) PMIC, controls the panel enable and disable
> signals for BYT for dsi panels. This is indicated in the VBT fields. Use
> that to initialize and use GPIO based control for these signals.
>
> v2: Use the newer gpiod interface(Alexand
On Fri, Apr 24, 2015 at 5:33 PM, Shobhit Kumar wrote:
> The CRC (Crystal Cove) PMIC, controls the panel enable and disable
> signals for BYT for dsi panels. This is indicated in the VBT fields. Use
> that to initialize and use GPIO based control for these signals.
>
> v2: Use the newer gpiod inte
On Fri, Apr 24, 2015 at 5:33 PM, Shobhit Kumar wrote:
> On some Intel SoC platforms, the panel enable/disable signals are
> controlled by CRC PMIC. Add those control as a new GPIO in a lookup
> table for gpio-crystalcove chip during CRC driver load
>
> v2: Make the lookup table static (Thierry)
>
Robert noticed that the FF_SLICE_CS_CHICKEN2 offset was wrong. Ooops.
The problem was introduced in the original patch:
commit 2caa3b260aa6a3d015352c07d1bce1461825fa6c
Author: Damien Lespiau
Date: Mon Feb 9 19:33:20 2015 +
drm/i915/skl: Implement WaDisableChickenBitTSGBarrierA
On 05/06/2015 12:34 PM, Joonas Lahtinen wrote:
Do not skip special GGTT views when considering whether an object
is pinned or not.
Wrong behaviour was introduced in;
commit ec7adb6ee79c8c9fe64d63ad638a31cd62e55515
Author: Joonas Lahtinen
Date: Mon Mar 16 14:11:13 2015 +0200
drm/i915:
Do no expose invalid gmbus pins as i2c devices to userspace.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_i2c.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 76070c4e76b3..92072f56e418 100644
Do no expose invalid gmbus pins as i2c devices to userspace.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_i2c.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 3daa7e322326..76070c4e76b3 10064
On 05/06/2015 12:36 PM, Joonas Lahtinen wrote:
Use partial view for huge BOs (bigger than half the mappable aperture)
in fault handler so that they can be accessed withough trying to make
room for them by evicting other objects.
v2:
- Only use partial views in the case where early rejection w
Use pread right after moving out of CPU domain to verify all
writes flushed correctly.
Due to extended usage, add own buffer.
Signed-off-by: Joonas Lahtinen
---
tests/gem_mmap_gtt.c | 28 +---
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/tests/gem_mmap
On 05/06/2015 12:35 PM, Joonas Lahtinen wrote:
Partial view type allows manipulating parts of huge BOs through the GGTT,
which was not previously possible due to constraint that whole object had
to be mapped for any access to it through GGTT.
v2:
- Retain error value from sg_alloc_table (Tvrt
On 05/06/2015 12:33 PM, Joonas Lahtinen wrote:
GGTT VMA sizes might be smaller than the whole object size due to
different GGTT views.
v2:
- Separate GGTT view constraint calculations from normal view
constraint calculations (Chris Wilson)
v3:
- Do not bother with debug wording. (Tvrtko Ursu
On Tue, May 05, 2015 at 03:04:18PM +0530, Shobhit Kumar wrote:
> In case some drivers are unloading, they can remove lookup tables which
> they would have registered during their load time to avoid redundant
> entries if loaded again
>
> v2: Ccing maintainers
> v3: Correct the subject line (Lee jo
On Tue, May 05, 2015 at 03:08:36PM +0530, Shobhit Kumar wrote:
> The Crystalcove PMIC controls PWM signals and this driver exports that
You say signal_s_ here, but you only expose a single PWM device. Does
the PMIC really control more than one? If it isn't, this should probably
become: "controls a
This provides an option to override the value set by VBT
for selecting edp Vswing Pre-emph setting table.
v2: Adding comment about this being a temporary workaround and
making the parameter read-only (Jani)
v3: Changing mode to 0400 instead of 0 (Jani)
https://bugs.freedesktop.org/show_bug.cgi?id
On ke, 2015-05-06 at 14:28 +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Do a POSTING_READ() between the DBUF_CTL register write and the
> udelay() to make sure we really wait after the register write has
> happened.
>
> Spotted while reviewing Damien's SKL cdclk patch wh
On ti, 2015-05-05 at 15:24 +0100, Nick Hoath wrote:
> On 29/04/2015 13:26, Deak, Imre wrote:
> > On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote:
> >> Signed-off-by: Nick Hoath
> >> ---
> >> drivers/gpu/drm/i915/i915_reg.h | 1 +
> >> drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +
On to, 2015-04-30 at 13:03 +0100, Tvrtko Ursulin wrote:
> On 04/30/2015 12:19 PM, Joonas Lahtinen wrote:
> >
> > GGTT VMA sizes might be smaller than the whole object size due to
> > different GGTT views.
> >
> > v2:
> > - Separate GGTT view constraint calculations from normal view
> >constrain
On ke, 2015-05-06 at 12:20 +0200, Daniel Vetter wrote:
> On Thu, Apr 30, 2015 at 01:16:30PM +0100, Tvrtko Ursulin wrote:
> > On 04/30/2015 12:20 PM, Joonas Lahtinen wrote:
> > >@@ -495,7 +503,10 @@ i915_ggtt_view_equal(const struct i915_ggtt_view *a,
> > > if (WARN_ON(!a || !b))
> > > r
Use partial view for huge BOs (bigger than half the mappable aperture)
in fault handler so that they can be accessed withough trying to make
room for them by evicting other objects.
v2:
- Only use partial views in the case where early rejection was
previously done.
- Account variable type chang
GGTT VMA sizes might be smaller than the whole object size due to
different GGTT views.
v2:
- Separate GGTT view constraint calculations from normal view
constraint calculations (Chris Wilson)
v3:
- Do not bother with debug wording. (Tvrtko Ursulin)
v4:
- Clearer logic for calculating map_and_fe
Do not skip special GGTT views when considering whether an object
is pinned or not.
Wrong behaviour was introduced in;
commit ec7adb6ee79c8c9fe64d63ad638a31cd62e55515
Author: Joonas Lahtinen
Date: Mon Mar 16 14:11:13 2015 +0200
drm/i915: Do not use ggtt_view with (aliasing) PPGTT
Cc: Dan
Partial view type allows manipulating parts of huge BOs through the GGTT,
which was not previously possible due to constraint that whole object had
to be mapped for any access to it through GGTT.
v2:
- Retain error value from sg_alloc_table (Tvrtko Ursulin)
- Do not zero already zeroed variable (
On ti, 2015-05-05 at 10:07 +0100, Tvrtko Ursulin wrote:
> On 05/04/2015 12:51 PM, Joonas Lahtinen wrote:
> > On to, 2015-04-30 at 15:54 +0100, Tvrtko Ursulin wrote:
> >> On 04/30/2015 12:21 PM, Joonas Lahtinen wrote:
> >>>
> >>> Use partial view for huge BOs (bigger than the mappable aperture)
> >>
From: Ville Syrjälä
Do a POSTING_READ() between the DBUF_CTL register write and the
udelay() to make sure we really wait after the register write has
happened.
Spotted while reviewing Damien's SKL cdclk patch which had the
POSTING_READ()s.
Cc: Imre Deak
Signed-off-by: Ville Syrjälä
---
drive
On Tue, May 05, 2015 at 05:17:32PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Use POSTING_READ() in intel_sdvo_write_sdvox() as appropriate.
>
> Signed-off-by: Ville Syrjälä
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_sdvo.c |
On Tue, May 05, 2015 at 02:33:39PM +0300, Jani Nikula wrote:
> On Tue, 05 May 2015, Vandana Kannan wrote:
> > Enabling BLC on BXT.
> > Includes register definition, and new functions for BXT.
> >
> > In BXT, there are 2 sets of registers for BLC. Until there is clarity
> > about which set would be
On Tue, May 05, 2015 at 09:17:29AM +0100, Chris Wilson wrote:
> [ 1572.417121] BUG: unable to handle kernel NULL pointer dereference at
> (null)
> [ 1572.421010] IP: []
> ftrace_raw_event_i915_context+0x5d/0x70 [i915]
> [ 1572.424970] PGD 1766a3067 PUD 1767a2067 PMD 0
> [ 1572.428892] O
On Tue, May 05, 2015 at 09:56:02PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 30, 2015 at 04:39:21PM +0100, Damien Lespiau wrote:
> > +static void
> > +skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int
> > required_vco)
> > +{
> > + unsigned int min_freq;
> > + u32 val;
> > +
> >
On Mon, May 04, 2015 at 05:44:11PM +0300, Mika Kuoppala wrote:
> wa_batchbuffer is part of some error states. Make sure it
> is freed.
>
> Signed-off-by: Mika Kuoppala
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
> 1 file changed, 1 inser
On Tue, May 05, 2015 at 11:03:28AM +0530, Sivakumar Thulasimani wrote:
> Reviewed-by: Sivakumar Thulasimani
>
> On 5/4/2015 7:50 PM, Jani Nikula wrote:
> >We should no longer enter the codec enable/disable functions in question
> >with port A anyway, but to err on the safe side, keep the warnings
On Tue, May 05, 2015 at 04:32:12PM +0300, Jani Nikula wrote:
> On Tue, 05 May 2015, Sivakumar Thulasimani
> wrote:
> > two points
> > 1) The eDP spec says Audio is optional so it is allowed to have audio,
> > but i am yet to come across any eDP panel that supports Audio.
> > 2) Also, there is no
Adding Chandra, who's implemented skl scaler code.
-Daniel
On Sat, May 02, 2015 at 10:05:42AM +0900, Sergey Senozhatsky wrote:
> Hi,
>
> linux-next 20150501
>
> [1.968953] [drm:check_crtc_state [i915]] *ERROR* mismatch in
> scaler_state.scaler_id (expected 0, found -1)
> [1.968953]
On Wed, May 06, 2015 at 12:53:14PM +0200, Daniel Vetter wrote:
> On Thu, Apr 30, 2015 at 04:39:22PM +0100, Damien Lespiau wrote:
> > Signed-off-by: Damien Lespiau
>
> Why? I.e. way too terse commit message.
Because I couldn't get the PCU to answer to the handcheck we should be
doing. Ville notic
On Wed, May 06, 2015 at 12:54:23PM +0200, Daniel Vetter wrote:
> On Thu, Apr 30, 2015 at 04:39:23PM +0100, Damien Lespiau wrote:
> > Signed-off-by: Damien Lespiau
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/drivers/
On Thu, Apr 30, 2015 at 04:39:23PM +0100, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f637667..25
On Thu, Apr 30, 2015 at 04:39:22PM +0100, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau
Why? I.e. way too terse commit message.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/int
I merged all the preceding patches to dinq. This one starts to conflict,
since dmc code landed meanwhile.
On Thu, Apr 30, 2015 at 04:39:21PM +0100, Damien Lespiau wrote:
> We need to re-init the display hardware when going out of suspend. This
> includes:
>
> - Hooking the PCH to the reset logi
From: Ankitprasad Sharma
This patch adds the testcases for verifying the new extended
gem_create ioctl. By means of this extended ioctl, memory
placement of the GEM object can be specified, i.e. either
shmem or stolen memory.
These testcases include functional tests and interface tests for
testin
From: Ankitprasad Sharma
This patch adds support for extending the pread/pwrite functionality
for objects not backed by shmem. The access will be made through
gtt interface.
This will cover prime objects as well as stolen memory backed objects
but for userptr objects it is still forbidden.
v2: d
From: Chris Wilson
If we run out of stolen memory when trying to allocate an object, see if
we can reap enough purgeable objects to free up enough contiguous free
space for the allocation. This is in principle very much like evicting
objects to free up enough contiguous space in the vma when bind
From: Ankitprasad Sharma
Extend the drm_i915_gem_create structure to add support for
creating Stolen memory backed objects. Added a new flag through
which user can specify the preference to allocate the object from
stolen memory, which if set, an attempt will be made to allocate
the object from s
From: Ankitprasad Sharma
This patch adds support for clearing buffer objects via blitter
engines. This is particularly useful for clearing out the memory
from stolen region.
v2: Add support for using execlists & PPGTT
v3: Fix issues in legacy ringbuffer submission mode
testcase: igt/gem_create
On Wed, 06 May 2015, Sonika Jindal wrote:
> This provides an option to override the value set by VBT
> for selecting edp Vswing Pre-emph setting table.
>
> v2: Adding comment about this being a temporary workaround and
> making the parameter read-only (Jani)
>
> https://bugs.freedesktop.org/show_b
From: Ankitprasad Sharma
This patch series adds support for creating/using Stolen memory backed
objects.
Despite being a unified memory architecture (UMA) some bits of memory
are more equal than others. In particular we have the thorny issue of
stolen memory, memory stolen from the system by the
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