On Mon, 2015-05-04 at 15:56 +0200, Daniel Vetter wrote:
> On Mon, Apr 27, 2015 at 07:52:46PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 23, 2015 at 03:07:56PM +0100, Peter Antoine wrote:
> > > If an application that has a driver lock created, wants the lock the
> > > kernel context, it is not allo
On Mon, 2015-05-04 at 15:52 +0200, Daniel Vetter wrote:
> On Tue, Apr 28, 2015 at 10:52:32AM +0100, ch...@chris-wilson.co.uk wrote:
> > On Tue, Apr 28, 2015 at 10:21:49AM +0100, Dave Gordon wrote:
> > > On 24/04/15 06:52, Antoine, Peter wrote:
> > > > I picked up this work due to the following Jira
Reviewed-by: Sivakumar Thulasimani
On 5/4/2015 7:50 PM, Jani Nikula wrote:
We should no longer enter the codec enable/disable functions in question
with port A anyway, but to err on the safe side, keep the warnings. Just
bail out early without messing with the registers.
Signed-off-by: Jani Ni
On 5/4/2015 7:50 PM, Jani Nikula wrote:
The eDP port A register on PCH split platforms has a slightly different
register layout from the other ports, with bit 6 being either alternate
scrambler reset or reserved, depending on the generation. Our
misinterpretation of the bit as audio has lead to
Reviewed-by: Sivakumar Thulasimani
On 5/4/2015 8:50 PM, Vandana Kannan wrote:
BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to
VCO frequencies. Program i_lockthresh in PORT_PLL_9.
VCO calculated based on the formula:
Desired Output = Port bit rate in MHz (DisplayPort
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6287
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
From: "Lu, Han"
In SKL, HDMI/DP codec and PCH HD Audio Controller are in different power wells,
so it's necessary to reset display audio codecs when power well on, otherwise
display audio codecs will disappear when resume from low power state.
Reset steps when power on:
enable codec wakeup ->
From: "Lu, Han"
Add support for enabling codec wakeup override signal to allow
re-enumeration of the controller on SKL after resume from low power state.
In SKL, HDMI/DP codec and PCH HD Audio Controller are in different power
wells, so it's necessary to reset display audio codecs when power wel
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6314
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
> Sent: Monday, May 04, 2015 8:01 AM
> To: Konduru, Chandra
> Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel; Syrjala, Ville
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Adding dbuf
>
> Iirc it was in the ddx, and it was actually using the mmap code. Leftovers
> from ums, but unfortunately X crashes if we take them away. If I recall
> correctly nouveau was in staging still, but per Linus staging or not
> doesn't matter when distros are shipping with the code already. I did dig
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6313
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6312
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6311
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
2015-05-04 5:34 GMT-03:00 Daniel Vetter :
> On Thu, Apr 30, 2015 at 10:43:39AM -0300, Paulo Zanoni wrote:
>> 2015-04-15 8:06 GMT-03:00 Ander Conselvan De Oliveira :
>> > Reviewed-by: Ander Conselvan de Oliveira
>> >
>> > On Fri, 2015-04-10 at 16:22 +0200, Daniel Vetter wrote:
>> >> Since universal
On Mon, May 04, 2015 at 10:12:23AM +0200, Daniel Vetter wrote:
> On Mon, May 04, 2015 at 10:58:02AM +0530, Deepak S wrote:
> >
> >
> > On Wednesday 29 April 2015 02:59 PM, Ville Syrjälä wrote:
> > >On Wed, Apr 29, 2015 at 08:36:24AM +0530, deepa...@linux.intel.com wrote:
> > >>From: Deepak S
> >
On Mon, May 04, 2015 at 05:44:12PM +0300, Mika Kuoppala wrote:
> If we have chained batch, the request only contains
> the batch buffer that branched the execution into chained
> batch. We can try to find object for actual head and
> if it is different than the object from request, record
> and pri
On Tue, Apr 28, 2015 at 03:30:54PM +0300, Jani Nikula wrote:
> Produce the intel_reg man page from rst using rst2man. Also facilitate
> writing any man page in reStructured text, as long as rst2man is
> available.
>
> v2: configure check for rst2man, credits to Thomas Wood for that.
>
> Signed-of
On Tue, Apr 28, 2015 at 03:04:26PM +0300, Jani Nikula wrote:
> Signed-off-by: Jani Nikula
> ---
> lib/intel_io.h | 4
> lib/intel_mmio.c | 24
> 2 files changed, 28 insertions(+)
>
> diff --git a/lib/intel_io.h b/lib/intel_io.h
> index 04aa3fd496b4..1c3b4445cd5b
On Tue, Apr 28, 2015 at 05:21:30PM +0300, Jani Nikula wrote:
> On Tue, 28 Apr 2015, han...@intel.com wrote:
> > From: "Lu, Han"
> >
> > In SKL, HDMI/DP codec and PCH HD Audio Controller are in different
> > power wells, so it's necessary to reset display audio codecs when
> > power well on, otherw
On Mon, May 04, 2015 at 05:44:12PM +0300, Mika Kuoppala wrote:
> + obj = find_obj_for_addr(dev, error->ring[i].acthd);
> + if (request && request->batch_obj == obj)
> + obj = NULL;
> +
> + if (obj) {
> + if (vm && !i915_gem
On Tue, Apr 28, 2015 at 08:48:03AM +0100, Chris Wilson wrote:
> This is the wrong layer to apply an arbitrary restriction and the wrong
> error code (object too large!). If we do want to prevent large offsets
> being return to the user on 32bit systems (to hide bugs in userspace),
> you want to res
On Mon, Apr 27, 2015 at 03:47:37PM -0700, Chandra Konduru wrote:
> Skylake nv12 format requires dbuf (aka. ddb) calculations
> and programming for each of y and uv sub-planes. Made minor
> changes to reuse current dbuf calculations and programming
> for uv plane. i.e., with this change, existing co
On Mon, May 04, 2015 at 04:51:24PM +0200, Daniel Vetter wrote:
> On Mon, Apr 27, 2015 at 01:41:27PM +0100, Chris Wilson wrote:
> > Ignore the restriction imposed by the user for when the GPU is stalling
> > the clients and dropping frames. We will return back to the user limits
> > immediately once
BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to
VCO frequencies. Program i_lockthresh in PORT_PLL_9.
VCO calculated based on the formula:
Desired Output = Port bit rate in MHz (DisplayPort HBR2 is 5400 MHz)
Fast Clock = Desired Output / 2
VCO = Fast Clock * P1 * P2
Prop
Hi Ville,
> I would suggest splitting that into a separate patch. Otherwise it's
> going to harder to revert either change separately, should the need
> arise. So that part is
> Reviewed-by: Ville Syrjälä
Okay, commit split in two as requested.
Question:
Daniel Vetter hardcoded the MacBookPro8
On Wed, Apr 29, 2015 at 12:39:17PM +0100, Chris Wilson wrote:
>
> On Wed, Apr 29, 2015 at 02:07:19PM +0300, David Weinehall wrote:
> > On Tue, Apr 28, 2015 at 03:46:46PM +0100, Chris Wilson wrote:
> > > On Tue, Apr 28, 2015 at 02:38:25PM +, Antoine, Peter wrote:
> > > > So is the plan to push
On Mon, Apr 27, 2015 at 01:41:27PM +0100, Chris Wilson wrote:
> Ignore the restriction imposed by the user for when the GPU is stalling
> the clients and dropping frames. We will return back to the user limits
> immediately once the stall is over.
>
> Signed-off-by: Chris Wilson
Unsure about thi
Updates the EDID compliance test function to perform the analyze and react to
the EDID data read as a result of a hot plug event. The results of this
analysis are handed off to userspace so that the userspace app can set the
display mode appropriately for the test result/response.
The compliance_t
If we have chained batch, the request only contains
the batch buffer that branched the execution into chained
batch. We can try to find object for actual head and
if it is different than the object from request, record
and print its state also.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i9
wa_batchbuffer is part of some error states. Make sure it
is freed.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index ac22614..a3e330d 100
On Mon, May 04, 2015 at 04:38:02PM +0200, Daniel Vetter wrote:
> On Mon, Apr 27, 2015 at 01:41:20PM +0100, Chris Wilson wrote:
> > Ring switches can occur many times per frame, and are often out of
> > control, causing frequent RPS boosting for no practical benefit. Treat
> > the sw semaphore synch
On Mon, Apr 27, 2015 at 01:41:20PM +0100, Chris Wilson wrote:
> Ring switches can occur many times per frame, and are often out of
> control, causing frequent RPS boosting for no practical benefit. Treat
> the sw semaphore synchronisation as a separate client and only allow it
> to boost once per b
On Mon, Apr 27, 2015 at 01:41:19PM +0100, Chris Wilson wrote:
> Expose some more of our internal RPS bookkeeping for debugging.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 25 +
> 1 file changed, 21 insertions(+), 4 deletions(-)
>
> diff
On Mon, Apr 27, 2015 at 10:43:19AM +0300, Jani Nikula wrote:
> On Sat, 25 Apr 2015, Fabian Frederick wrote:
> > Inspired by scripts/coccinelle/api/err_cast.cocci
> >
> > Signed-off-by: Fabian Frederick
>
> Reviewed-by: Jani Nikula
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vett
On Mon, May 04, 2015 at 04:21:20PM +0200, Daniel Vetter wrote:
> On Mon, May 04, 2015 at 04:14:41PM +0200, Daniel Vetter wrote:
> > On Thu, Apr 23, 2015 at 12:54:37PM +0100, Chris Wilson wrote:
> > > Since
> > >
> > > commit 43566dedde54f9729113f5f9fde77d53e75e61e9
> > > Author: Chris Wilson
> >
On Fri, Apr 24, 2015 at 06:07:05PM +, Konduru, Chandra wrote:
>
>
> > -Original Message-
> > From: Konduru, Chandra
> > Sent: Friday, April 24, 2015 10:53 AM
> > To: 'Tvrtko Ursulin'; Intel-gfx@lists.freedesktop.org
> > Cc: Ursulin, Tvrtko
> > Subject: RE: [PATCH] drm/i915/skl: Bypass
Single channel LVDS maxes out at 112 MHz, anything above must be dual
channel. This avoids the need to specify i915.lvds_channel_mode=2 on
all 17" MacBook Pro models with i915 graphics since they had 1920x1200
(193 MHz), plus those 15" pre-retina models which had a resolution
of 1680x1050 (119 MHz)
Single channel LVDS maxes out at 112 MHz. The 15" pre-retina models
shipped with 1440x900 (106 MHz) by default or 1680x1050 (119 MHz)
as a BTO option, both versions used dual channel LVDS even though
the smaller one would have fit into a single channel.
Signed-off-by: Lukas Wunner
Acked-by: Jani
On Mon, Apr 27, 2015 at 01:55:15PM +0100, Tvrtko Ursulin wrote:
>
> On 04/24/2015 01:09 PM, Joonas Lahtinen wrote:
> >Do not to clear mappings outside the allocated VMA under any
> >circumstances. Only clear the smaller of VMA or object page count.
> >
> >This is required to allow creating partial
On Mon, May 04, 2015 at 04:14:41PM +0200, Daniel Vetter wrote:
> On Thu, Apr 23, 2015 at 12:54:37PM +0100, Chris Wilson wrote:
> > Since
> >
> > commit 43566dedde54f9729113f5f9fde77d53e75e61e9
> > Author: Chris Wilson
> > Date: Fri Jan 2 16:29:29 2015 +0530
> >
> > drm/i915: Broaden applic
The eDP port A register on PCH split platforms has a slightly different
register layout from the other ports, with bit 6 being either alternate
scrambler reset or reserved, depending on the generation. Our
misinterpretation of the bit as audio has lead to warnings.
Fix this by not enabling audio o
We should no longer enter the codec enable/disable functions in question
with port A anyway, but to err on the safe side, keep the warnings. Just
bail out early without messing with the registers.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_audio.c | 20
1 file
On Fri, Apr 24, 2015 at 11:06:10AM +0300, Mika Kahola wrote:
> This patch adds information on current CD clock
> frequency to debugfs i915_frequency_info
>
> Signed-off-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/driver
On Thu, Apr 30, 2015 at 12:22:56PM +0100, Chris Wilson wrote:
> On Thu, Apr 30, 2015 at 01:28:46PM +0300, Joonas Lahtinen wrote:
> > On ma, 2015-04-27 at 20:43 +0100, Chris Wilson wrote:
> > > On Mon, Apr 27, 2015 at 06:35:54PM +0100, Thomas Wood wrote:
> > > > On 24 April 2015 at 08:38, Joonas Lah
On Thu, Apr 23, 2015 at 12:54:37PM +0100, Chris Wilson wrote:
> Since
>
> commit 43566dedde54f9729113f5f9fde77d53e75e61e9
> Author: Chris Wilson
> Date: Fri Jan 2 16:29:29 2015 +0530
>
> drm/i915: Broaden application of set-domain(GTT)
>
> we allowed objects to be in the GTT domain, but u
On Tue, Apr 28, 2015 at 01:29:21PM +, Antoine, Peter wrote:
> On Tue, 2015-04-28 at 16:08 +0300, Ville Syrjälä wrote:
> > On Tue, Apr 28, 2015 at 11:29:06AM +, Antoine, Peter wrote:
> > > > > > diff --git a/include/drm/drmP.h b/include/drm/drmP.h index
> > > > > > 62c40777..367e42f 100644
On Mon, Apr 27, 2015 at 07:52:46PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 23, 2015 at 03:07:56PM +0100, Peter Antoine wrote:
> > If an application that has a driver lock created, wants the lock the
> > kernel context, it is not allowed to. If the call to drm_lock has a
> > context of 0, it is re
On Tue, Apr 28, 2015 at 10:52:32AM +0100, ch...@chris-wilson.co.uk wrote:
> On Tue, Apr 28, 2015 at 10:21:49AM +0100, Dave Gordon wrote:
> > On 24/04/15 06:52, Antoine, Peter wrote:
> > > I picked up this work due to the following Jira ticket created by the
> > > security team (on Android) and was
On Tue, Apr 28, 2015 at 09:28:51AM +, Antoine, Peter wrote:
> On Mon, 2015-04-27 at 16:33 +0100, Chris Wilson wrote:
> > On Mon, Apr 27, 2015 at 04:24:37PM +0100, Thomas Wood wrote:
> > > On 23 April 2015 at 15:07, Peter Antoine wrote:
> > > > There are several issues with the hardware locks f
On Wed, Apr 22, 2015 at 01:24:20PM +0200, maarten.lankho...@linux.intel.com
wrote:
> From: Maarten Lankhorst
A bit more explanation in the commit message here would be useful, i.e.
what changed that we need this now.
-Daniel
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/i9
I've fumbled this in
commit f02ad907cd9e7fe3a6405d2d005840912f1ed258
Author: Daniel Vetter
Date: Thu Jan 22 16:36:23 2015 +0100
drm/atomic-helpers: Recover full cursor plane behaviour
and accidentally put the assignment for legacy_cursor_upate after the
atomic commit, where it is pretty u
On Fri, Apr 24, 2015 at 09:31:56AM +0100, Tvrtko Ursulin wrote:
>
> On 04/23/2015 08:15 PM, Daniel Vetter wrote:
> >On Tue, Apr 21, 2015 at 01:18:57PM +0100, Tvrtko Ursulin wrote:
> >>On 04/21/2015 11:07 AM, Chris Wilson wrote:
> >>>On Tue, Apr 21, 2015 at 11:01:03AM +0100, Tvrtko Ursulin wrote:
>
On Thu, Apr 30, 2015 at 03:30:10PM -0300, Paulo Zanoni wrote:
> 2015-04-18 4:04 GMT-03:00 Todd Previte :
> > Updates the EDID compliance test function to perform the analyze and react
> > to
> > the EDID data read as a result of a hot plug event. The results of this
> > analysis are handed off to
On Thu, Apr 16, 2015 at 02:22:06PM +0530, Animesh Manna wrote:
> v4:
> - Removed all warning by reordering the patchsets.
> - Changed the dmc firmware file name skl_dmc_ver1.bin, followed naming
> conventipon as _dmc_.bin
>
> v3:
> MOdified the code of patch 1 and 3 based on review commets.
>
>
On Thu, Apr 16, 2015 at 02:22:11PM +0530, Animesh Manna wrote:
> From: Suketu Shah
>
> Add triggers for DC6 as per details provided in skl_enable_dc6
> and skl_disable_dc6 implementations.
>
> Also Call POSTING_READ for every write to a register to ensure
> it is written to immediately
>
> v1:
On Thu, Apr 30, 2015 at 02:59:34PM +0100, Michel Thierry wrote:
> The patch 69876bed7e008f5fe01538a2d47c09f2862129d0: "drm/i915/gen8:
> page directories rework allocation" added an overflow warning, but the
> mask had an extra 0. Use typo-prone option suggested by Dave instead.
I think you mean "l
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6310
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Wed, Apr 29, 2015 at 10:59:20PM +0530, Animesh Manna wrote:
> From: "A.Sunil Kamath"
>
> Display Context Save and Restore support is needed for
> various SKL Display C states like DC5, DC6.
>
> This implementation is added based on first version of DMC CSR program
> that we received from h/w
At Mon, 04 May 2015 10:49:15 +0300,
Jani Nikula wrote:
>
> On Mon, 04 May 2015, "Lu, Han" wrote:
> > Hi Takashi,
> >
> > Our target is to apply the patches into intel-drm-nightly tree, It
> > will be great if you can help merge the patches into your
> > tree. However I get a negative test result
On to, 2015-04-30 at 15:54 +0100, Tvrtko Ursulin wrote:
> On 04/30/2015 12:21 PM, Joonas Lahtinen wrote:
> >
> > Use partial view for huge BOs (bigger than the mappable aperture)
> > in fault handler so that they can be accessed without trying to make
> > room for them by evicting other objects.
>
On Mon, 04 May 2015, Martin Kepplinger wrote:
> So. -rc1 broke suspending by closing my laptop lid and it's not fixed in
> -rc2. It works exactly *one* first time and every subsequent lid-closing
> is ignored.
>
> Biscted and tested first bad commit:
> 14aa02449064541217836b9f3d3295e241d5ae9c
>
>
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6309
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On ma, 2015-05-04 at 11:30 +0200, Daniel Vetter wrote:
> On Thu, Apr 30, 2015 at 04:02:34PM +0300, Imre Deak wrote:
> > On ke, 2015-04-29 at 22:59 +0530, Animesh Manna wrote:
> > > From: "A.Sunil Kamath"
> > >
> > > Display Context Save and Restore support is needed for
> > > various SKL Display
Hi,
linux-next 20150501
[1.968953] [drm:check_crtc_state [i915]] *ERROR* mismatch in
scaler_state.scaler_id (expected 0, found -1)
[1.968953] [ cut here ]
[1.968983] WARNING: CPU: 0 PID: 6 at
drivers/gpu/drm/i915/intel_display.c:12008 check_crtc_state+0xb15/0
On Thu, Apr 16, 2015 at 02:22:11PM +0530, Animesh Manna wrote:
> From: Suketu Shah
>
> Add triggers for DC6 as per details provided in skl_enable_dc6
> and skl_disable_dc6 implementations.
>
> Also Call POSTING_READ for every write to a register to ensure
> it is written to immediately
>
> v1:
On Fri, Apr 17, 2015 at 07:46:16PM +0530, Animesh Manna wrote:
> From: Suketu Shah
>
> Add triggers as per expectations mentioned in gen9_enable_dc5
> and gen9_disable_dc5 patch.
>
> Also call POSTING_READ for every write to a register to ensure that
> its written immediately.
>
> v1: Remove PO
On Thu, Apr 30, 2015 at 04:02:34PM +0300, Imre Deak wrote:
> On ke, 2015-04-29 at 22:59 +0530, Animesh Manna wrote:
> > From: "A.Sunil Kamath"
> >
> > Display Context Save and Restore support is needed for
> > various SKL Display C states like DC5, DC6.
> >
> > This implementation is added based
On Mon, May 04, 2015 at 10:54:14AM +0200, Daniel Vetter wrote:
> i915_needs_cmd_parser already checks that for us.
>
> Suggested-by: Reviewed-by: Mika Kuoppala
Oops, r-b obviously shouldn't be here, copypasta-fail.
-Daniel
> Cc: Reviewed-by: Mika Kuoppala
> Signed-off-by: Daniel Vetter
> ---
On Mon, May 04, 2015 at 10:06:51AM +0100, Chris Wilson wrote:
> On Mon, May 04, 2015 at 10:49:30AM +0200, Daniel Vetter wrote:
> > On Fri, Apr 24, 2015 at 12:55:57PM +0100, Chris Wilson wrote:
> > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > >
On Mon, May 04, 2015 at 10:49:30AM +0200, Daniel Vetter wrote:
> On Fri, Apr 24, 2015 at 12:55:57PM +0100, Chris Wilson wrote:
> > On Fri, Apr 24, 2015 at 12:14:17PM +0100, Chris Wilson wrote:
> > > On Mon, Apr 20, 2015 at 09:04:05AM -0700, Daniel Vetter wrote:
> > > > Currently we have the problem
i915_needs_cmd_parser already checks that for us.
Suggested-by: Reviewed-by: Mika Kuoppala
Cc: Reviewed-by: Mika Kuoppala
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_
On Fri, Apr 24, 2015 at 12:55:57PM +0100, Chris Wilson wrote:
> On Fri, Apr 24, 2015 at 12:14:17PM +0100, Chris Wilson wrote:
> > On Mon, Apr 20, 2015 at 09:04:05AM -0700, Daniel Vetter wrote:
> > > Currently we have the problem that the decision whether ptes need to
> > > be (re)written is splatte
On Tue, 21 Apr 2015, Mika Kuoppala wrote:
> Reading from disconnected ports will spit out timeout error
> on the dmesg. Skip the attempted read if the port is not
> connected and avoid confusing users/testcases about
> expected timeouts.
>
> This new dpcd debugfs entry was introduced by commit aa7
On Thu, Apr 30, 2015 at 10:43:39AM -0300, Paulo Zanoni wrote:
> 2015-04-15 8:06 GMT-03:00 Ander Conselvan De Oliveira :
> > Reviewed-by: Ander Conselvan de Oliveira
> >
> > On Fri, 2015-04-10 at 16:22 +0200, Daniel Vetter wrote:
> >> Since universal planes the primary plane might not be around, an
On Wed, Apr 29, 2015 at 03:16:29PM +0300, Imre Deak wrote:
> On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote:
> > Signed-off-by: Nick Hoath
>
> Reviewed-by: Imre Deak
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_
On Mon, Apr 27, 2015 at 05:13:49AM +, Konduru, Chandra wrote:
>
>
> > -Original Message-
> > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> > Vetter
> > Sent: Thursday, April 23, 2015 1:20 PM
> > To: Konduru, Chandra
> > Cc: intel-gfx@lists.freedesktop.org;
On Mon, May 04, 2015 at 10:58:02AM +0530, Deepak S wrote:
>
>
> On Wednesday 29 April 2015 02:59 PM, Ville Syrjälä wrote:
> >On Wed, Apr 29, 2015 at 08:36:24AM +0530, deepa...@linux.intel.com wrote:
> >>From: Deepak S
> >>
> >>Based on the spec, Setting up static BIAS for GPU to improve the
> >>
On Wed, Apr 29, 2015 at 08:23:21AM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> After feedback from the hardware team, now we set the GPU min/idel freq to
> RPe.
> Punit is expecting us to operate GPU between Rpe & Rp0. If we drop the
> frequency to RPn, punit is failing to change
On Thu, Apr 30, 2015 at 03:34:32PM +0530, Deepak S wrote:
>
>
> On Wednesday 29 April 2015 03:56 PM, Ville Syrjälä wrote:
> >On Wed, Apr 29, 2015 at 08:20:20AM +0530, Deepak S wrote:
> >>
> >>On Wednesday 29 April 2015 12:02 AM, Ville Syrjälä wrote:
> >>>On Tue, Apr 28, 2015 at 11:16:29AM -0700,
On Mon, Apr 27, 2015 at 08:33:38PM +, Konduru, Chandra wrote:
> > -Original Message-
> > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > Sent: Monday, April 27, 2015 8:28 AM
> > On Fri, Feb 20, 2015 at 04:11:33PM -0800, Chandra Konduru wrote:
> > > This patch adds support
Hi Jani,
Thanks for review.
Hi Takashi,
Should we re-send the patch to ALSA mailing list?
> -Original Message-
> From: Nikula, Jani
> Sent: Monday, May 04, 2015 3:49 PM
> To: Lu, Han; Takashi Iwai
> Cc: Vetter, Daniel; Yang, Libin; Lin, Mengdong; intel-
> g...@lists.freedesktop.org
> Su
On Mon, 04 May 2015, "Lu, Han" wrote:
> Hi Takashi,
>
> Our target is to apply the patches into intel-drm-nightly tree, It
> will be great if you can help merge the patches into your
> tree. However I get a negative test result on BYT platform auto test,
> I'll confirm if it's caused by my patches
Please submit patches to intel-gfx, not just to me in private. Adding the
list. I did test-apply the patch, and this applies cleanly. Thanks for
fixing up your setup.
-Daniel
On Thu, Apr 30, 2015 at 10:07:54PM +0200, Thomas Richter wrote:
> From af7f1b8da36808a7369c0e209fc3de7f567b46b5 Mon Sep 17
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