This patch adds DP link training optimization by reusing the
previously trained values.
v2:
- rebase
V3:
- rebase
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm
This is patch series optimizes DP link training by reusing
the link parameter settings if DP link has bee previously
trained. In case we are not able to train the link by reusing
the known values, the link training parameters are set
to zero and training is restarted.
The first patch is for eDP on
This is a first of series patches that optimize DP link
training. The first patch is for eDP only where we reuse
the previously trained link training values from cache
i.e. voltage swing and pre-emphasis levels.
In case we are not able to train the link by reusing
the known values, the link traini
Hi,
(replies inline)
-Original Message-
From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
Sent: Monday, April 27, 2015 6:04 PM
To: Antoine, Peter
Cc: intel-gfx@lists.freedesktop.org; airl...@redhat.com;
dri-de...@lists.freedesktop.org; daniel.vet...@ffwll.ch
Subject: Re: [Intel
Skylake nv12 format requires dbuf (aka. ddb) calculations
and programming for each of y and uv sub-planes. Made minor
changes to reuse current dbuf calculations and programming
for uv plane. i.e., with this change, existing computation
is used for either packed format or uv portion of nv12
dependin
On Mon, Apr 27, 2015 at 04:34:05PM +0100, Tvrtko Ursulin wrote:
> +static void prepare_crtc(data_t *data, igt_output_t *output, enum pipe pipe,
> + igt_plane_t *plane)
> +{
> + drmModeModeInfo *mode;
> + igt_display_t *display = &data->display;
> + int fb_id, fb_mod
This patch enables skylake primary plane scaling using shared
scalers atomic desgin.
v2:
-use single copy of scaler limits (Matt)
v3:
-move detach_scalers to crtc commit path (Matt)
-use values in plane_state->src as regular integers (me)
v4:
-changes to align with updated scaler structures (Mat
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Monday, April 27, 2015 8:28 AM
> On Fri, Feb 20, 2015 at 04:11:33PM -0800, Chandra Konduru wrote:
> > This patch adds support for Skylake display pipe background color.
> > + Background color in 16bp
On Mon, Apr 27, 2015 at 06:35:54PM +0100, Thomas Wood wrote:
> On 24 April 2015 at 08:38, Joonas Lahtinen
> wrote:
> > Now that there is PAGE_SIZE define, use it.
>
> Thanks, I've pushed this patch. I also noticed PAGE_SIZE gets defined
> in several tests, so at some point it might be worth movin
Hi Daniel, hi Ville,
as promised, I was recently able to borrow an X30 that - similar to the
R31 - features the intel DVO VCH. As Ville mentioned, this notebook
suffers from bug #49838, namely the screen is blank after a resume from
suspend.
With some debugging, I was able to resolve this pr
On 27/04/15 16:32, Chris Wilson wrote:
> drivers/gpu/drm/i915/intel_dvo.c: In function ‘intel_dvo_init’:
> drivers/gpu/drm/i915/intel_dvo.c:531:8: warning: array subscript is above
> array bounds [-Warray-bounds]
I found this one too, so:
Reviewed-by: Dave Gordon
> Signed-off-by: Chris Wilson
On 23/04/15 17:54, Yunlian Jiang wrote:
> The bug entry is at
> https://code.google.com/p/chromium/issues/detail?id=476001
>
> The patch below makes clang happy.
>
> debugger/eudb.c | 6 +-
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/debugger/eudb.c b/debugger/eudb.c
>
On 24 April 2015 at 08:38, Joonas Lahtinen
wrote:
> Now that there is PAGE_SIZE define, use it.
Thanks, I've pushed this patch. I also noticed PAGE_SIZE gets defined
in several tests, so at some point it might be worth moving it into
the library.
>
> Signed-off-by: Joonas Lahtinen
> ---
> tes
On 23 April 2015 at 10:41, Jindal, Sonika wrote:
> Thanks Tvrtko.
> This series makes kms_rotation_crc much cleaner :)
>
> Reviewed-by: Sonika Jindal
Thanks, I've pushed the whole series.
>
>
>
> On 4/22/2015 9:16 PM, Tvrtko Ursulin wrote:
>>
>> From: Tvrtko Ursulin
>>
>> Saves a good amount
On Fri, Apr 17, 2015 at 07:31:22PM +0300, Imre Deak wrote:
> At the moment intel_prepare_ddi buffer will iterate through both MST and
> CRT encoders, which is incorrect. Neither of these encoder types have an
> embedding intel_digital_port object, so for these encoder types we will
> use random dat
On Fri, Apr 17, 2015 at 07:31:21PM +0300, Imre Deak wrote:
> In the next patch we'll need to get at both the encoder's intel_digital_port
> object - which maybe NULL for a CRT - and it's port, so factor out this
> functionality.
>
> No functional change.
>
> Bugzilla: https://bugs.freedesktop.org
On Mon, Apr 27, 2015 at 06:15:45PM +0100, Damien Lespiau wrote:
> On Mon, Apr 27, 2015 at 06:05:31PM +0100, Damien Lespiau wrote:
> > On Fri, Apr 17, 2015 at 02:58:10PM +0300, Imre Deak wrote:
> > > We should check if a given encoder is of a digital type before casting
> > > it to a digital port ob
On Mon, Apr 27, 2015 at 06:05:31PM +0100, Damien Lespiau wrote:
> On Fri, Apr 17, 2015 at 02:58:10PM +0300, Imre Deak wrote:
> > We should check if a given encoder is of a digital type before casting
> > it to a digital port object. This broke on HSW when iterating the VGA
> > encoder.
> >
> > Int
On Fri, Apr 17, 2015 at 02:58:10PM +0300, Imre Deak wrote:
> We should check if a given encoder is of a digital type before casting
> it to a digital port object. This broke on HSW when iterating the VGA
> encoder.
>
> Introduced in
> commit b403745c84592b26a0713e6944c2b109f6df5c82
> Author: Damie
On Thu, Apr 23, 2015 at 03:07:57PM +0100, Peter Antoine wrote:
> As these functions are only used by one driver and there are security holes
> in these functions. Make the functions optional.
>
> Issue: VIZ-5485
> Signed-off-by: Peter Antoine
> ---
> drivers/gpu/drm/drm_lock.c| 6 ++
On Thu, Apr 23, 2015 at 03:07:56PM +0100, Peter Antoine wrote:
> If an application that has a driver lock created, wants the lock the
> kernel context, it is not allowed to. If the call to drm_lock has a
> context of 0, it is rejected. If you set the context to _DRM_LOCK_CONT
> then call drm lock,
From: Tvrtko Ursulin
Measures DRM_IOCTL_MODE_SETCRTC and DRM_IOCTL_MODE_SETPLANE as proxy for
drm_atomic_helper_update_plane if I got it right.
Discovered some slow cursor updates (1.6ms) so needed something to test
different kernel configs etc.
v2:
* Move to a test case and fail if ioctl ta
On Mon, Apr 27, 2015 at 04:24:37PM +0100, Thomas Wood wrote:
> On 23 April 2015 at 15:07, Peter Antoine wrote:
> > There are several issues with the hardware locks functions that stretch
> > from kernel crashes to priority escalations. This new test will test the
> > the fixes for these features.
drivers/gpu/drm/i915/intel_dvo.c: In function ‘intel_dvo_init’:
drivers/gpu/drm/i915/intel_dvo.c:531:8: warning: array subscript is above array
bounds [-Warray-bounds]
gcc -v
Using built-in specs.
COLLECT_GCC=gcc
COLLECT_LTO_WRAPPER=/usr/lib/gcc/x86_64-linux-gnu/4.7/lto-wrapper
Target: x86_64-lin
On Fri, Feb 20, 2015 at 04:11:33PM -0800, Chandra Konduru wrote:
> This patch adds support for Skylake display pipe background color.
>
> v2:
> - added property documentation to drm DocBook (Daniel Vetter)
> - moved property to drm_mode_config (Daniel Vetter)
> - change to set property to NULL onc
On 23 April 2015 at 15:07, Peter Antoine wrote:
> There are several issues with the hardware locks functions that stretch
> from kernel crashes to priority escalations. This new test will test the
> the fixes for these features.
>
> This test will cause a driver/kernel crash on un-patched kernels,
From: Tim Gore
The call to low_mem_killer_disable(true) was being done
from within function oom_adjust_for_doom. However,
oom_adjust_for_doom gets called from 3 places. We only
want the call to low_mem_killer_disable(true) to happen
during common_init, so call it from here instead of from
oom_adj
On Mon, Apr 27, 2015 at 03:37:30PM +0100, Chris Wilson wrote:
> > I've used e18 for over a year and I never had this problem until the exact
> > moment I upgraded the intel driver.
> > Out of curiosity, even if the bug was with enlightenment, how do I resize
> > my screen once it's been mistakenly
On Mon, Apr 27, 2015 at 04:46:20PM +0300, Joonas Lahtinen wrote:
> In XenGT, when the mappable aperture size is decreased due to slicing of
> the aperture for different guests, it's not about large objects but
> small aperture. And that is the reason why the feature was initially
> implemented, and
Hi,
On 04/24/2015 01:09 PM, Joonas Lahtinen wrote:
Partial view type allows manipulating parts of huge BOs through the GGTT,
which was not previously possible due to constraint that whole object had
to be mapped for any access to it through GGTT.
Signed-off-by: Joonas Lahtinen
---
drivers/
On Mon, Apr 27, 2015 at 07:27:20AM -0700, Marc MERLIN wrote:
> After upgrading to xserver-xorg-video-intel 2:2.99.917-1~exp1 , the
> performance did improve, but twice, I had e18 crash (its fault, not X's
> fault), give me a window that it was going to restart, and when it restarted
> the screen we
On Mon, Apr 27, 2015 at 03:25:14PM +0100, Peter Antoine wrote:
> This patch fixed a timing issue that causes a GPU hang when a the system
> comes out of power saving.
A few more details to explain the timing issue and why this is a fix and
not just papering over the bug.
> Bugzilla: https://bugs
This patch fixed a timing issue that causes a GPU hang when a the system
comes out of power saving.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89600
Signed-off-by: Peter Antoine
---
drivers/gpu/drm/i915/i915_drv.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff
Ignore this. I mean S3/S4 not P3/P4.
-Original Message-
From: Antoine, Peter
Sent: Monday, April 27, 2015 3:25 PM
To: intel-gfx@lists.freedesktop.org
Cc: S, Deepak; Weinehall, David; Tian, YeX; Antoine, Peter
Subject: [PATCH] drm/i915: Avoid GPU hang when coming out of P3 or P4
This patc
This patch fixed a timing issue that causes a GPU hang when a the system
comes out of power saving.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89600
Signed-off-by: Peter Antoine
---
drivers/gpu/drm/i915/i915_drv.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff
After upgrading to xserver-xorg-video-intel 2:2.99.917-1~exp1 , the
performance did improve, but twice, I had e18 crash (its fault, not X's
fault), give me a window that it was going to restart, and when it restarted
the screen went dark.
I went to a text console, and xrandr said this:
Screen 0: m
This patch fixed a timing issue that causes a GPU hang when a the system
comes out of power saving.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89600
Signed-off-by: Peter Antoine
---
drivers/gpu/drm/i915/i915_drv.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff
Hi,
On 04/24/2015 01:09 PM, Joonas Lahtinen wrote:
GGTT VMA sizes might be smaller than the whole object size due to
different GGTT views.
v2:
- Separate GGTT view constraint calculations from normal view
constraint calculations (Chris Wilson)
Cc: Chris Wilson
Signed-off-by: Joonas Lahti
On 24 April 2015 at 16:27, Tvrtko Ursulin
wrote:
> From: Tvrtko Ursulin
>
> Measures DRM_IOCTL_MODE_SETCRTC and DRM_IOCTL_MODE_SETPLANE as proxy for
> drm_atomic_helper_update_plane if I got it right.
>
> Discovered some slow cursor updates (1.6ms) so needed something to test
> different kernel c
On ma, 2015-04-27 at 13:25 +0100, Chris Wilson wrote:
> On Mon, Apr 27, 2015 at 03:12:01PM +0300, Joonas Lahtinen wrote:
> > On ma, 2015-04-27 at 12:21 +0100, Chris Wilson wrote:
> > > On Mon, Apr 27, 2015 at 02:01:59PM +0300, Joonas Lahtinen wrote:
> > > > On pe, 2015-04-24 at 13:33 +0100, Chris W
On Mon, Apr 27, 2015 at 02:26:36PM +0100, Chris Wilson wrote:
> Hmm, you probably could...
>
> Try
> xrandr --newmode v4k 712.34 3840 4152 4576 5312 2160 2161 2164 2235 -HSync
> +Vsync
> xrandr --addmode VIRTUAL1 v4k
> xrandr --output VIRTUAL1 --mode v4k
well, this is a half way through ;) xf
On 23 April 2015 at 17:54, Yunlian Jiang wrote:
> The bug entry is at
> https://code.google.com/p/chromium/issues/detail?id=476001
>
> The patch below makes clang happy.
Thanks for the patch; Ben Widawsky reviewed it and added his
reviewed-by tag. Unfortunately it doesn't apply cleanly because ta
On Mon, Apr 27, 2015 at 01:19:01PM +0200, Lukas Hejtmanek wrote:
> On Fri, Apr 24, 2015 at 02:15:09PM +0100, Chris Wilson wrote:
> > Check panning afterwards? What does xrandr --verbose say before/after?
>
> even with explicit:
> xrandr --output eDP1 --off --fb 3840x2160 --panning 3840x2160
>
> n
On Fri, Apr 24, 2015 at 02:15:09PM +0100, Chris Wilson wrote:
> Check panning afterwards? What does xrandr --verbose say before/after?
even with explicit:
xrandr --output eDP1 --off --fb 3840x2160 --panning 3840x2160
no luck.
looks like you need at least one outout that keeps fb/panning, disconn
On 04/24/2015 01:09 PM, Joonas Lahtinen wrote:
Do not to clear mappings outside the allocated VMA under any
circumstances. Only clear the smaller of VMA or object page count.
This is required to allow creating partial object VMAs which in
turn are needed for partial GGTT views.
Signed-off-by:
As we perform the mmio-flip without any locking and then try to acquire
the struct_mutex prior to dereferencing the request, it is possible for
userspace to queue a new pageflip before the worker can finish clearing
the old state - and then it will clear the new flip request. The result
is that the
Since the remove of the pin-ioctl, we only care about not changing the
cache level on buffers pinned to the hardware as indicated by
obj->pin_display. So we can safely replace i915_gem_object_is_pinned()
here with a plain obj->pin_display check. During rebinding, we will check
sanity checks in case
This is a preparation patch to change the interface over from gen6+ to
any so that we can extend the RPS infrastructure to support earlier
generations in subsequent patches.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +--
drivers/gpu/drm/i915/i915_drv.h | 2 +
Synchronising to an object active on the same ring is a no-op, for the
benefit of execbuffer scheduler. However, for CS flips this means that
we can forgo checking whether the last write request of the object is
actually queued and more importantly whether the cache flush for the
write was emitted.
Currently, we only track the last request globally across all engines.
This prevents us from issuing concurrent read requests on e.g. the RCS
and BCS engines (or more likely the render and media engines). Without
semaphores, we incur costly stalls as we synchronise between rings -
greatly impacting
Refactor the reclocking logic used by RPS on Ironlake to reuse the
infrastructure developed for RPS on Sandybridge+, along with the
waitboosting support for stalled clients and missed frames.
Reported-by: di...@gmx.net
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90137
Signed-off-by: Chr
Since we will often pageflip to an active surface, we will often have to
wait for the surface to be written before issuing the flip. Also we are
likely to wait on that surface in plenty of time before the vblank.
Since we have a mechanism for boosting when a flip misses the expected
vblank, curtain
Ignore the restriction imposed by the user for when the GPU is stalling
the clients and dropping frames. We will return back to the user limits
immediately once the stall is over.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-
We no longer interpolate domains in the same manner, and even if we did,
we should trust setting either of the other write domains would trigger
an invalidation rather than force it. Remove the tweaking of the
read_domains since it serves no purpose and use
i915_gem_object_wait_rendering() directly
This trims a little overhead from the common case of not needing to
synchronize between rings.
v2: execlists is special and likes to duplicate code.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 10 +++---
drivers/gpu/drm/i915/intel_lrc.c | 9 ++
Expose some more of our internal RPS bookkeeping for debugging.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 25 +
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debu
If the client stalls on a congested request, chosen to be 20ms old to
match throttling, allow the client a free RPS boost.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_pm.c | 19 +++---
With the removal of the pin_ioctl, we need only consider
obj->pin_display when looking at available aperture space.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/dr
Now that we have internal clients, rather than faking a whole
drm_i915_file_private just for tracking RPS boosts, create a new struct
intel_rps_client and pass it along when waiting.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 12
drivers/gpu/drm/i915/i915_
Ring switches can occur many times per frame, and are often out of
control, causing frequent RPS boosting for no practical benefit. Treat
the sw semaphore synchronisation as a separate client and only allow it
to boost once per busy/idle cycle.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i91
I have so many outstanding patches, that my smtp relay reject them for
being a spamhost...
These are the simple patches for further tuning RPS to begin with. 5
trivial/bug fixes, a couple of patches for read-read concurrency, and
then 8 patches to both limit the number of RPS boosts on systems wi
If we have clients stalled waiting for requests, ignore the GPU if it
signals that it should downclock due to low load. This helps prevent
the automatic timeout from causing extremely long running batches from
taking even longer.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.
On Mon, Apr 27, 2015 at 03:12:01PM +0300, Joonas Lahtinen wrote:
> On ma, 2015-04-27 at 12:21 +0100, Chris Wilson wrote:
> > On Mon, Apr 27, 2015 at 02:01:59PM +0300, Joonas Lahtinen wrote:
> > > On pe, 2015-04-24 at 13:33 +0100, Chris Wilson wrote:
> > > > On Fri, Apr 24, 2015 at 03:10:20PM +0300,
On pe, 2015-04-24 at 13:29 +0100, Chris Wilson wrote:
> On Fri, Apr 24, 2015 at 03:09:39PM +0300, Joonas Lahtinen wrote:
> > Do not skip special GGTT views when considering whether an object
> > is pinned or not.
> >
> > Wrong behaviour was introduced in;
> >
> > commit ec7adb6ee79c8c9fe64d63ad63
On ma, 2015-04-27 at 12:21 +0100, Chris Wilson wrote:
> On Mon, Apr 27, 2015 at 02:01:59PM +0300, Joonas Lahtinen wrote:
> > On pe, 2015-04-24 at 13:33 +0100, Chris Wilson wrote:
> > > On Fri, Apr 24, 2015 at 03:10:20PM +0300, Joonas Lahtinen wrote:
> > > > Use partial view for huge BOs (bigger tha
commit 53292cdb066950611e5bc2e0eb109c7edb42af78 ("drm/i915: Workaround
to avoid lite restore with HEAD==TAIL") added a check for req0 != null
which is unnecessary.
The only way req0 could be null is if the list was empty, and this is
already addressed at the beginning of execlists_context_unqueue(
From: Tvrtko Ursulin
Test used to call prepare_crtc twice in the plane loop and leaked two
framebuffers per [subtest]x[pipe]x[plane].
What the loops really wants to do, instead of second invocation of
prepare_crtc, is to just turn on the display with the unrotated fb to
verify that the plane pro
On Mon, Apr 27, 2015 at 02:01:59PM +0300, Joonas Lahtinen wrote:
> On pe, 2015-04-24 at 13:33 +0100, Chris Wilson wrote:
> > On Fri, Apr 24, 2015 at 03:10:20PM +0300, Joonas Lahtinen wrote:
> > > Use partial view for huge BOs (bigger than half the mappable aperture)
> > > in fault handler so that t
On pe, 2015-04-24 at 13:33 +0100, Chris Wilson wrote:
> On Fri, Apr 24, 2015 at 03:10:20PM +0300, Joonas Lahtinen wrote:
> > Use partial view for huge BOs (bigger than half the mappable aperture)
> > in fault handler so that they can be accessed withough trying to make
> > room for them by evicting
Inspired by scripts/coccinelle/api/err_cast.cocci
Signed-off-by: Fabian Frederick
---
drivers/gpu/drm/i915/intel_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 897f17d..d52f267 100644
--- a/drive
On Sat, 25 Apr 2015, Fabian Frederick wrote:
> Inspired by scripts/coccinelle/api/err_cast.cocci
>
> Signed-off-by: Fabian Frederick
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_drv.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915
71 matches
Mail list logo
