> -----Original Message-----
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Monday, April 27, 2015 8:28 AM
> On Fri, Feb 20, 2015 at 04:11:33PM -0800, Chandra Konduru wrote:
> > This patch adds support for Skylake display pipe background color.
> > + <td valign="top" >Background color in 16bpc BGR (B-MSB, R-LSB)</td>
>
> I'd prefer to settle on ARGB msb->lsb layout, unless there's already precedent
> for something else. I think it's the most common component order around, and
> so should result in least amount of code to stuff the bits into the hardware
> registers.
To give some background on this, initially using ARGB msb->lsb layout to stuff
bit into hw regs, but changed to BGR msb->lsb per feedback. Before reversing/
respunning, would like to have an agreement. Daniel/Damien, are you ok with
reversing the order to align with hw? Or just keep the way current patch doing?
>
> > +static int intel_crtc_set_property(struct drm_crtc *crtc,
> > + struct drm_property *property, uint64_t val) {
> > + struct drm_device *dev = crtc->dev;
> > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > + int i;
> > +
> > + if (INTEL_INFO(dev)->gen >= 9) {
> > + if (property == dev->mode_config.background_color_property)
> {
> > + uint64_t bottom = 0;
> > +
> > + /* BGR 16bpc ==> RGB 10bpc */
> > + for (i = 0; i < 3; i++)
> > + bottom |= (((val >> (i * 16 + 6)) & 0x3FF) <<
> > ((2 -
> i) * 10));
> > +
> > + intel_crtc->background_color = (uint32_t) bottom;
> > +
> > + skl_crtc_set_background_color(intel_crtc);
> > + }
> > + return 0;
> > + }
> > + return -EINVAL;
> > +}
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