The sink rate read from supported link rate table is in KHz as per spec
while in drm, the saved clock is in deca-KHz. So divide the link rate by
10 before storing.
Cc: Ville Syrjälä
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/intel_dp.c |3 ++-
1 file changed, 2 insertions(+), 1 d
On 4/20/2015 11:14 PM, Daniel Vetter wrote:
On Mon, Apr 20, 2015 at 05:38:20PM +0100, Tvrtko Ursulin wrote:
On 04/20/2015 05:22 PM, Daniel Vetter wrote:
On Mon, Apr 20, 2015 at 04:22:48PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Add Y tiling support to skl_do_mmio_flip.
Signed-o
The hardware is limited to 2^9 - 1 (511) bytes transfers, and current
driver has no protections in case users attempt to do larger transfers.
The code will just stomp over status register and mayhem ensues.
Let's split larger transfers into digestable chunks. Doing this allows
Atmel MXT driver on
Exercises the new blob-creation ioctl, testing lifetimes and behaviour
of user-created blobs, as well as exercising all the invariant
conditions we guarantee from modes exposed as blob properties.
Signed-off-by: Daniel Stone
---
tests/.gitignore | 1 +
tests/Makefile.sources | 1 +
tes
Due to changes in the driver and to support Displayport compliance testing,
the test request and sink IRQ logic has been relocated from
intel_dp_check_link_status to intel_dp_detect. This is because the bulk of the
compliance tests that set the TEST_REQUEST bit in the DEVICE_IRQ field of the
DPCD i
On Mon, Apr 20, 2015 at 8:41 AM, Daniel Vetter wrote:
> On Thu, Apr 16, 2015 at 09:10:11AM -0700, Eric Caruso wrote:
>> On Thu, Apr 16, 2015 at 8:58 AM, Rodrigo Vivi wrote:
>> > I'm not sure that that property will be accepted...
>> > if so it can be changed to toggle, but for now it is informati
Hi Michael,
On Mon, Apr 20, 2015 at 2:28 AM, Michael Burke wrote:
> Hi Rodrigo,
>
> Thank you for your email.
>
> The problem here is that myself and others will be stuck. Our only choices
> are to wait for Ubuntu 15.04 to come out and then install the new version of
> the Intel drivers, or upd
On Mon, Apr 20, 2015 at 01:09:18PM -0700, Yu Dai wrote:
>
>
> On 04/20/2015 12:52 PM, Chris Wilson wrote:
> >On Mon, Apr 20, 2015 at 09:02:20AM -0700, Yu Dai wrote:
> >>
> >>
> >> On 04/18/2015 06:47 AM, Chris Wilson wrote:
> >> >On Fri, Apr 17, 2015 at 02:21:12PM -0700, yu@intel.com wrote:
>
On 04/20/2015 12:52 PM, Chris Wilson wrote:
On Mon, Apr 20, 2015 at 09:02:20AM -0700, Yu Dai wrote:
>
>
> On 04/18/2015 06:47 AM, Chris Wilson wrote:
> >On Fri, Apr 17, 2015 at 02:21:12PM -0700, yu@intel.com wrote:
> >> From: Alex Dai
> >>
> >> All gem objects used by GuC are pinned to ggt
On 04/20/2015 12:43 PM, Chris Wilson wrote:
On Mon, Apr 20, 2015 at 09:07:28AM -0700, Yu Dai wrote:
>
>
> On 04/18/2015 06:48 AM, Chris Wilson wrote:
> >On Fri, Apr 17, 2015 at 02:21:13PM -0700, yu@intel.com wrote:
> >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm
On Mon, Apr 20, 2015 at 09:02:20AM -0700, Yu Dai wrote:
>
>
> On 04/18/2015 06:47 AM, Chris Wilson wrote:
> >On Fri, Apr 17, 2015 at 02:21:12PM -0700, yu@intel.com wrote:
> >> From: Alex Dai
> >>
> >> All gem objects used by GuC are pinned to ggtt space out of range
> >> [0, WOPCM size]. In
On Mon, Apr 20, 2015 at 09:07:28AM -0700, Yu Dai wrote:
>
>
> On 04/18/2015 06:48 AM, Chris Wilson wrote:
> >On Fri, Apr 17, 2015 at 02:21:13PM -0700, yu@intel.com wrote:
> >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> >> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >> index de8c0
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6236
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Mon, Apr 20, 2015 at 05:38:20PM +0100, Tvrtko Ursulin wrote:
>
> On 04/20/2015 05:22 PM, Daniel Vetter wrote:
> >On Mon, Apr 20, 2015 at 04:22:48PM +0100, Tvrtko Ursulin wrote:
> >>From: Tvrtko Ursulin
> >>
> >>Add Y tiling support to skl_do_mmio_flip.
> >>
> >>Signed-off-by: Tvrtko Ursulin
>
On Mon, Apr 20, 2015 at 05:38:20PM +0100, Tvrtko Ursulin wrote:
>
> On 04/20/2015 05:22 PM, Daniel Vetter wrote:
> >On Mon, Apr 20, 2015 at 04:22:48PM +0100, Tvrtko Ursulin wrote:
> >>From: Tvrtko Ursulin
> >>
> >>Add Y tiling support to skl_do_mmio_flip.
> >>
> >>Signed-off-by: Tvrtko Ursulin
>
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6235
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On 04/20/2015 05:22 PM, Daniel Vetter wrote:
On Mon, Apr 20, 2015 at 04:22:48PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Add Y tiling support to skl_do_mmio_flip.
Signed-off-by: Tvrtko Ursulin
Cc: Damien Lespiau
Cc: Sonika Jindal
Cc: Daniel Vetter
---
Looks like we completely mi
On 04/20/2015 09:16 AM, Daniel Vetter wrote:
On Fri, Apr 17, 2015 at 10:01:11PM -0700, Ben Widawsky wrote:
> On Thu, Mar 26, 2015 at 12:44:19PM -0700,
intel-gfx-requ...@lists.freedesktop.org wrote:
> > Send Intel-gfx mailing list submissions to
> > intel-gfx@lists.freedesktop.org
> >
> >
On Sat, Apr 18, 2015 at 12:04:18AM -0700, Todd Previte wrote:
> For test 4.2.2.5 to pass per the Link CTS Core 1.2 rev1.1 spec, the source
> device must attempt at least 7 times to read the EDID when it receives an
> I2C defer. The normal DRM code makes only 7 retries, regardless of whether
> or no
On Mon, Apr 20, 2015 at 01:50:48PM +0100, Chris Wilson wrote:
> On Mon, Apr 20, 2015 at 01:14:14PM +0100, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > Using imported objects should not leak i915 vmas (and vms).
> >
> > In practice this simulates Xorg importing fbcon and leaking (or not
On Mon, Apr 20, 2015 at 04:22:48PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Add Y tiling support to skl_do_mmio_flip.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Damien Lespiau
> Cc: Sonika Jindal
> Cc: Daniel Vetter
> ---
> Looks like we completely missed this completely parallel
On Mon, Apr 20, 2015 at 05:08:14PM +0530, Durgadoss R wrote:
> This patch creates a connector specific debugfs
> interface to read any particular DPCD register.
> The DPCD register address (hex format) is written
> to 'i915_dpcd_addr' interface and the corresponding
> value can be read from 'i915_d
On Fri, Apr 17, 2015 at 10:01:11PM -0700, Ben Widawsky wrote:
> On Thu, Mar 26, 2015 at 12:44:19PM -0700,
> intel-gfx-requ...@lists.freedesktop.org wrote:
> > Send Intel-gfx mailing list submissions to
> > intel-gfx@lists.freedesktop.org
> >
> > To subscribe or unsubscribe via the World Wide
On Fri, Apr 17, 2015 at 03:26:03PM +0200, Thomas Richter wrote:
> Hi Daniel, hi Ville,
>
> did you get this?
>
> Greetings,
> Thomas
>
> Signed-off-by: Thomas Richter
>
> This patch enables the (unfortunately undocumented) scaler of the
> NatSemi 2501 DVO found in the Fujitsu-Siemens S601
On Fri, Apr 17, 2015 at 04:49:18PM +0300, Mika Kuoppala wrote:
> Daniel Vetter writes:
>
> > On Tue, Apr 14, 2015 at 06:53:41PM +0100, Chris Wilson wrote:
> >> On Tue, Apr 14, 2015 at 07:11:25PM +0200, Daniel Vetter wrote:
> >> > On Tue, Apr 14, 2015 at 05:06:36PM +0100, Chris Wilson wrote:
> >>
On 04/18/2015 06:48 AM, Chris Wilson wrote:
On Fri, Apr 17, 2015 at 02:21:13PM -0700, yu@intel.com wrote:
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index de8c074..8f13e80 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b
On Fri, Apr 17, 2015 at 12:49:07PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
>commit ae6c4806927b8b0781ecc187aa16b10c820fc430
>Author: Daniel Vetter
>Date: Wed Aug 6 15:04:53 2014 +0200
>
>drm/i915: Only track real ppgtt for a context
>
> Changed the code but
Currently we have the problem that the decision whether ptes need to
be (re)written is splattered all over the codebase. Move all that into
i915_vma_bind. This needs a few changes:
- Just reuse the PIN_* flags for i915_vma_bind and do the conversion
to vma->bound in there to avoid duplicating the
On 04/18/2015 06:47 AM, Chris Wilson wrote:
On Fri, Apr 17, 2015 at 02:21:12PM -0700, yu@intel.com wrote:
> From: Alex Dai
>
> All gem objects used by GuC are pinned to ggtt space out of range
> [0, WOPCM size]. In GuC address space mapping, [0, WPOCM size] is
> used internally for its Boo
On Fri, Apr 17, 2015 at 04:49:18PM +0300, Mika Kuoppala wrote:
> Daniel Vetter writes:
>
> > On Tue, Apr 14, 2015 at 06:53:41PM +0100, Chris Wilson wrote:
> >> On Tue, Apr 14, 2015 at 07:11:25PM +0200, Daniel Vetter wrote:
> >> > On Tue, Apr 14, 2015 at 05:06:36PM +0100, Chris Wilson wrote:
> >>
On Fri, Apr 17, 2015 at 05:02:39PM +0300, Joonas Lahtinen wrote:
> On to, 2015-04-16 at 10:13 +0100, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > One month passed between posting a patch and it getting merged, and
> > unfortunately even though it still applies, it needs fixing to accoun
On Fri, Apr 17, 2015 at 01:00:28PM +0300, Ville Syrjälä wrote:
> On Fri, Apr 17, 2015 at 06:33:57AM +, R, Durgadoss wrote:
> > >-Original Message-
> > >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > >Sent: Thursday, April 16, 2015 8:03 PM
> > >To: Jani Nikula
> > >Cc: R,
On Thu, Apr 16, 2015 at 09:10:11AM -0700, Eric Caruso wrote:
> On Thu, Apr 16, 2015 at 8:58 AM, Rodrigo Vivi wrote:
> > I'm not sure that that property will be accepted...
> > if so it can be changed to toggle, but for now it is informative only
> > (DRM_MODE_PROP_IMMUTABLE).
> >
>
> Okay, that c
From: Tvrtko Ursulin
Add Y tiling support to skl_do_mmio_flip.
Signed-off-by: Tvrtko Ursulin
Cc: Damien Lespiau
Cc: Sonika Jindal
Cc: Daniel Vetter
---
Looks like we completely missed this completely parallel instance of plane
programming code when working on Y tiling support!
Will rotation
On Mon, Apr 20, 2015 at 03:56:09PM +0100, Tvrtko Ursulin wrote:
> >Will take a bit of judicious planning (like doing a self-copy on the dst
> >first to make sure it bound ahead of the leak and not reallocating the
> >batch handle)
>
> Hm.. not bad!
>
> >Or alternatively, we know the name of the f
On 04/20/2015 01:50 PM, Chris Wilson wrote:
On Mon, Apr 20, 2015 at 01:14:14PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Using imported objects should not leak i915 vmas (and vms).
In practice this simulates Xorg importing fbcon and leaking (or not) one vma
per Xorg startup cycle.
S
On Sat, 2015-04-18 at 08:27 +0100, Matthew Garrett wrote:
> On Mon, Apr 13, 2015 at 04:46:29PM -0700, Rodrigo Vivi wrote:
> > Another questions,
> >
> > Are you using powertop --auto-tune?
> >
> > If so, can you please try to repdoruce X slowness issue on these 2
> > scenarios:
> > 1. without do
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6234
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On 17 April 2015 at 18:52, Todd Previte wrote:
>
>
> On 4/17/2015 6:44 AM, Thomas Wood wrote:
>>
>> On 10 April 2015 at 16:54, Todd Previte wrote:
>>>
>>> This is the userspace component of the Displayport compliance testing
>>> software requried for compliance testing of the i915 driver. The REA
On Mon, Apr 20, 2015 at 02:11:39PM +0100, Tvrtko Ursulin wrote:
>
> On 04/20/2015 01:58 PM, Chris Wilson wrote:
> >On Mon, Apr 20, 2015 at 01:53:03PM +0100, Tvrtko Ursulin wrote:
> >>>No we can't do this, as it makes close sync and so can have disasterous
> >>>effects on performance (though mitiga
On 04/20/2015 01:58 PM, Chris Wilson wrote:
On Mon, Apr 20, 2015 at 01:53:03PM +0100, Tvrtko Ursulin wrote:
No we can't do this, as it makes close sync and so can have disasterous
effects on performance (though mitigated chiefly by userspace
agressively caching bo) and also the unbind is very l
Reviewed-by: Sivakumar Thulasimani
On 4/20/2015 5:08 PM, Durgadoss R wrote:
This patch creates a connector specific debugfs
interface to read any particular DPCD register.
The DPCD register address (hex format) is written
to 'i915_dpcd_addr' interface and the corresponding
value can be read fr
On Mon, Apr 20, 2015 at 01:53:03PM +0100, Tvrtko Ursulin wrote:
> >No we can't do this, as it makes close sync and so can have disasterous
> >effects on performance (though mitigated chiefly by userspace
> >agressively caching bo) and also the unbind is very likely to fail,
> >though admittedly the
On 04/20/2015 01:36 PM, Chris Wilson wrote:
On Mon, Apr 20, 2015 at 01:14:34PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
If a client instantiates a VMA against an imported object (flink) this VMA
will not get unbound when the object is closed.
This happens because the exporter holds
On Mon, Apr 20, 2015 at 01:14:14PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Using imported objects should not leak i915 vmas (and vms).
>
> In practice this simulates Xorg importing fbcon and leaking (or not) one vma
> per Xorg startup cycle.
>
> Signed-off-by: Tvrtko Ursulin
>
On Mon, Apr 20, 2015 at 01:14:34PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> If a client instantiates a VMA against an imported object (flink) this VMA
> will not get unbound when the object is closed.
>
> This happens because the exporter holds a reference count on the object and
From: Tvrtko Ursulin
If a client instantiates a VMA against an imported object (flink) this VMA
will not get unbound when the object is closed.
This happens because the exporter holds a reference count on the object and
will also keep a reference to the PPGTT VM.
In real life this happens with
From: Tvrtko Ursulin
Using imported objects should not leak i915 vmas (and vms).
In practice this simulates Xorg importing fbcon and leaking (or not) one vma
per Xorg startup cycle.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
tests/gem_ppgtt.c | 100 +++
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, April 17, 2015 3:30 PM
>To: R, Durgadoss
>Cc: Jani Nikula; intel-gfx@lists.freedesktop.org; Syrjala, Ville; Zanoni,
>Paulo R
>Subject: Re: [Intel-gfx] [PATCH v2] drm/i915: Add debugfs to read any
This patch creates a connector specific debugfs
interface to read any particular DPCD register.
The DPCD register address (hex format) is written
to 'i915_dpcd_addr' interface and the corresponding
value can be read from 'i915_dpcd_val' interface.
To write into a DPCD register, echo a value into
'
Hi Rodrigo,
Thank you for your email.
The problem here is that myself and others will be stuck. Our only choices are
to wait for Ubuntu 15.04 to come out and then install the new version of the
Intel drivers, or update 14.04 to 14.10 - which is a complete disaster as I've
already tried it befo
Op 15-04-15 om 16:34 schreef Maarten Lankhorst:
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_atomic_plane.c | 18 +--
> drivers/gpu/drm/i915/intel_display.c | 196
> --
> drivers/gpu/drm/i915/intel_sprite.c | 25 +---
> 3 files ch
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