From: Tvrtko Ursulin <tvrtko.ursu...@intel.com>

Add Y tiling support to skl_do_mmio_flip.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
Cc: Damien Lespiau <damien.lesp...@intel.com>
Cc: Sonika Jindal <sonika.jin...@intel.com>
Cc: Daniel Vetter <daniel.vet...@ffwll.ch>
---
Looks like we completely missed this completely parallel instance of plane
programming code when working on Y tiling support!

Will rotation need supporting here as well?

And what about the comment at intel_do_mmio_flip saying this was only
temporary code?
---
 drivers/gpu/drm/i915/intel_display.c | 23 +++++++++++++++++------
 1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index bac82d5..4d37f74 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10480,23 +10480,34 @@ static void skl_do_mmio_flip(struct intel_crtc 
*intel_crtc)
        struct drm_device *dev = intel_crtc->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
-       struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-       struct drm_i915_gem_object *obj = intel_fb->obj;
        const enum pipe pipe = intel_crtc->pipe;
        u32 ctl, stride;
 
        ctl = I915_READ(PLANE_CTL(pipe, 0));
        ctl &= ~PLANE_CTL_TILED_MASK;
-       if (obj->tiling_mode == I915_TILING_X)
+       switch (fb->modifier[0]) {
+       case DRM_FORMAT_MOD_NONE:
+               break;
+       case I915_FORMAT_MOD_X_TILED:
                ctl |= PLANE_CTL_TILED_X;
+               break;
+       case I915_FORMAT_MOD_Y_TILED:
+               ctl |= PLANE_CTL_TILED_Y;
+               break;
+       case I915_FORMAT_MOD_Yf_TILED:
+               ctl |= PLANE_CTL_TILED_YF;
+               break;
+       default:
+               MISSING_CASE(fb->modifier[0]);
+       }
 
        /*
         * The stride is either expressed as a multiple of 64 bytes chunks for
         * linear buffers or in number of tiles for tiled buffers.
         */
-       stride = fb->pitches[0] >> 6;
-       if (obj->tiling_mode == I915_TILING_X)
-               stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
+       stride = fb->pitches[0] /
+                intel_fb_stride_alignment(dev, fb->modifier[0],
+                                          fb->pixel_format);
 
        /*
         * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
-- 
2.3.5

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