[Intel-gfx] [PATCH 1/4] drm/i915: Split SSEU init into functions by platform

From: Jeff McGee Signed-off-by: Jeff McGee --- drivers/gpu/drm/i915/i915_dma.c | 234 +--- 1 file changed, 125 insertions(+), 109 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index ec661fe..9691f0f 100644 --- a/

[Intel-gfx] [PATCH 2/4] drm/i915/bxt: Determine BXT slice/subslice/EU info

From: Jeff McGee Modify the Gen9 SSEU info initialization logic to support Broxton. Broxton reuses the SKL fuse registers but has at most 1 slice and 6 EU per subslice. Signed-off-by: Jeff McGee --- drivers/gpu/drm/i915/i915_dma.c | 47 ++--- drivers/gpu/drm

[Intel-gfx] [PATCH 3/4] drm/i915: Split-up SSEU device status by platform

From: Jeff McGee Signed-off-by: Jeff McGee --- drivers/gpu/drm/i915/i915_debugfs.c | 172 +--- 1 file changed, 100 insertions(+), 72 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 91c945b..c5746ef 10064

[Intel-gfx] [PATCH 4/4] drm/i915/bxt: Support BXT in SSEU device status dump

From: Jeff McGee Modify the Gen9 SSEU device status logic to support Broxton. Broxton reuses the Skylake power gate acknowledgment registers but has at most 1 slice and 3 subslices. Broxton supports subslice power gating within its single slice. Signed-off-by: Jeff McGee --- drivers/gpu/drm/i9

[Intel-gfx] [PATCH 0/4 v2] BXT basic slice/subslice/EU stuff

From: Jeff McGee Reworked this set by first breaking out the existing logic into more manageable per-device functions as suggested by Daniel. Then added Broxton support within the Skylake logic, also suggested by Daniel. These patches are dependent on the initial BXT enabling set from Imre, part

[Intel-gfx] [PATCH i-g-t] tests/pm_sseu: Require Gen8+ early in setup

From: Jeff McGee Pre-Gen8 devices should be skipped early instead of failing when test resources are not found. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89822 Signed-off-by: Jeff McGee --- tests/pm_sseu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/pm_sseu.c b/tes

Re: [Intel-gfx] [PATCH] drm: Add integer overflow checking to transitional plane helpers

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6130 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -2

[Intel-gfx] [PATCH] drm: Add integer overflow checking to transitional plane helpers

Add tests for destination rectangle integer overflow before calling the driver's check function. This will ensure that the transitional plane helpers match the behavior of the full atomic helpers by always returning -ERANGE for planes positioned beyond INT_MAX. Note that the legacy SetPlane ioctl

[Intel-gfx] Broadwell i915 VT behavior on resume from sleep

Running 3.19.3 on a Broadwell ThinkPad X250. I'm running into some unfortunate behaviour. When I resume from sleep, the GPU occasionally hangs: https://bugs.freedesktop.org/show_bug.cgi?id=89896 And I also have this issue with the virtual terminals after I resume (reproduced by doing a suspend/r

[Intel-gfx] [PATCH v2 06/18] drm/i915: Defer default hardware context initialisation until first open

From: Dave Gordon In order to fully initialise the default contexts, we have to execute batchbuffer commands on the GPU engines. But we can't do that until any required firmware has been loaded, which may not be possible during driver load, because the filesystem(s) containing the firmware may no

[Intel-gfx] [PATCH v2 12/18] drm/i915: Interrupt routing for GuC scheduler

From: Alex Dai Turn on interrupt steering to route necessary interrupts to GuC. Issue: VIZ-4884 Signed-off-by: Dave Gordon Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/i915_reg.h| 11 -- drivers/gpu/drm/i915/intel_guc.h | 7 drivers/gpu/drm/i915/intel_guc_s

[Intel-gfx] [PATCH v2 02/18] drm/i915: Add i915_gem_object_write() to i915_gem.c

From: "Michael H. Nguyen" i915_gem_object_write() is a generic function to copy data from user memory to gem object. Issue: VIZ-4884 Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/i915_gem.c | 30 ++ 2 files changed, 33 in

[Intel-gfx] [PATCH v2 03/18] drm/i915: Unified firmware loading mechanism

From: Dave Gordon Factor out the common code of loading firmware into a new file, leaving only the uC-specific parts in the GuC loaders. Issue: VIZ-4884 Signed-off-by: Alex Dai Signed-off-by: Dave Gordon --- drivers/gpu/drm/i915/Makefile | 3 + drivers/gpu/drm/i915/intel_uc_loader.

[Intel-gfx] [PATCH v2 18/18] Documentation/drm: kerneldoc for GuC

From: Alex Dai Add overview design of GuC, plus some key points related to the implementation. Signed-off-by: Alex Dai --- Documentation/DocBook/drm.tmpl | 19 +++ 1 file changed, 19 insertions(+) diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl ind

[Intel-gfx] [PATCH v2 13/18] drm/i915: Enable commands submission via GuC

From: Alex Dai Add functions to submit work queue item and ring the door bell. GuC TLB needs to be invalided if LRC context changes. Issue: VIZ-4884 Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/intel_guc.h | 3 + drivers/gpu/drm/i915/intel_guc_client.c| 182

[Intel-gfx] [PATCH v2 04/18] drm/i915: GuC firmware loader

From: Alex Dai Add GuC firmware loader. It uses the unified firmware loader to fetch firmware blob first, then load to hw in driver main thread. Issue: VIZ-4884 Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915_dma.c | 6 + driver

[Intel-gfx] [PATCH v2 09/18] drm/i915: Add functions to allocate / release gem obj for GuC

From: Alex Dai All gem objects used by GuC are pinned to ggtt space out of range [0, WOPCM size]. In GuC address space mapping, [0, WPOCM size] is used internally for its Boot ROM, SRAM etc. Currently this WPOCM size is 512K. This is done by using of PIN_OFFSET_BIAS. Issue: VIZ-4884 Signed-off-b

[Intel-gfx] [PATCH v2 16/18] drm/i915: Ring Context allocating for GuC

From: Alex Dai GuC firmware uses the one page after Ring Context as shared data. However, GuC uses same offset to address this page for all rings. So we have to allocate same size of lrc context for all rings. Also, reduce ring buffer size to 4 pages. In GuC, work queue tail is referenced by 11

[Intel-gfx] [PATCH v2 17/18] drm/i915: Taking forcewake during GuC load.

From: Sagar Kamble The firmware loader will use GuC DMA engine to move data from ggtt to WOPCM. Need to take forcewake before GuC loading. Issue: VIZ-4884 Change-Id: Ie422fc1e122933b161ff63cab23622197e6bba54 Signed-off-by: Sagar Kamble --- drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++ 1 fil

[Intel-gfx] [PATCH v2 15/18] drm/i915: Enable GuC firmware log

From: Alex Dai Allocate a gem obj to hold GuC log data. Also a debugfs interface (i915_guc_log_dump) is provided to print out the log content. Issue: VIZ-4884 Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/i915_debugfs.c| 29 + drivers/gpu/drm/i915/i915_drv.h|

[Intel-gfx] [PATCH v2 07/18] drm/i915: Move execlists defines from .c to .h

From: "Michael H. Nguyen" Move defines from intel_lrc.c to i915_reg.h so they are accessible by the guc files Issue: VIZ-4884 Signed-off-by: Michael H. Nguyen --- drivers/gpu/drm/i915/i915_reg.h | 68 drivers/gpu/drm/i915/intel_lrc.c | 67 -

[Intel-gfx] [PATCH v2 05/18] drm/i915: Add firmware version check

From: Alex Dai Set the firmware version that required by HW. Driver sets required version according to platform. After firmware is loaded but before send to HW, the major.minor version is read from CSS header field, which is 17th DWORD currently. The major version must be same; the minor version

[Intel-gfx] [PATCH v2 14/18] drm/i915: debugfs of GuC status

From: Alex Dai Now print out Bootrom, uKernel and MIA Core status. The scratch reg 0 & 15 are used for communication between driver and firmware. Their status is also printed out. Issue: VIZ-4884 Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/i915_debugfs.c | 73 +

[Intel-gfx] [PATCH v2 10/18] drm/i915: Functions to support command submission via GuC

From: Alex Dai To enable GuC command submission / scheduling, we need to setup firmware initializaion properly. i915.enable_guc_scheduling is introduced to enable / disable GuC submission. Issue: VIZ-4884 Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/Makefile | 3 +- drivers/g

[Intel-gfx] [PATCH v2 08/18] drm/i915: Make several execlist helper functions external

From: Alex Dai These functions will be used by GuC scheduler. Issue: VIZ-4884 Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/intel_lrc.c | 6 +++--- drivers/gpu/drm/i915/intel_lrc.h | 3 +++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/dri

[Intel-gfx] [PATCH v2 11/18] drm/i915: Integration of GuC client

From: Alex Dai Implementation of GuC client. A GuC client has its own doorbell and workqueue. It maintains the doorbell cache line, process description object and work queue item. A default guc_client is created to do the in-order legacy execlist submission. Issue: VIZ-4884 Signed-off-by: Alex

[Intel-gfx] [PATCH v2 00/18] *** Command submission via GuC for SKL ***

From: Alex Dai v2: 1. Add kernel-doc patch. All comments here have been moved into source code. 2. Change the way to load fw because a signed firmware has different layout. 3. One previous patch to notify GuC about RC6 feature is dropped for future submission. Need to double check the potentia

[Intel-gfx] [PATCH v2 01/18] drm/i915: Add guc firmware interface headers

From: Alex Dai These are the subset of GuC interface that we are going to use to enable command submission through GuC. The definition of these struct and bit setting need to match those in firmware. Issue: VIZ-4884 Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/intel_guc_api.h | 217 +++

[Intel-gfx] [PATCH 03/11] drm/i915: Add a delay in Displayport AUX transactions for compliance testing

The Displayport Link Layer Compliance Testing Specification 1.2 rev 1.1 specifies that repeated AUX transactions after a failure (no response / invalid response) must have a minimum delay of 400us before the resend can occur. Tests 4.2.1.1 and 4.2.1.2 are two tests that require this specifically.

[Intel-gfx] [QA 2015/04/03 ww14] Testing report for `drm-intel-testing` (was: Updated -next)

Summary We covered the platforms: Skylake, Braswell, Broadwell, Haswell, Baytrail, Ivybridge. In this circle, 3 new bugs have been found in manual testing and 3 new bugs have been found in nightly testing. 89872 - [ HSW Regression ] VGA was whi

Re: [Intel-gfx] [PATCH] drm/i915: Pin tiled objects for L-shaped configs

On Thu, Nov 20, 2014 at 09:26:30AM +0100, Daniel Vetter wrote: > diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c > b/drivers/gpu/drm/i915/i915_gem_tiling.c > index 749ab485569e..03c675a4476e 100644 > --- a/drivers/gpu/drm/i915/i915_gem_tiling.c > +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c >

Re: [Intel-gfx] [PATCH] drm: Defer disabling the vblank IRQ until the next interrupt (for instant-off)

On Fri, Apr 03, 2015 at 11:20:20AM +0900, Michel Dänzer wrote: > On 02.04.2015 20:34, Chris Wilson wrote: > > On vblank instant-off systems, we can get into a situation where the cost > > of enabling and disabling the vblank IRQ around a drmWaitVblank query > > dominates. However, we know that if t

Re: [Intel-gfx] [PATCH] Correct drm display mode table about 1856x1392 @75Hz mode

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6127 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -1